Changeset 106751 in vbox for trunk/src/VBox/Disassembler/testcase
- Timestamp:
- Oct 28, 2024 2:00:52 PM (6 months ago)
- svn:sync-xref-src-repo-rev:
- 165635
- File:
-
- 1 edited
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- Unmodified
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trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S
r106746 r106751 1403 1403 1404 1404 1405 ldr b0, [x1, x2] 1406 ldr b31, [x1, x2] 1407 ldr b0, [x1, x2, SXTX #0] 1408 ldr b0, [x1, x2, LSL #0] ; UXTX 1409 ldr b0, [x1, x2, SXTX #0] 1410 ldr b31, [x1, w2, UXTW #0] 1411 ldr b31, [x1, w2, SXTW #0] 1412 ldr b31, [x1, w2, UXTW #0] 1413 ldr b31, [x1, w2, SXTW #0] 1414 1415 ldr b0, [sp, x2] 1416 ldr b31, [sp, x2] 1417 ldr b0, [sp, x2, SXTX #0] 1418 ldr b0, [sp, x2, LSL #0] ; UXTX 1419 ldr b0, [sp, x2, SXTX #0] 1420 ldr b31, [sp, w2, UXTW #0] 1421 ldr b31, [sp, w2, SXTW #0] 1422 ldr b31, [sp, w2, UXTW #0] 1423 ldr b31, [sp, w2, SXTW #0] 1424 1425 1426 ldr h0, [x1, x2] 1427 ldr h31, [x1, x2] 1428 ldr h0, [x1, x2, SXTX #1] 1429 ldr h0, [x1, x2, LSL #1] ; UXTX 1430 ldr h0, [x1, x2, SXTX #1] 1431 ldr h31, [x1, w2, UXTW #0] 1432 ldr h31, [x1, w2, SXTW #0] 1433 ldr h31, [x1, w2, UXTW #1] 1434 ldr h31, [x1, w2, SXTW #1] 1435 1436 ldr h0, [sp, x2] 1437 ldr h31, [sp, x2] 1438 ldr h0, [sp, x2, SXTX #1] 1439 ldr h0, [sp, x2, LSL #1] ; UXTX 1440 ldr h0, [sp, x2, SXTX #1] 1441 ldr h31, [sp, w2, UXTW #0] 1442 ldr h31, [sp, w2, SXTW #0] 1443 ldr h31, [sp, w2, UXTW #1] 1444 ldr h31, [sp, w2, SXTW #1] 1445 1446 1447 ldr s0, [x1, x2] 1448 ldr s31, [x1, x2] 1449 ldr s0, [x1, x2, SXTX #2] 1450 ldr s0, [x1, x2, LSL #2] ; UXTX 1451 ldr s0, [x1, x2, SXTX #2] 1452 ldr s31, [x1, w2, UXTW #0] 1453 ldr s31, [x1, w2, SXTW #0] 1454 ldr s31, [x1, w2, UXTW #2] 1455 ldr s31, [x1, w2, SXTW #2] 1456 1457 ldr s0, [sp, x2] 1458 ldr s31, [sp, x2] 1459 ldr s0, [sp, x2, SXTX #2] 1460 ldr s0, [sp, x2, LSL #2] ; UXTX 1461 ldr s0, [sp, x2, SXTX #2] 1462 ldr s31, [sp, w2, UXTW #0] 1463 ldr s31, [sp, w2, SXTW #0] 1464 ldr s31, [sp, w2, UXTW #2] 1465 ldr s31, [sp, w2, SXTW #2] 1466 1467 1468 ldr d0, [x1, x2] 1469 ldr d31, [x1, x2] 1470 ldr d0, [x1, x2, SXTX #3] 1471 ldr d0, [x1, x2, LSL #3] ; UXTX 1472 ldr d0, [x1, x2, SXTX #3] 1473 ldr d31, [x1, w2, UXTW #0] 1474 ldr d31, [x1, w2, SXTW #0] 1475 ldr d31, [x1, w2, UXTW #3] 1476 ldr d31, [x1, w2, SXTW #3] 1477 1478 ldr d0, [sp, x2] 1479 ldr d31, [sp, x2] 1480 ldr d0, [sp, x2, SXTX #3] 1481 ldr d0, [sp, x2, LSL #3] ; UXTX 1482 ldr d0, [sp, x2, SXTX #3] 1483 ldr d31, [sp, w2, UXTW #0] 1484 ldr d31, [sp, w2, SXTW #0] 1485 ldr d31, [sp, w2, UXTW #3] 1486 ldr d31, [sp, w2, SXTW #3] 1487 1488 1489 ldr q0, [x1, x2] 1490 ldr q31, [x1, x2] 1491 ldr q0, [x1, x2, SXTX #4] 1492 ldr q0, [x1, x2, LSL #4] ; UXTX 1493 ldr q0, [x1, x2, SXTX #4] 1494 ldr q31, [x1, w2, UXTW #0] 1495 ldr q31, [x1, w2, SXTW #0] 1496 ldr q31, [x1, w2, UXTW #4] 1497 ldr q31, [x1, w2, SXTW #4] 1498 1499 ldr q0, [sp, x2] 1500 ldr q31, [sp, x2] 1501 ldr q0, [sp, x2, SXTX #4] 1502 ldr q0, [sp, x2, LSL #4] ; UXTX 1503 ldr q0, [sp, x2, SXTX #4] 1504 ldr q31, [sp, w2, UXTW #0] 1505 ldr q31, [sp, w2, SXTW #0] 1506 ldr q31, [sp, w2, UXTW #4] 1507 ldr q31, [sp, w2, SXTW #4] 1508 1509 1405 1510 ; SIMD memory stores 1406 1511 str b0, [x0] … … 1433 1538 str q31, [sp] 1434 1539 str q31, [sp, #65520] 1540 1541 1542 str b0, [x1, x2] 1543 str b31, [x1, x2] 1544 str b0, [x1, x2, SXTX #0] 1545 str b0, [x1, x2, LSL #0] ; UXTX 1546 str b0, [x1, x2, SXTX #0] 1547 str b31, [x1, w2, UXTW #0] 1548 str b31, [x1, w2, SXTW #0] 1549 str b31, [x1, w2, UXTW #0] 1550 str b31, [x1, w2, SXTW #0] 1551 1552 str b0, [sp, x2] 1553 str b31, [sp, x2] 1554 str b0, [sp, x2, SXTX #0] 1555 str b0, [sp, x2, LSL #0] ; UXTX 1556 str b0, [sp, x2, SXTX #0] 1557 str b31, [sp, w2, UXTW #0] 1558 str b31, [sp, w2, SXTW #0] 1559 str b31, [sp, w2, UXTW #0] 1560 str b31, [sp, w2, SXTW #0] 1561 1562 1563 str h0, [x1, x2] 1564 str h31, [x1, x2] 1565 str h0, [x1, x2, SXTX #1] 1566 str h0, [x1, x2, LSL #1] ; UXTX 1567 str h0, [x1, x2, SXTX #1] 1568 str h31, [x1, w2, UXTW #0] 1569 str h31, [x1, w2, SXTW #0] 1570 str h31, [x1, w2, UXTW #1] 1571 str h31, [x1, w2, SXTW #1] 1572 1573 str h0, [sp, x2] 1574 str h31, [sp, x2] 1575 str h0, [sp, x2, SXTX #1] 1576 str h0, [sp, x2, LSL #1] ; UXTX 1577 str h0, [sp, x2, SXTX #1] 1578 str h31, [sp, w2, UXTW #0] 1579 str h31, [sp, w2, SXTW #0] 1580 str h31, [sp, w2, UXTW #1] 1581 str h31, [sp, w2, SXTW #1] 1582 1583 1584 str s0, [x1, x2] 1585 str s31, [x1, x2] 1586 str s0, [x1, x2, SXTX #2] 1587 str s0, [x1, x2, LSL #2] ; UXTX 1588 str s0, [x1, x2, SXTX #2] 1589 str s31, [x1, w2, UXTW #0] 1590 str s31, [x1, w2, SXTW #0] 1591 str s31, [x1, w2, UXTW #2] 1592 str s31, [x1, w2, SXTW #2] 1593 1594 str s0, [sp, x2] 1595 str s31, [sp, x2] 1596 str s0, [sp, x2, SXTX #2] 1597 str s0, [sp, x2, LSL #2] ; UXTX 1598 str s0, [sp, x2, SXTX #2] 1599 str s31, [sp, w2, UXTW #0] 1600 str s31, [sp, w2, SXTW #0] 1601 str s31, [sp, w2, UXTW #2] 1602 str s31, [sp, w2, SXTW #2] 1603 1604 1605 str d0, [x1, x2] 1606 str d31, [x1, x2] 1607 str d0, [x1, x2, SXTX #3] 1608 str d0, [x1, x2, LSL #3] ; UXTX 1609 str d0, [x1, x2, SXTX #3] 1610 str d31, [x1, w2, UXTW #0] 1611 str d31, [x1, w2, SXTW #0] 1612 str d31, [x1, w2, UXTW #3] 1613 str d31, [x1, w2, SXTW #3] 1614 1615 str d0, [sp, x2] 1616 str d31, [sp, x2] 1617 str d0, [sp, x2, SXTX #3] 1618 str d0, [sp, x2, LSL #3] ; UXTX 1619 str d0, [sp, x2, SXTX #3] 1620 str d31, [sp, w2, UXTW #0] 1621 str d31, [sp, w2, SXTW #0] 1622 str d31, [sp, w2, UXTW #3] 1623 str d31, [sp, w2, SXTW #3] 1624 1625 1626 str q0, [x1, x2] 1627 str q31, [x1, x2] 1628 str q0, [x1, x2, SXTX #4] 1629 str q0, [x1, x2, LSL #4] ; UXTX 1630 str q0, [x1, x2, SXTX #4] 1631 str q31, [x1, w2, UXTW #0] 1632 str q31, [x1, w2, SXTW #0] 1633 str q31, [x1, w2, UXTW #4] 1634 str q31, [x1, w2, SXTW #4] 1635 1636 str q0, [sp, x2] 1637 str q31, [sp, x2] 1638 str q0, [sp, x2, SXTX #4] 1639 str q0, [sp, x2, LSL #4] ; UXTX 1640 str q0, [sp, x2, SXTX #4] 1641 str q31, [sp, w2, UXTW #0] 1642 str q31, [sp, w2, SXTW #0] 1643 str q31, [sp, w2, UXTW #4] 1644 str q31, [sp, w2, SXTW #4] 1435 1645 1436 1646
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