Changeset 106756 in vbox

Timestamp:

Oct 28, 2024 2:55:43 PM (5 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165640

Message:

Disassembler: Decode SIMD ldr/str (immediate post index) instructions, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmTables-armv8-a64-ld-st.cpp.h (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (2 diffs)

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h

@@ -341 +341 @@
 
 
+/* SIMD STR/LDR */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPostIndexSimd)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize,        30,  2, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12,  9, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed,      0,  0, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegImmPostIndexSimd128)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128,      0,  0, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12,  9, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed,      0,  0, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPostIndexSimd)
+    DIS_ARMV8_OP(           0x3c000400, "str",             OP_ARMV8_A64_STR,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x3c400400, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP_ALT_DECODE(0x3c800400, "str",             OP_ARMV8_A64_STR,       DISOPTYPE_HARMLESS, LdStRegImmPostIndexSimd128), /** @todo size == 0. */
+    DIS_ARMV8_OP_ALT_DECODE(0x3cc00400, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS, LdStRegImmPostIndexSimd128), /** @todo size == 0. */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPostIndexSimd, 0x3fe00c00 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeNop,
+                                       RT_BIT_32(22) | RT_BIT_32(23), 22);
+
+
 /*
  * C4.1.94.26 - Loads and Stores - Load/Store register (immediate post-indexed) variants
@@ -353 +376 @@
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPostIndex)
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndexGpr),
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPostIndexSimd),
 DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPostIndex, RT_BIT_32(26), 26);
 

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -1562 +1562 @@
 
 
+        ldr b0, [x28], #0
+        ldr b0, [x28], #-256
+        ldr b0, [x28], #255
+
+        ldr b31, [sp], #0
+        ldr b31, [sp], #-256
+        ldr b31, [sp], #255
+
+        ldr h0, [x28], #0
+        ldr h0, [x28], #-256
+        ldr h0, [x28], #255
+
+        ldr h31, [sp], #0
+        ldr h31, [sp], #-256
+        ldr h31, [sp], #255
+
+        ldr s0, [x28], #0
+        ldr s0, [x28], #-256
+        ldr s0, [x28], #255
+
+        ldr s31, [sp], #0
+        ldr s31, [sp], #-256
+        ldr s31, [sp], #255
+
+        ldr d0, [x28], #0
+        ldr d0, [x28], #-256
+        ldr d0, [x28], #255
+
+        ldr d31, [sp], #0
+        ldr d31, [sp], #-256
+        ldr d31, [sp], #255
+
+        ldr q0, [x28], #0
+        ldr q0, [x28], #-256
+        ldr q0, [x28], #255
+
+        ldr q31, [sp], #0
+        ldr q31, [sp], #-256
+        ldr q31, [sp], #255
+
+
         ; SIMD memory stores
         str b0, [x0]
@@ -1751 +1792 @@
         stnp q30, q31, [x0, #-1024]
         stnp q23, q24, [x0, #1008]
+
+
+        str b0, [x28], #0
+        str b0, [x28], #-256
+        str b0, [x28], #255
+
+        str b31, [sp], #0
+        str b31, [sp], #-256
+        str b31, [sp], #255
+
+        str h0, [x28], #0
+        str h0, [x28], #-256
+        str h0, [x28], #255
+
+        str h31, [sp], #0
+        str h31, [sp], #-256
+        str h31, [sp], #255
+
+        str s0, [x28], #0
+        str s0, [x28], #-256
+        str s0, [x28], #255
+
+        str s31, [sp], #0
+        str s31, [sp], #-256
+        str s31, [sp], #255
+
+        str d0, [x28], #0
+        str d0, [x28], #-256
+        str d0, [x28], #255
+
+        str d31, [sp], #0
+        str d31, [sp], #-256
+        str d31, [sp], #255
+
+        str q0, [x28], #0
+        str q0, [x28], #-256
+        str q0, [x28], #255
+
+        str q31, [sp], #0
+        str q31, [sp], #-256
+        str q31, [sp], #255