Changeset 106757 in vbox for trunk/src/VBox/Disassembler

Timestamp:

Oct 28, 2024 2:59:05 PM (3 months ago)

Author:

vboxsync

Message:

Disassembler: Decode SIMD ldr/str (immediate pre index) instructions, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmTables-armv8-a64-ld-st.cpp.h (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (2 diffs)

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h

@@ -292 +292 @@
 
 
+/* SIMD STR/LDR */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegImmPreIndexSimd)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize,        30,  2, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12,  9, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed,       0,  0, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegImmPreIndexSimd128)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128,      0,  0, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12,  9, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPreIndexed,       0,  0, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegImmPreIndexSimd)
+    DIS_ARMV8_OP(           0x3c000c00, "str",             OP_ARMV8_A64_STR,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x3c400c00, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP_ALT_DECODE(0x3c800c00, "str",             OP_ARMV8_A64_STR,       DISOPTYPE_HARMLESS, LdStRegImmPreIndexSimd128), /** @todo size == 0. */
+    DIS_ARMV8_OP_ALT_DECODE(0x3cc00c00, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS, LdStRegImmPreIndexSimd128), /** @todo size == 0. */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegImmPreIndexSimd, 0x3fe00c00 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeNop,
+                                       RT_BIT_32(22) | RT_BIT_32(23), 22);
+
+
 /*
  * C4.1.94.28 - Loads and Stores - Load/Store register (immediate pre-indexed) variants
@@ -304 +327 @@
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegImmPreIndex)
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndexGpr),
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegImmPreIndexSimd),
 DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegImmPreIndex, RT_BIT_32(26), 26);
 

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -1603 +1603 @@
 
 
+        ldr b0, [x28, #0]!
+        ldr b0, [x28, #-256]!
+        ldr b0, [x28, #255]!
+
+        ldr b31, [sp, #0]!
+        ldr b31, [sp, #-256]!
+        ldr b31, [sp, #255]!
+
+        ldr h0, [x28, #0]!
+        ldr h0, [x28, #-256]!
+        ldr h0, [x28, #255]!
+
+        ldr h31, [sp, #0]!
+        ldr h31, [sp, #-256]!
+        ldr h31, [sp, #255]!
+
+        ldr s0, [x28, #0]!
+        ldr s0, [x28, #-256]!
+        ldr s0, [x28, #255]!
+
+        ldr s31, [sp, #0]!
+        ldr s31, [sp, #-256]!
+        ldr s31, [sp, #255]!
+
+        ldr d0, [x28, #0]!
+        ldr d0, [x28, #-256]!
+        ldr d0, [x28, #255]!
+
+        ldr d31, [sp, #0]!
+        ldr d31, [sp, #-256]!
+        ldr d31, [sp, #255]!
+
+        ldr q0, [x28, #0]!
+        ldr q0, [x28, #-256]!
+        ldr q0, [x28, #255]!
+
+        ldr q31, [sp, #0]!
+        ldr q31, [sp, #-256]!
+        ldr q31, [sp, #255]!
+
+
         ; SIMD memory stores
         str b0, [x0]
@@ -1833 +1874 @@
         str q31, [sp], #-256
         str q31, [sp], #255
+
+
+        str b0, [x28, #0]!
+        str b0, [x28, #-256]!
+        str b0, [x28, #255]!
+
+        str b31, [sp, #0]!
+        str b31, [sp, #-256]!
+        str b31, [sp, #255]!
+
+        str h0, [x28, #0]!
+        str h0, [x28, #-256]!
+        str h0, [x28, #255]!
+
+        str h31, [sp, #0]!
+        str h31, [sp, #-256]!
+        str h31, [sp, #255]!
+
+        str s0, [x28, #0]!
+        str s0, [x28, #-256]!
+        str s0, [x28, #255]!
+
+        str s31, [sp, #0]!
+        str s31, [sp, #-256]!
+        str s31, [sp, #255]!
+
+        str d0, [x28, #0]!
+        str d0, [x28, #-256]!
+        str d0, [x28, #255]!
+
+        str d31, [sp, #0]!
+        str d31, [sp, #-256]!
+        str d31, [sp, #255]!
+
+        str q0, [x28, #0]!
+        str q0, [x28, #-256]!
+        str q0, [x28, #255]!
+
+        str q31, [sp, #0]!
+        str q31, [sp, #-256]!
+        str q31, [sp, #255]!