Changeset 106768 in vbox

Timestamp:

Oct 29, 2024 11:16:24 AM (5 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165656

Message:

Disassembler: Decode ldr/ldrsw (literal) instructions, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmCore-armv8.cpp (modified) (1 diff)
• DisasmTables-armv8-a64-ld-st.cpp.h (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (1 diff)

trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp

@@ -198 +198 @@
 DECLINLINE(int32_t) disArmV8ExtractBitVecFromInsnSignExtend(uint32_t u32Insn, uint8_t idxBitStart, uint8_t cBits)
 {
-    uint32_t fMask = RT_BIT_32(idxBitStart + cBits) - 1;
-    uint32_t fSign = ~(UINT32_MAX & (RT_BIT_32(cBits - 1) - 1));
-    uint32_t fValue = (u32Insn & fMask) >> idxBitStart;
-    if (fValue & fSign)
-        return (int32_t)(fValue | fSign);
-
-    return (int32_t)fValue;
+    uint32_t const fMask = RT_BIT_32(cBits) - 1;
+    uint32_t const fSignBit = RT_BIT_32(cBits - 1);
+    uint32_t const u32 = (u32Insn >> idxBitStart) & fMask;
+    return (int32_t)((u32 ^ fSignBit) - fSignBit);
 }
 

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h

@@ -997 +997 @@
 
 
+/* LDR/LDRSW/PRFM - literal variant. */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdRegLiteralGpr)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,           0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel,          5, 19, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdRegLiteralGpr)
+ DIS_ARMV8_OP_EX(0x18000000, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_32BIT),
+ DIS_ARMV8_OP_EX(0x58000000, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+ DIS_ARMV8_OP_EX(0x98000000, "ldrsw",           OP_ARMV8_A64_LDRSW,     DISOPTYPE_HARMLESS, DISARMV8INSNCLASS_F_FORCED_64BIT),
+    INVALID_OPCODE, /** @todo PRFM */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdRegLiteralGpr, 0xff000000 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeNop,
+                                       RT_BIT_32(30) | RT_BIT_32(31), 30);
+
+
+/* SIMD LDR - literal variant. */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdRegLiteralSimd)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize32,       0,  0, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel,              5, 19, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdRegLiteralSimd64)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize64,       0,  0, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel,              5, 19, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdRegLiteralSimd128)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128,      0,  0, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseImmRel,              5, 19, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdRegLiteralSimd)
+    DIS_ARMV8_OP(           0x1c000000, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP_ALT_DECODE(0x5c000000, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS, LdRegLiteralSimd64),
+    DIS_ARMV8_OP_ALT_DECODE(0x9c000000, "ldr",             OP_ARMV8_A64_LDR,       DISOPTYPE_HARMLESS, LdRegLiteralSimd128),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdRegLiteralSimd, 0xff000000 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeNop,
+                                       RT_BIT_32(30) | RT_BIT_32(31), 30);
+
+
+/*
+ * C4.1.94.19 - Loads and Stores - Load register (literal) variants
+ *
+ * Differentiate further based on the VR field.
+ *
+ *     Bit  26
+ *     +-------------------------------------------
+ *           0 GPR variants.
+ *           1 SIMD/FP variants
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdRegLiteral)
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdRegLiteralGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdRegLiteralSimd),
+DIS_ARMV8_DECODE_MAP_DEFINE_END(LdRegLiteral, RT_BIT_32(26), 26);
+
+
+/**
+ * C4.1.94 - Loads and Stores
+ *
+ * Differentiate between Load register (literal) and the other classes based on op2<14> (bit 24).
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStBit28_1_Bit29_0)
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdRegLiteral),
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,         /** @todo RCW compare and swap / 128-bit atomic memory instructions / GCS load/store / Load/store memory tags / LDIAPP/STILP / LDAPR/STLR / Memory Copy and Set */
+DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(LdStBit28_1_Bit29_0, 24);
+
+
 /*
  * C4.1.94 - Loads and Stores
@@ -1014 +1077 @@
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOp0Lo)
     DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStBit28_1_Bit29_0),
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPair),
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStReg),

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -3573 +3573 @@
 
         ;
+        ; LDR literal variants
+        ;
+
+        ldr w0, #0
+        ldr wzr, #0xffffc
+        ldr wzr, #-0xffffc
+
+        ldr x0, #0
+        ldr xzr, #0xffffc
+        ldr xzr, #-0xffffc
+
+        ldrsw x0, #0
+        ldrsw xzr, #0xffffc
+        ldrsw xzr, #-0xffffc
+
+        ldr s0, #0
+        ldr s31, #0xffffc
+        ldr s31, #-0xffffc
+
+        ldr d0, #0
+        ldr d31, #0xffffc
+        ldr d31, #-0xffffc
+
+        ldr q0, #0
+        ldr q31, #0xffffc
+        ldr q31, #-0xffffc
+
+        ;
         ; Keep last so the testcase can catch errors in
         ; the disassembly of the last instruction.