Changeset 106772 in vbox

Timestamp:

Oct 29, 2024 2:07:47 PM (4 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165661

Message:

Disassembler: Compare and swap instructions, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmTables-armv8-a64-ld-st.cpp.h (modified) (3 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (2 diffs)

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h

@@ -1116 +1116 @@
 
 /**
- * C4.1.94 - Loads and Stores
+ * C4.1.94 - Loads and Stores - Compare and swap
  *
  * Differentiate between Load register (literal) and the other classes based on op2<14> (bit 24).
@@ -1124 +1124 @@
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStBit28_1_Bit29_0_Bit24_1),
 DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(LdStBit28_1_Bit29_0, 24);
+
+
+/* C4.1.94.14 - Loads and Stores - Compare and swap */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStCas)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32,       16,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32,        0,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,      5,  5, 2 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStCas64)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64,       16,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64,        0,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,      5,  5, 2 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStCas)
+    DIS_ARMV8_OP(           0x08a07c00, "casb",            OP_ARMV8_A64_CASB,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x08a0fc00, "caslb",           OP_ARMV8_A64_CASLB,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x08e07c00, "casab",           OP_ARMV8_A64_CASAB,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x08e0fc00, "casalb",          OP_ARMV8_A64_CASALB,    DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x48a07c00, "cash",            OP_ARMV8_A64_CASH,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x48a0fc00, "caslh",           OP_ARMV8_A64_CASLH,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x48e07c00, "casah",           OP_ARMV8_A64_CASAH,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x48e0fc00, "casalh",          OP_ARMV8_A64_CASALH,    DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x88a07c00, "cas",             OP_ARMV8_A64_CAS,       DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x88a0fc00, "casl",            OP_ARMV8_A64_CASL,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x88e07c00, "casa",            OP_ARMV8_A64_CASA,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x88e0fc00, "casal",           OP_ARMV8_A64_CASAL,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP_ALT_DECODE(0xc8a07c00, "cas",             OP_ARMV8_A64_CAS,       DISOPTYPE_HARMLESS, LdStCas64),
+    DIS_ARMV8_OP_ALT_DECODE(0xc8a0fc00, "casl",            OP_ARMV8_A64_CASL,      DISOPTYPE_HARMLESS, LdStCas64),
+    DIS_ARMV8_OP_ALT_DECODE(0xc8e07c00, "casa",            OP_ARMV8_A64_CASA,      DISOPTYPE_HARMLESS, LdStCas64),
+    DIS_ARMV8_OP_ALT_DECODE(0xc8e0fc00, "casal",           OP_ARMV8_A64_CASAL,     DISOPTYPE_HARMLESS, LdStCas64),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStCas, 0xffe0fc00 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeCollate,
+                            /* o0 */     RT_BIT_32(15)
+                            /* L  */   | RT_BIT_32(22)
+                            /* size */ | RT_BIT_32(30) | RT_BIT_32(31), 15);
+
+
+/**
+ * C4.1.94 - Loads and Stores
+ *
+ * Differentiate between Load/Store ordered and Compare and swap instruction classes based on op2<11> (bit 21).
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOrdered_Cas)
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DIS_ARMV8_DECODE_MAP_ENTRY(LdStOrdered), */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStCas),
+DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(LdStOrdered_Cas, 21);
+
+
+/**
+ * C4.1.94 - Loads and Stores
+ *
+ * Differentiate between Advanced SIMD load/stores and the rest based on op2<13> (bit 23).
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStBit28_1_Bit29_0_Bit26_1)
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo  Load/store exclusive register */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStOrdered_Cas),
+DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(LdStBit28_1_Bit29_0_Bit26_1, 23);
+
+
+/**
+ * C4.1.94 - Loads and Stores
+ *
+ * Differentiate between Advanced SIMD load/stores and the rest based on op1 (bit 26).
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStBit28_0_Bit29_0)
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStBit28_1_Bit29_0_Bit26_1),
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo  Advanced SIMD load/store multiple structures (post-indexed) / Advanced SIMD load/store single structure / Advanced SIMD load/store single structure (post-indexed) */
+DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(LdStBit28_0_Bit29_0, 26);
 
 
@@ -1142 +1208 @@
  */
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOp0Lo)
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStBit28_0_Bit29_0),
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStBit28_1_Bit29_0),
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegPair),

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -28 +28 @@
 .private_extern _TestProcA64
 _TestProcA64:
+
+        casb  w0,  w1, [x0]
 
         ; Miscellaneous instructions without a parameter
@@ -3707 +3709 @@
 
         ;
+        ; Compare and swap
+        ;
+
+        casb  w0,  w1, [x0]
+        casb wzr, wzr, [sp]
+
+        caslb  w0,  w1, [x0]
+        caslb wzr, wzr, [sp]
+
+        casab  w0,  w1, [x0]
+        casab wzr, wzr, [sp]
+
+        casalb  w0,  w1, [x0]
+        casalb wzr, wzr, [sp]
+
+        cash  w0,  w1, [x0]
+        cash wzr, wzr, [sp]
+
+        caslh  w0,  w1, [x0]
+        caslh wzr, wzr, [sp]
+
+        casah  w0,  w1, [x0]
+        casah wzr, wzr, [sp]
+
+        casalh  w0,  w1, [x0]
+        casalh wzr, wzr, [sp]
+
+        cas  w0,  w1, [x0]
+        cas wzr, wzr, [sp]
+
+        casl  w0,  w1, [x0]
+        casl wzr, wzr, [sp]
+
+        casa  w0,  w1, [x0]
+        casa wzr, wzr, [sp]
+
+        casal  w0,  w1, [x0]
+        casal wzr, wzr, [sp]
+
+        cas  x0,  x1, [x0]
+        cas xzr, xzr, [sp]
+
+        casl  x0,  x1, [x0]
+        casl xzr, xzr, [sp]
+
+        casa  x0,  x1, [x0]
+        casa xzr, xzr, [sp]
+
+        casal  x0,  x1, [x0]
+        casal xzr, xzr, [sp]
+
+        ;
         ; Keep last so the testcase can catch errors in
         ; the disassembly of the last instruction.