Changeset 106782 in vbox for trunk/src/VBox/Disassembler

Timestamp:

Oct 30, 2024 8:44:32 AM (3 months ago)

Author:

vboxsync

Message:

Disassembler: Decode Load/Store exclusive pair instructions, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmCore-armv8.cpp (modified) (1 diff)
• DisasmTables-armv8-a64-ld-st.cpp.h (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (1 diff)

trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp

@@ -1004 +1004 @@
 
     Assert(pInsnParm->cBits == 1);
-    Assert(pInsnParm->idxBitStart == 31);
-    *pf64Bit = RT_BOOL(u32Insn & RT_BIT_32(31));
+    Assert(pInsnParm->idxBitStart == 31 || pInsnParm->idxBitStart == 30);
+    *pf64Bit = RT_BOOL(u32Insn & RT_BIT_32(pInsnParm->idxBitStart));
     return VINF_SUCCESS;
 }

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h

@@ -1170 +1170 @@
 
 
-/* C4.1.94.14 - Loads and Stores - Compare and swap */
+/* C4.1.94.11 - Loads and Stores - Load exclusive pair */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStExclusivePair)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSf,            30,  1, DIS_ARMV8_INSN_PARAM_UNSET), /* Not exactly an SF bit but serves the same purpose. */
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32,       16,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,         10,  5, 2 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,      5,  5, 3 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStExclusiveRegLd)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSf,            30,  1, DIS_ARMV8_INSN_PARAM_UNSET), /* Not exactly an SF bit but serves the same purpose. */
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr,         10,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,      5,  5, 2 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStExclusivePair)
+    DIS_ARMV8_OP(           0x88200000, "stxp",            OP_ARMV8_A64_STXP,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x88208000, "stlxp",           OP_ARMV8_A64_STLXP,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP_ALT_DECODE(0x88600000, "ldxp",            OP_ARMV8_A64_LDXP,      DISOPTYPE_HARMLESS, LdStExclusiveRegLd),
+    DIS_ARMV8_OP_ALT_DECODE(0x88608000, "ldaxp",           OP_ARMV8_A64_LDAXP,     DISOPTYPE_HARMLESS, LdStExclusiveRegLd),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStExclusivePair, 0xbfe08000 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeCollate,
+                            /* o0 */     RT_BIT_32(15)
+                            /* L  */   | RT_BIT_32(22), 15);
+
+
+/* C4.1.94.14 - Loads and Stores - Load exclusive register */
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStExclusiveReg)
     DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32,       16,  5, 0 /*idxParam*/),
@@ -1216 +1239 @@
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStExclusive)
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStExclusiveReg),
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DIS_ARMV8_DECODE_MAP_ENTRY(LdStExclusivePair), */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStExclusivePair),
 DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(LdStExclusive, 21);
 

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -3819 +3819 @@
 
         ;
+        ; Load/store exclusive pair
+        ;
+
+        stxp w0,  w1,  w2, [x3]
+        stxp w0, wzr, wzr, [sp]
+        stxp w0,  x1,  x2, [x3]
+        stxp w0, xzr, xzr, [sp]
+
+        stlxp w0,  w1,  w2, [x3]
+        stlxp w0, wzr, wzr, [sp]
+        stlxp w0,  x1,  x2, [x3]
+        stlxp w0, xzr, xzr, [sp]
+
+        ldxp  w1,  w2, [x0]
+        ldxp wzr, wzr, [sp]
+        ldxp  x1,  x2, [x0]
+        ldxp xzr, xzr, [sp]
+
+        ldaxp  w1,  w2, [x0]
+        ldaxp wzr, wzr, [sp]
+        ldaxp  x1,  x2, [x0]
+        ldaxp xzr, xzr, [sp]
+
+        ;
         ; Keep last so the testcase can catch errors in
         ; the disassembly of the last instruction.