Changeset 106783 in vbox for trunk/src/VBox/Disassembler

Timestamp:

Oct 30, 2024 9:10:18 AM (4 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165675

Message:

Disassembler: Decode Load/Store ordered instructions, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmTables-armv8-a64-ld-st.cpp.h (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (1 diff)

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h

@@ -1126 +1126 @@
 
 
+/* C4.1.94.13 - Loads and Stores - Load/Store ordered */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStOrdered)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr32,        0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,      5,  5, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStOrdered64)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprZr64,        0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,      5,  5, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStOrdered)
+    DIS_ARMV8_OP(           0x089f7c00, "stllrb",          OP_ARMV8_A64_STLLRB,    DISOPTYPE_HARMLESS),                /* FEAT_LOR */
+    DIS_ARMV8_OP(           0x089ffc00, "stlrb",           OP_ARMV8_A64_STLRB,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x08df7c00, "ldlarb",          OP_ARMV8_A64_LDLARB,    DISOPTYPE_HARMLESS),                /* FEAT_LOR */
+    DIS_ARMV8_OP(           0x08dffc00, "ldarb",           OP_ARMV8_A64_LDARB,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x489f7c00, "stllrh",          OP_ARMV8_A64_STLLRH,    DISOPTYPE_HARMLESS),                /* FEAT_LOR */
+    DIS_ARMV8_OP(           0x489ffc00, "stlrh",           OP_ARMV8_A64_STLRH,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x48df7c00, "ldlarh",          OP_ARMV8_A64_LDLARH,    DISOPTYPE_HARMLESS),                /* FEAT_LOR */
+    DIS_ARMV8_OP(           0x48dffc00, "ldarh",           OP_ARMV8_A64_LDARH,     DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x889f7c00, "stllr",           OP_ARMV8_A64_STLLR,     DISOPTYPE_HARMLESS),                /* FEAT_LOR */
+    DIS_ARMV8_OP(           0x889ffc00, "stlr",            OP_ARMV8_A64_STLR,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x88df7c00, "ldlar",           OP_ARMV8_A64_LDLAR,     DISOPTYPE_HARMLESS),                /* FEAT_LOR */
+    DIS_ARMV8_OP(           0x88dffc00, "ldar",            OP_ARMV8_A64_LDAR,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP_ALT_DECODE(0xc89f7c00, "stllr",           OP_ARMV8_A64_STLLR,     DISOPTYPE_HARMLESS, LdStOrdered64), /* FEAT_LOR */
+    DIS_ARMV8_OP_ALT_DECODE(0xc89ffc00, "stlr",            OP_ARMV8_A64_STLR,      DISOPTYPE_HARMLESS, LdStOrdered64),
+    DIS_ARMV8_OP_ALT_DECODE(0xc8df7c00, "ldlar",           OP_ARMV8_A64_LDLAR,     DISOPTYPE_HARMLESS, LdStOrdered64), /* FEAT_LOR */
+    DIS_ARMV8_OP_ALT_DECODE(0xc8dffc00, "ldar",            OP_ARMV8_A64_LDAR,      DISOPTYPE_HARMLESS, LdStOrdered64),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStOrdered, 0xfffffc00 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeCollate,
+                            /* o0 */     RT_BIT_32(15)
+                            /* L  */   | RT_BIT_32(22)
+                            /* size */ | RT_BIT_32(30) | RT_BIT_32(31), 15);
+
+
 /* C4.1.94.14 - Loads and Stores - Compare and swap */
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStCas)
@@ -1165 +1196 @@
  */
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStOrdered_Cas)
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DIS_ARMV8_DECODE_MAP_ENTRY(LdStOrdered), */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStOrdered),
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStCas),
 DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(LdStOrdered_Cas, 21);

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -3843 +3843 @@
 
         ;
+        ; Load/store ordered
+        ;
+
+        stllrb w0,  [x1]
+        stllrb wzr, [sp]
+
+        stlrb w0,  [x1]
+        stlrb wzr, [sp]
+
+        ldlarb w0,  [x1]
+        ldlarb wzr, [sp]
+
+        ldarb w0,  [x1]
+        ldarb wzr, [sp]
+
+        stllrh w0,  [x1]
+        stllrh wzr, [sp]
+
+        stlrh w0,  [x1]
+        stlrh wzr, [sp]
+
+        ldlarh w0,  [x1]
+        ldlarh wzr, [sp]
+
+        ldarh w0,  [x1]
+        ldarh wzr, [sp]
+
+        stllr w0,  [x1]
+        stllr wzr, [sp]
+
+        stlr w0,  [x1]
+        stlr wzr, [sp]
+
+        ldlar w0,  [x1]
+        ldlar wzr, [sp]
+
+        ldar w0,  [x1]
+        ldar wzr, [sp]
+
+        stllr x0,  [x1]
+        stllr xzr, [sp]
+
+        stlr x0,  [x1]
+        stlr xzr, [sp]
+
+        ldlar x0,  [x1]
+        ldlar xzr, [sp]
+
+        ldar x0,  [x1]
+        ldar xzr, [sp]
+
+        ;
         ; Keep last so the testcase can catch errors in
         ; the disassembly of the last instruction.