Changeset 106791 in vbox for trunk/src/VBox/Disassembler
- Timestamp:
- Oct 30, 2024 1:59:23 PM (3 months ago)
- Location:
- trunk/src/VBox/Disassembler
- Files:
-
- 6 edited
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DisasmCore-armv8.cpp (modified) (7 diffs)
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DisasmFormatArmV8.cpp (modified) (17 diffs)
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DisasmInternal-armv8.h (modified) (2 diffs)
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DisasmTables-armv8-a64-ld-st.cpp.h (modified) (1 diff)
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testcase/tstDisasmArmv8-1-asm.S (modified) (1 diff)
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testcase/tstDisasmArmv8-1.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp
r106782 r106791 84 84 static FNDISPARSEARMV8 disArmV8ParseGprSp; 85 85 static FNDISPARSEARMV8 disArmV8ParseGprOff; 86 static FNDISPARSEARMV8 disArmV8ParseVecReg; 86 87 static FNDISPARSEARMV8 disArmV8ParseAddrGprSp; 87 88 static FNDISPARSEARMV8 disArmV8ParseRegFixed31; … … 117 118 static FNDISPARSEARMV8 disArmV8ParseLdrPacImm; 118 119 static FNDISPARSEARMV8 disArmV8ParseLdrPacW; 120 static FNDISPARSEARMV8 disArmV8ParseVecRegElemSize; 121 static FNDISPARSEARMV8 disArmV8ParseVecRegQ; 122 static FNDISPARSEARMV8 disArmV8ParseVecGrp; 119 123 /** @} */ 120 124 … … 145 149 disArmV8ParseGprSp, 146 150 disArmV8ParseGprOff, 151 disArmV8ParseVecReg, 147 152 disArmV8ParseAddrGprSp, 148 153 disArmV8ParseRegFixed31, … … 178 183 disArmV8ParseSImmTags, 179 184 disArmV8ParseLdrPacImm, 180 disArmV8ParseLdrPacW 185 disArmV8ParseLdrPacW, 186 disArmV8ParseVecRegElemSize, 187 disArmV8ParseVecRegQ, 188 disArmV8ParseVecGrp 181 189 }; 182 190 … … 391 399 pParam->armv8.GprIndex.enmRegType = kDisOpParamArmV8RegType_Gpr_64Bit; /* Might get overwritten later on. */ 392 400 pParam->fUse |= DISUSE_INDEX; 401 return VINF_SUCCESS; 402 } 403 404 405 static int disArmV8ParseVecReg(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit) 406 { 407 RT_NOREF(pDis, pOp, pInsnClass, pf64Bit); 408 Assert(pParam->armv8.enmType == kDisArmv8OpParmNone); 409 410 pParam->armv8.enmType = kDisArmv8OpParmReg; 411 pParam->armv8.Op.Reg.idReg = disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits); 412 pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Simd_Vector; 413 pParam->armv8.Op.Reg.enmVecType = pDis->armv8.enmVecRegType; 393 414 return VINF_SUCCESS; 394 415 } … … 1081 1102 1082 1103 1104 static int disArmV8ParseVecRegElemSize(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit) 1105 { 1106 RT_NOREF(pDis, pOp, pInsnClass, pParam, pInsnParm, pf64Bit); 1107 1108 Assert(pInsnParm->cBits == 2); 1109 Assert(pInsnParm->idxBitStart == 10); 1110 Assert(pDis->armv8.enmVecRegType == kDisOpParamArmV8VecRegType_None); 1111 1112 uint32_t u32 = disArmV8ExtractBitVecFromInsn(u32Insn, 10, 2); 1113 switch (u32) 1114 { 1115 case 0: pDis->armv8.enmVecRegType = kDisOpParamArmV8VecRegType_8B; break; 1116 case 1: pDis->armv8.enmVecRegType = kDisOpParamArmV8VecRegType_4H; break; 1117 case 2: pDis->armv8.enmVecRegType = kDisOpParamArmV8VecRegType_2S; break; 1118 case 3: pDis->armv8.enmVecRegType = kDisOpParamArmV8VecRegType_1D; break; 1119 default: AssertFailed(); break; 1120 } 1121 1122 return VINF_SUCCESS; 1123 } 1124 1125 1126 static int disArmV8ParseVecRegQ(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit) 1127 { 1128 RT_NOREF(pDis, pOp, pInsnClass, pParam, pInsnParm, pf64Bit); 1129 1130 Assert(pInsnParm->cBits == 1); 1131 Assert(pInsnParm->idxBitStart == 30); 1132 Assert( pDis->armv8.enmVecRegType != kDisOpParamArmV8VecRegType_None 1133 && pDis->armv8.enmVecRegType < kDisOpParamArmV8VecRegType_2D); 1134 /* This ASSUMES that the vector register type for the 64-bit and 128-bit vector register lengths are adjacent. */ 1135 if (u32Insn & RT_BIT_32(30)) 1136 pDis->armv8.enmVecRegType = (DISOPPARAMARMV8VECREGTYPE)((uint8_t)pDis->armv8.enmVecRegType + 1); 1137 return VINF_SUCCESS; 1138 } 1139 1140 1141 static int disArmV8ParseVecGrp(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit) 1142 { 1143 RT_NOREF(pDis, u32Insn, pOp, pInsnClass, pParam, pInsnParm, pf64Bit); 1144 1145 /* This is special as it doesn't really parse the instruction but sets the given parameter from vector to group vector and sets the register count based on the number if bits. */ 1146 Assert(pInsnParm->cBits <= 4); 1147 Assert(pInsnParm->idxBitStart == 0); 1148 Assert(pParam->armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Simd_Vector); 1149 pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Simd_Vector_Group; 1150 pParam->armv8.Op.Reg.cRegs = pInsnParm->cBits; 1151 return VINF_SUCCESS; 1152 } 1153 1154 1083 1155 static uint32_t disArmV8DecodeIllegal(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass) 1084 1156 { … … 1212 1284 pDis->armv8.enmCond = kDisArmv8InstrCond_Al; 1213 1285 pDis->armv8.enmFpType = kDisArmv8InstrFpType_Invalid; 1286 pDis->armv8.enmVecRegType = kDisOpParamArmV8VecRegType_None; 1214 1287 pDis->armv8.cbOperand = 0; 1215 1288 -
trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp
r106760 r106791 79 79 "q0\0", "q1\0", "q2\0", "q3\0", "q4\0", "q5\0", "q6\0", "q7\0", "q8\0", "q9\0", "q10", "q11", "q12", "q13", "q14", "q15", 80 80 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 81 }; 82 static const char g_aszArmV8RegSimdVector[32][4] = 83 { 84 "v0\0", "v1\0", "v2\0", "v3\0", "v4\0", "v5\0", "v6\0", "v7\0", "v8\0", "v9\0", "v10", "v11", "v12", "v13", "v14", "v15", 85 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 81 86 }; 82 87 static const char g_aszArmV8Cond[16][3] = … … 99 104 /* kDisArmv8InstrPState_SVCRSMZA */ "svcrsmza", 100 105 /* kDisArmv8InstrPState_TCO */ "tco" 106 }; 107 static const char g_aszArmV8VecRegType[9][4] = 108 { 109 /* kDisOpParamArmV8VecRegType_None */ "\0\0\0", 110 /* kDisOpParamArmV8VecRegType_8B */ "8B\0", 111 /* kDisOpParamArmV8VecRegType_16B */ "16B", 112 /* kDisOpParamArmV8VecRegType_4H */ "4H\0", 113 /* kDisOpParamArmV8VecRegType_8H */ "8H\0", 114 /* kDisOpParamArmV8VecRegType_2S */ "2S\0", 115 /* kDisOpParamArmV8VecRegType_4S */ "4S\0", 116 /* kDisOpParamArmV8VecRegType_1D */ "1D\0", 117 /* kDisOpParamArmV8VecRegType_2D */ "2D\0" 101 118 }; 102 119 … … 344 361 * @returns Pointer to the register name. 345 362 * @param pDis The disassembler state. 346 * @param pParam The parameter. 363 * @param enmRegType The register type. 364 * @param idReg The register ID. 347 365 * @param pcchReg Where to store the length of the name. 348 366 */ 349 DECLINLINE(const char *) disasmFormatArmV8Reg(PCDISSTATE pDis, PCDISOPPARAMARMV8REG pReg, size_t *pcchReg)367 DECLINLINE(const char *) disasmFormatArmV8Reg(PCDISSTATE pDis, uint8_t enmRegType, uint8_t idReg, size_t *pcchReg) 350 368 { 351 369 RT_NOREF_PV(pDis); 352 370 353 switch ( pReg->enmRegType)371 switch (enmRegType) 354 372 { 355 373 case kDisOpParamArmV8RegType_Gpr_32Bit: 356 374 { 357 Assert( pReg->idReg < RT_ELEMENTS(g_aszArmV8RegGen32));358 const char *psz = g_aszArmV8RegGen32[ pReg->idReg];375 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegGen32)); 376 const char *psz = g_aszArmV8RegGen32[idReg]; 359 377 *pcchReg = 2 + !!psz[2]; 360 378 return psz; … … 362 380 case kDisOpParamArmV8RegType_Gpr_64Bit: 363 381 { 364 Assert( pReg->idReg < RT_ELEMENTS(g_aszArmV8RegGen64));365 const char *psz = g_aszArmV8RegGen64[ pReg->idReg];382 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegGen64)); 383 const char *psz = g_aszArmV8RegGen64[idReg]; 366 384 *pcchReg = 2 + !!psz[2]; 367 385 return psz; … … 370 388 { 371 389 Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid); 372 Assert( pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpSingle));373 const char *psz = g_aszArmV8RegFpSingle[ pReg->idReg];390 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegFpSingle)); 391 const char *psz = g_aszArmV8RegFpSingle[idReg]; 374 392 *pcchReg = 2 + !!psz[2]; 375 393 return psz; … … 378 396 { 379 397 Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid); 380 Assert( pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpDouble));381 const char *psz = g_aszArmV8RegFpDouble[ pReg->idReg];398 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegFpDouble)); 399 const char *psz = g_aszArmV8RegFpDouble[idReg]; 382 400 *pcchReg = 2 + !!psz[2]; 383 401 return psz; … … 386 404 { 387 405 Assert(pDis->armv8.enmFpType != kDisArmv8InstrFpType_Invalid); 388 Assert( pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpHalf));389 const char *psz = g_aszArmV8RegFpHalf[ pReg->idReg];406 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegFpHalf)); 407 const char *psz = g_aszArmV8RegFpHalf[idReg]; 390 408 *pcchReg = 2 + !!psz[2]; 391 409 return psz; … … 393 411 case kDisOpParamArmV8RegType_Simd_Scalar_8Bit: 394 412 { 395 Assert( pReg->idReg < RT_ELEMENTS(g_aszArmV8RegSimdScalar8Bit));396 const char *psz = g_aszArmV8RegSimdScalar8Bit[ pReg->idReg];413 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegSimdScalar8Bit)); 414 const char *psz = g_aszArmV8RegSimdScalar8Bit[idReg]; 397 415 *pcchReg = 2 + !!psz[2]; 398 416 return psz; … … 400 418 case kDisOpParamArmV8RegType_Simd_Scalar_16Bit: 401 419 { 402 Assert( pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpHalf));403 const char *psz = g_aszArmV8RegFpHalf[ pReg->idReg];420 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegFpHalf)); 421 const char *psz = g_aszArmV8RegFpHalf[idReg]; 404 422 *pcchReg = 2 + !!psz[2]; 405 423 return psz; … … 407 425 case kDisOpParamArmV8RegType_Simd_Scalar_32Bit: 408 426 { 409 Assert( pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpSingle));410 const char *psz = g_aszArmV8RegFpSingle[ pReg->idReg];427 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegFpSingle)); 428 const char *psz = g_aszArmV8RegFpSingle[idReg]; 411 429 *pcchReg = 2 + !!psz[2]; 412 430 return psz; … … 415 433 { 416 434 /* Using the floating point double register names here. */ 417 Assert( pReg->idReg < RT_ELEMENTS(g_aszArmV8RegFpDouble));418 const char *psz = g_aszArmV8RegFpDouble[ pReg->idReg];435 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegFpDouble)); 436 const char *psz = g_aszArmV8RegFpDouble[idReg]; 419 437 *pcchReg = 2 + !!psz[2]; 420 438 return psz; … … 422 440 case kDisOpParamArmV8RegType_Simd_Scalar_128Bit: 423 441 { 424 Assert( pReg->idReg < RT_ELEMENTS(g_aszArmV8RegSimdScalar128Bit));425 const char *psz = g_aszArmV8RegSimdScalar128Bit[ pReg->idReg];442 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegSimdScalar128Bit)); 443 const char *psz = g_aszArmV8RegSimdScalar128Bit[idReg]; 426 444 *pcchReg = 2 + !!psz[2]; 427 445 return psz; … … 431 449 *pcchReg = 2; 432 450 return "sp"; 451 } 452 case kDisOpParamArmV8RegType_Simd_Vector: 453 case kDisOpParamArmV8RegType_Simd_Vector_Group: 454 { 455 Assert(idReg < RT_ELEMENTS(g_aszArmV8RegSimdVector)); 456 const char *psz = g_aszArmV8RegSimdVector[idReg]; 457 *pcchReg = 2 + !!psz[2]; 458 return psz; 433 459 } 434 460 default: … … 437 463 return NULL; 438 464 } 465 } 466 467 468 /** 469 * Gets the vector register type for the given parameter. 470 * 471 * @returns Pointer to the register type. 472 * @param enmVecType THe vector type. 473 * @param pcchType Where to store the length of the type. 474 */ 475 DECLINLINE(const char *) disasmFormatArmV8VecRegType(uint8_t enmVecType, size_t *pcchType) 476 { 477 Assert( enmVecType != kDisOpParamArmV8VecRegType_None 478 && enmVecType < RT_ELEMENTS(g_aszArmV8VecRegType)); 479 480 const char *psz = g_aszArmV8VecRegType[enmVecType]; 481 *pcchType = 2 + !!psz[2]; 482 return psz; 439 483 } 440 484 … … 799 843 Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32))); 800 844 801 size_t cchReg; 802 const char *pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.Op.Reg, &cchReg); 803 PUT_STR(pszReg, cchReg); 845 if (pParam->armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Simd_Vector_Group) 846 { 847 PUT_C('{'); 848 849 Assert( pParam->armv8.Op.Reg.cRegs > 0 850 && pParam->armv8.Op.Reg.cRegs <= 4); 851 Assert(pParam->armv8.Op.Reg.enmVecType != kDisOpParamArmV8VecRegType_None); 852 853 for (uint8_t idReg = pParam->armv8.Op.Reg.idReg; idReg < (pParam->armv8.Op.Reg.idReg + pParam->armv8.Op.Reg.cRegs); idReg++) 854 { 855 if (idReg > pParam->armv8.Op.Reg.idReg) 856 PUT_C(','); 857 PUT_C(' '); /** @todo Make the indenting configurable. */ 858 859 size_t cchTmp; 860 const char *pszTmp = disasmFormatArmV8Reg(pDis, kDisOpParamArmV8RegType_Simd_Vector_Group, 861 idReg % RT_ELEMENTS(g_aszArmV8RegSimdVector), &cchTmp); 862 PUT_STR(pszTmp, cchTmp); 863 PUT_C('.'); 864 pszTmp = disasmFormatArmV8VecRegType(pParam->armv8.Op.Reg.enmVecType, &cchTmp); 865 PUT_STR(pszTmp, cchTmp); 866 } 867 868 PUT_C('}'); 869 } 870 else 871 { 872 size_t cchTmp; 873 const char *pszTmp = disasmFormatArmV8Reg(pDis, pParam->armv8.Op.Reg.enmRegType, 874 pParam->armv8.Op.Reg.idReg, &cchTmp); 875 PUT_STR(pszTmp, cchTmp); 876 877 if ( pParam->armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Simd_Vector 878 && pParam->armv8.Op.Reg.enmVecType != kDisOpParamArmV8VecRegType_None) 879 { 880 PUT_C('.'); 881 pszTmp = disasmFormatArmV8VecRegType(pParam->armv8.Op.Reg.enmVecType, &cchTmp); 882 PUT_STR(pszTmp, cchTmp); 883 } 884 } 804 885 break; 805 886 } … … 825 906 826 907 size_t cchReg; 827 const char *pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.Op.Reg, &cchReg); 908 const char *pszReg = disasmFormatArmV8Reg(pDis, pParam->armv8.Op.Reg.enmRegType, 909 pParam->armv8.Op.Reg.idReg, &cchReg); 828 910 PUT_STR(pszReg, cchReg); 829 911 … … 840 922 PUT_SZ(", "); 841 923 842 pszReg = disasmFormatArmV8Reg(pDis, &pParam->armv8.GprIndex, &cchReg); 924 pszReg = disasmFormatArmV8Reg(pDis, pParam->armv8.GprIndex.enmRegType, 925 pParam->armv8.GprIndex.idReg, &cchReg); 843 926 PUT_STR(pszReg, cchReg); 844 927 } -
trunk/src/VBox/Disassembler/DisasmInternal-armv8.h
r106770 r106791 61 61 kDisParmParseGprSp, 62 62 kDisParmParseGprOff, 63 kDisParmParseVecReg, 63 64 kDisParmParseAddrGprSp, 64 65 kDisParmParseRegFixed31, … … 95 96 kDisParmParseLdrPacImm, 96 97 kDisParmParseLdrPacW, 98 kDisParmParseVecRegElemSize, 99 kDisParmParseVecQ, 100 kDisParmParseVecGrp, 97 101 kDisParmParseMax 98 102 } DISPARMPARSEIDX; -
trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h
r106783 r106791 1285 1285 1286 1286 1287 /* C4.1.94.2 - Loads and Stores - Advanced SIMD load/store multiple structures */ 1288 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStAdvSimdMultStructs) 1289 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1290 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1291 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1292 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 4, 0 /*idxParam*/), 1293 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1294 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructs3) 1295 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1296 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1297 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1298 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 3, 0 /*idxParam*/), 1299 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1300 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructs2) 1301 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1302 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1303 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1304 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 2, 0 /*idxParam*/), 1305 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1306 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructs1) 1307 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1308 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1309 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1310 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 1, 0 /*idxParam*/), 1311 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1312 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStAdvSimdMultStructs) 1313 DIS_ARMV8_OP( 0x0c000000, "st4", OP_ARMV8_A64_ST4, DISOPTYPE_HARMLESS), 1314 INVALID_OPCODE, 1315 DIS_ARMV8_OP( 0x0c002000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS), 1316 INVALID_OPCODE, 1317 DIS_ARMV8_OP_ALT_DECODE(0x0c004000, "st3", OP_ARMV8_A64_ST3, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructs3), 1318 INVALID_OPCODE, 1319 DIS_ARMV8_OP_ALT_DECODE(0x0c006000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructs3), 1320 DIS_ARMV8_OP_ALT_DECODE(0x0c007000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructs1), 1321 DIS_ARMV8_OP_ALT_DECODE(0x0c008000, "st2", OP_ARMV8_A64_ST2, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructs2), 1322 INVALID_OPCODE, 1323 DIS_ARMV8_OP_ALT_DECODE(0x0c00a000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructs2), 1324 INVALID_OPCODE, 1325 INVALID_OPCODE, 1326 INVALID_OPCODE, 1327 INVALID_OPCODE, 1328 INVALID_OPCODE, 1329 DIS_ARMV8_OP( 0x0c400000, "ld4", OP_ARMV8_A64_LD4, DISOPTYPE_HARMLESS), 1330 INVALID_OPCODE, 1331 DIS_ARMV8_OP( 0x0c402000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS), 1332 INVALID_OPCODE, 1333 DIS_ARMV8_OP_ALT_DECODE(0x0c404000, "ld3", OP_ARMV8_A64_LD3, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructs3), 1334 INVALID_OPCODE, 1335 DIS_ARMV8_OP_ALT_DECODE(0x0c406000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructs3), 1336 DIS_ARMV8_OP_ALT_DECODE(0x0c407000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructs1), 1337 DIS_ARMV8_OP_ALT_DECODE(0x0c408000, "ld2", OP_ARMV8_A64_LD2, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructs2), 1338 INVALID_OPCODE, 1339 DIS_ARMV8_OP_ALT_DECODE(0x0c40a000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructs2), 1340 /* Rest is invalid */ 1341 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStAdvSimdMultStructs, 0xbffff000 /*fFixedInsn*/, 1342 kDisArmV8OpcDecodeCollate, 1343 /* opcode */ RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(15) 1344 /* L */ | RT_BIT_32(22), 12); 1345 1346 1287 1347 /** 1288 1348 * C4.1.94 - Loads and Stores 1289 1349 * 1350 * Differentiate between the Advanced SIMD load/stores. 1351 */ 1352 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStAdvSimd) 1353 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructs), 1354 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Advanced SIMD load/store multiple structures (post-indexed) */ 1355 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Advanced SIMD load/store single structure */ 1356 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Advanced SIMD load/store single structure (post-indexed) */ 1357 DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStAdvSimd, RT_BIT_32(23) | RT_BIT_32(24), 23); 1358 1359 1360 /** 1361 * C4.1.94 - Loads and Stores 1362 * 1290 1363 * Differentiate between Advanced SIMD load/stores and the rest based on op1 (bit 26). 1291 1364 */ 1292 1365 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStBit28_0_Bit29_0) 1293 1366 DIS_ARMV8_DECODE_MAP_ENTRY(LdStBit28_1_Bit29_0_Bit26_1), 1294 DIS_ARMV8_DECODE_MAP_ INVALID_ENTRY, /** @todo Advanced SIMD load/store multiple structures (post-indexed) / Advanced SIMD load/store single structure / Advanced SIMD load/store single structure (post-indexed) */1367 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimd), 1295 1368 DIS_ARMV8_DECODE_MAP_DEFINE_END_SINGLE_BIT(LdStBit28_0_Bit29_0, 26); 1296 1369 -
trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S
r106783 r106791 3895 3895 3896 3896 ; 3897 ; Advanced SIMD load/store multiple structures 3898 ; 3899 st4 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0] 3900 st4 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp] 3901 st4 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0] 3902 st4 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp] 3903 3904 st4 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0] 3905 st4 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp] 3906 st4 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0] 3907 st4 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp] 3908 3909 st4 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0] 3910 st4 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp] 3911 st4 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0] 3912 st4 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp] 3913 3914 st4 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0] 3915 st4 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp] 3916 3917 st1 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0] 3918 st1 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp] 3919 st1 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0] 3920 st1 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp] 3921 3922 st1 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0] 3923 st1 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp] 3924 st1 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0] 3925 st1 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp] 3926 3927 st1 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0] 3928 st1 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp] 3929 st1 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0] 3930 st1 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp] 3931 3932 st1 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0] 3933 st1 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp] 3934 3935 st3 { v0.8B, v1.8B, v2.8B }, [x0] 3936 st3 { v31.8B, v0.8B, v1.8B }, [sp] 3937 st3 { v0.16B, v1.16B, v2.16B }, [x0] 3938 st3 { v31.16B, v0.16B, v1.16B }, [sp] 3939 3940 st3 { v0.4H, v1.4H, v2.4H }, [x0] 3941 st3 { v31.4H, v0.4H, v1.4H }, [sp] 3942 st3 { v0.8H, v1.8H, v2.8H }, [x0] 3943 st3 { v31.8H, v0.8H, v1.8H }, [sp] 3944 3945 st3 { v0.2S, v1.2S, v2.2S }, [x0] 3946 st3 { v31.2S, v0.2S, v1.2S }, [sp] 3947 st3 { v0.4S, v1.4S, v2.4S }, [x0] 3948 st3 { v31.4S, v0.4S, v1.4S }, [sp] 3949 3950 st3 { v0.2D, v1.2D, v2.2D }, [x0] 3951 st3 { v31.2D, v0.2D, v1.2D }, [sp] 3952 3953 st1 { v0.8B, v1.8B, v2.8B }, [x0] 3954 st1 { v31.8B, v0.8B, v1.8B }, [sp] 3955 st1 { v0.16B, v1.16B, v2.16B }, [x0] 3956 st1 { v31.16B, v0.16B, v1.16B }, [sp] 3957 3958 st1 { v0.4H, v1.4H, v2.4H }, [x0] 3959 st1 { v31.4H, v0.4H, v1.4H }, [sp] 3960 st1 { v0.8H, v1.8H, v2.8H }, [x0] 3961 st1 { v31.8H, v0.8H, v1.8H }, [sp] 3962 3963 st1 { v0.2S, v1.2S, v2.2S }, [x0] 3964 st1 { v31.2S, v0.2S, v1.2S }, [sp] 3965 st1 { v0.4S, v1.4S, v2.4S }, [x0] 3966 st1 { v31.4S, v0.4S, v1.4S }, [sp] 3967 3968 st1 { v0.2D, v1.2D, v2.2D }, [x0] 3969 st1 { v31.2D, v0.2D, v1.2D }, [sp] 3970 3971 st1 { v0.8B }, [x0] 3972 st1 { v31.8B }, [sp] 3973 st1 { v0.16B }, [x0] 3974 st1 { v31.16B }, [sp] 3975 3976 st1 { v0.4H }, [x0] 3977 st1 { v31.4H }, [sp] 3978 st1 { v0.8H }, [x0] 3979 st1 { v31.8H }, [sp] 3980 3981 st1 { v0.2S }, [x0] 3982 st1 { v31.2S }, [sp] 3983 st1 { v0.4S }, [x0] 3984 st1 { v31.4S }, [sp] 3985 3986 st1 { v0.2D }, [x0] 3987 st1 { v31.2D }, [sp] 3988 3989 st2 { v0.8B, v1.8B }, [x0] 3990 st2 { v31.8B, v0.8B }, [sp] 3991 st2 { v0.16B, v1.16B }, [x0] 3992 st2 { v31.16B, v0.16B }, [sp] 3993 3994 st2 { v0.4H, v1.4H }, [x0] 3995 st2 { v31.4H, v0.4H }, [sp] 3996 st2 { v0.8H, v1.8H }, [x0] 3997 st2 { v31.8H, v0.8H }, [sp] 3998 3999 st2 { v0.2S, v1.2S }, [x0] 4000 st2 { v31.2S, v0.2S }, [sp] 4001 st2 { v0.4S, v1.4S }, [x0] 4002 st2 { v31.4S, v0.4S }, [sp] 4003 4004 st2 { v0.2D, v1.2D }, [x0] 4005 st2 { v31.2D, v0.2D }, [sp] 4006 4007 st1 { v0.8B, v1.8B }, [x0] 4008 st1 { v31.8B, v0.8B }, [sp] 4009 st1 { v0.16B, v1.16B }, [x0] 4010 st1 { v31.16B, v0.16B }, [sp] 4011 4012 st1 { v0.4H, v1.4H }, [x0] 4013 st1 { v31.4H, v0.4H }, [sp] 4014 st1 { v0.8H, v1.8H }, [x0] 4015 st1 { v31.8H, v0.8H }, [sp] 4016 4017 st1 { v0.2S, v1.2S }, [x0] 4018 st1 { v31.2S, v0.2S }, [sp] 4019 st1 { v0.4S, v1.4S }, [x0] 4020 st1 { v31.4S, v0.4S }, [sp] 4021 4022 st1 { v0.2D, v1.2D }, [x0] 4023 st1 { v31.2D, v0.2D }, [sp] 4024 4025 4026 ld4 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0] 4027 ld4 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp] 4028 ld4 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0] 4029 ld4 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp] 4030 4031 ld4 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0] 4032 ld4 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp] 4033 ld4 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0] 4034 ld4 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp] 4035 4036 ld4 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0] 4037 ld4 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp] 4038 ld4 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0] 4039 ld4 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp] 4040 4041 ld4 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0] 4042 ld4 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp] 4043 4044 ld1 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0] 4045 ld1 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp] 4046 ld1 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0] 4047 ld1 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp] 4048 4049 ld1 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0] 4050 ld1 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp] 4051 ld1 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0] 4052 ld1 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp] 4053 4054 ld1 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0] 4055 ld1 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp] 4056 ld1 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0] 4057 ld1 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp] 4058 4059 ld1 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0] 4060 ld1 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp] 4061 4062 ld3 { v0.8B, v1.8B, v2.8B }, [x0] 4063 ld3 { v31.8B, v0.8B, v1.8B }, [sp] 4064 ld3 { v0.16B, v1.16B, v2.16B }, [x0] 4065 ld3 { v31.16B, v0.16B, v1.16B }, [sp] 4066 4067 ld3 { v0.4H, v1.4H, v2.4H }, [x0] 4068 ld3 { v31.4H, v0.4H, v1.4H }, [sp] 4069 ld3 { v0.8H, v1.8H, v2.8H }, [x0] 4070 ld3 { v31.8H, v0.8H, v1.8H }, [sp] 4071 4072 ld3 { v0.2S, v1.2S, v2.2S }, [x0] 4073 ld3 { v31.2S, v0.2S, v1.2S }, [sp] 4074 ld3 { v0.4S, v1.4S, v2.4S }, [x0] 4075 ld3 { v31.4S, v0.4S, v1.4S }, [sp] 4076 4077 ld3 { v0.2D, v1.2D, v2.2D }, [x0] 4078 ld3 { v31.2D, v0.2D, v1.2D }, [sp] 4079 4080 ld1 { v0.8B, v1.8B, v2.8B }, [x0] 4081 ld1 { v31.8B, v0.8B, v1.8B }, [sp] 4082 ld1 { v0.16B, v1.16B, v2.16B }, [x0] 4083 ld1 { v31.16B, v0.16B, v1.16B }, [sp] 4084 4085 ld1 { v0.4H, v1.4H, v2.4H }, [x0] 4086 ld1 { v31.4H, v0.4H, v1.4H }, [sp] 4087 ld1 { v0.8H, v1.8H, v2.8H }, [x0] 4088 ld1 { v31.8H, v0.8H, v1.8H }, [sp] 4089 4090 ld1 { v0.2S, v1.2S, v2.2S }, [x0] 4091 ld1 { v31.2S, v0.2S, v1.2S }, [sp] 4092 ld1 { v0.4S, v1.4S, v2.4S }, [x0] 4093 ld1 { v31.4S, v0.4S, v1.4S }, [sp] 4094 4095 ld1 { v0.2D, v1.2D, v2.2D }, [x0] 4096 ld1 { v31.2D, v0.2D, v1.2D }, [sp] 4097 4098 ld1 { v0.8B }, [x0] 4099 ld1 { v31.8B }, [sp] 4100 ld1 { v0.16B }, [x0] 4101 ld1 { v31.16B }, [sp] 4102 4103 ld1 { v0.4H }, [x0] 4104 ld1 { v31.4H }, [sp] 4105 ld1 { v0.8H }, [x0] 4106 ld1 { v31.8H }, [sp] 4107 4108 ld1 { v0.2S }, [x0] 4109 ld1 { v31.2S }, [sp] 4110 ld1 { v0.4S }, [x0] 4111 ld1 { v31.4S }, [sp] 4112 4113 ld1 { v0.2D }, [x0] 4114 ld1 { v31.2D }, [sp] 4115 4116 ld2 { v0.8B, v1.8B }, [x0] 4117 ld2 { v31.8B, v0.8B }, [sp] 4118 ld2 { v0.16B, v1.16B }, [x0] 4119 ld2 { v31.16B, v0.16B }, [sp] 4120 4121 ld2 { v0.4H, v1.4H }, [x0] 4122 ld2 { v31.4H, v0.4H }, [sp] 4123 ld2 { v0.8H, v1.8H }, [x0] 4124 ld2 { v31.8H, v0.8H }, [sp] 4125 4126 ld2 { v0.2S, v1.2S }, [x0] 4127 ld2 { v31.2S, v0.2S }, [sp] 4128 ld2 { v0.4S, v1.4S }, [x0] 4129 ld2 { v31.4S, v0.4S }, [sp] 4130 4131 ld2 { v0.2D, v1.2D }, [x0] 4132 ld2 { v31.2D, v0.2D }, [sp] 4133 4134 ld1 { v0.8B, v1.8B }, [x0] 4135 ld1 { v31.8B, v0.8B }, [sp] 4136 ld1 { v0.16B, v1.16B }, [x0] 4137 ld1 { v31.16B, v0.16B }, [sp] 4138 4139 ld1 { v0.4H, v1.4H }, [x0] 4140 ld1 { v31.4H, v0.4H }, [sp] 4141 ld1 { v0.8H, v1.8H }, [x0] 4142 ld1 { v31.8H, v0.8H }, [sp] 4143 4144 ld1 { v0.2S, v1.2S }, [x0] 4145 ld1 { v31.2S, v0.2S }, [sp] 4146 ld1 { v0.4S, v1.4S }, [x0] 4147 ld1 { v31.4S, v0.4S }, [sp] 4148 4149 ld1 { v0.2D, v1.2D }, [x0] 4150 ld1 { v31.2D, v0.2D }, [sp] 4151 4152 ; 3897 4153 ; Keep last so the testcase can catch errors in 3898 4154 ; the disassembly of the last instruction. -
trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1.cpp
r106770 r106791 102 102 { RT_STR_TUPLE("]"), RTSCRIPTLEXTOKTYPE_PUNCTUATOR, false, 0 }, 103 103 { RT_STR_TUPLE("!"), RTSCRIPTLEXTOKTYPE_PUNCTUATOR, false, 0 }, 104 { RT_STR_TUPLE("{"), RTSCRIPTLEXTOKTYPE_PUNCTUATOR, false, 0 }, 105 { RT_STR_TUPLE("}"), RTSCRIPTLEXTOKTYPE_PUNCTUATOR, false, 0 }, 104 106 { NULL, 0, RTSCRIPTLEXTOKTYPE_INVALID, false, 0 } 105 107 };
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