Changeset 106814 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Nov 1, 2024 2:01:09 AM (6 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165715

Message:

ValidationKit/bootsectors: Implement SIMD FP testcases for cvtpi2pd, cvtpd2pi, cvttpd2pi, and several IEM fixes; bugref:10658; jiraref:VBP-1206

IEM:

• fix IEM cvttpd2pi, cvttps2pi, cvtps2pi, cvtpd2pi failing to raise x87/MMX exceptions
• fix IEM cvtpi2ps incorrectly raising x87/MMX exceptions for non-MMX instructions

ValKit bs3-cpu-instr-4 test setup:

• add FP64_x2 value bar macros
• fix SDM exception table 23-4/5/6 test cfgs
• test cvtpi2ps, cvtps2pi, cvttps2pi with correct exceptions: table 23-5
• test cvtsi2ss, cvtss2si, cvttss2si with correct exceptions: class 3

ValKit bs3-cpu-instr-4 test worker:

• add ability to mark an instruction test immune to a particular exception

ValKit bs3-cpu-instr-4 tests:

• add tests for cvtpi2pd, cvtpd2pi, cvttpd2pi

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (9 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h

@@ -3621 +3621 @@
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-        IEM_MC_MAYBE_RAISE_FPU_XCPT();
 
         IEM_MC_PREPARE_FPU_USAGE();
@@ -3984 +3983 @@
         IEM_MC_ARG_LOCAL_REF(uint64_t *,    pu64Dst, u64Dst,    0);
         IEM_MC_ARG(uint64_t,                u64Src,             1);
+        IEM_MC_MAYBE_RAISE_FPU_XCPT();
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_PREPARE_FPU_USAGE();
@@ -4009 +4009 @@
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
+        IEM_MC_MAYBE_RAISE_FPU_XCPT();
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
@@ -4039 +4040 @@
         IEM_MC_ARG_LOCAL_REF(uint64_t *,    pu64Dst, u64Dst,    0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc,               1);
+        IEM_MC_MAYBE_RAISE_FPU_XCPT();
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_PREPARE_FPU_USAGE();
@@ -4065 +4067 @@
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
+        IEM_MC_MAYBE_RAISE_FPU_XCPT();
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
@@ -4290 +4293 @@
         IEM_MC_ARG(uint64_t,                u64Src,             1);
 
+        IEM_MC_MAYBE_RAISE_FPU_XCPT();
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_PREPARE_FPU_USAGE();
@@ -4315 +4319 @@
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
+        IEM_MC_MAYBE_RAISE_FPU_XCPT();
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
@@ -4346 +4351 @@
         IEM_MC_ARG(PCX86XMMREG,             pSrc,               1);
 
+        IEM_MC_MAYBE_RAISE_FPU_XCPT();
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_PREPARE_FPU_USAGE();
@@ -4372 +4378 @@
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
+        IEM_MC_MAYBE_RAISE_FPU_XCPT();
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);