Changeset 106816 in vbox for trunk/src/VBox/Disassembler
- Timestamp:
- Nov 1, 2024 9:24:29 AM (3 months ago)
- Location:
- trunk/src/VBox/Disassembler
- Files:
-
- 3 edited
-
DisasmFormatArmV8.cpp (modified) (2 diffs)
-
DisasmTables-armv8-a64-ld-st.cpp.h (modified) (2 diffs)
-
testcase/tstDisasmArmv8-1-asm.S (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp
r106805 r106816 924 924 Assert( (pParam->fUse & (DISUSE_PRE_INDEXED | DISUSE_POST_INDEXED)) 925 925 != (DISUSE_PRE_INDEXED | DISUSE_POST_INDEXED)); 926 Assert( ( RT_BOOL(pParam->fUse & (DISUSE_PRE_INDEXED | DISUSE_POST_INDEXED))927 != RT_BOOL(pParam->fUse & DISUSE_INDEX))928 || !(pParam->fUse & (DISUSE_PRE_INDEXED | DISUSE_POST_INDEXED | DISUSE_INDEX)));929 926 930 927 PUT_C('['); … … 938 935 { 939 936 Assert(pParam->armv8.enmExtend == kDisArmv8OpParmExtendNone); 940 PUT_SZ("], #"); 941 PUT_NUM_S16(pParam->armv8.u.offBase); 937 PUT_C(']'); 938 if (pParam->fUse & DISUSE_INDEX) 939 { 940 PUT_SZ(", "); 941 942 pszReg = disasmFormatArmV8Reg(pDis, pParam->armv8.GprIndex.enmRegType, 943 pParam->armv8.GprIndex.idReg, &cchReg); 944 PUT_STR(pszReg, cchReg); 945 } 946 else if ( pParam->armv8.u.offBase 947 || (pParam->fUse & (DISUSE_POST_INDEXED | DISUSE_PRE_INDEXED))) 948 { 949 PUT_SZ(", #"); 950 if ( pParam->armv8.u.offBase >= INT16_MIN 951 && pParam->armv8.u.offBase <= INT16_MAX) 952 PUT_NUM_S16(pParam->armv8.u.offBase); 953 else 954 PUT_NUM_S32(pParam->armv8.u.offBase); 955 } 942 956 } 943 957 else -
trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h
r106805 r106816 1398 1398 1399 1399 1400 /* C4.1.94.3 - Loads and Stores - Advanced SIMD load/store multiple structures (post-indexed), register variant. */ 1401 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStAdvSimdMultStructsPostIndexGpr) 1402 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1403 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1404 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1405 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 4, 0 /*idxParam*/), 1406 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1407 DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/), 1408 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /*idxParam*/), 1409 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructsPostIndexGpr3) 1410 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1411 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1412 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1413 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 3, 0 /*idxParam*/), 1414 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1415 DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/), 1416 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /*idxParam*/), 1417 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructsPostIndexGpr2) 1418 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1419 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1420 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1421 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 2, 0 /*idxParam*/), 1422 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1423 DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/), 1424 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /*idxParam*/), 1425 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructsPostIndexGpr1) 1426 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1427 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1428 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1429 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 1, 0 /*idxParam*/), 1430 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1431 DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff, 16, 5, 1 /*idxParam*/), 1432 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /*idxParam*/), 1433 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStAdvSimdMultStructsPostIndexGpr) 1434 DIS_ARMV8_OP( 0x0c800000, "st4", OP_ARMV8_A64_ST4, DISOPTYPE_HARMLESS), 1435 INVALID_OPCODE, 1436 DIS_ARMV8_OP( 0x0c802000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS), 1437 INVALID_OPCODE, 1438 DIS_ARMV8_OP_ALT_DECODE(0x0c804000, "st3", OP_ARMV8_A64_ST3, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr3), 1439 INVALID_OPCODE, 1440 DIS_ARMV8_OP_ALT_DECODE(0x0c806000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr3), 1441 DIS_ARMV8_OP_ALT_DECODE(0x0c807000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr1), 1442 DIS_ARMV8_OP_ALT_DECODE(0x0c808000, "st2", OP_ARMV8_A64_ST2, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr2), 1443 INVALID_OPCODE, 1444 DIS_ARMV8_OP_ALT_DECODE(0x0c80a000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr2), 1445 INVALID_OPCODE, 1446 INVALID_OPCODE, 1447 INVALID_OPCODE, 1448 INVALID_OPCODE, 1449 INVALID_OPCODE, 1450 DIS_ARMV8_OP( 0x0cc00000, "ld4", OP_ARMV8_A64_LD4, DISOPTYPE_HARMLESS), 1451 INVALID_OPCODE, 1452 DIS_ARMV8_OP( 0x0cc02000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS), 1453 INVALID_OPCODE, 1454 DIS_ARMV8_OP_ALT_DECODE(0x0cc04000, "ld3", OP_ARMV8_A64_LD3, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr3), 1455 INVALID_OPCODE, 1456 DIS_ARMV8_OP_ALT_DECODE(0x0cc06000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr3), 1457 DIS_ARMV8_OP_ALT_DECODE(0x0cc07000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr1), 1458 DIS_ARMV8_OP_ALT_DECODE(0x0cc08000, "ld2", OP_ARMV8_A64_LD2, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr2), 1459 INVALID_OPCODE, 1460 DIS_ARMV8_OP_ALT_DECODE(0x0cc0a000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr2), 1461 /* Rest is invalid */ 1462 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStAdvSimdMultStructsPostIndexGpr, 0xbfe0f000 /*fFixedInsn*/, 1463 kDisArmV8OpcDecodeCollate, 1464 /* opcode */ RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(15) 1465 /* L */ | RT_BIT_32(22), 12); 1466 1467 1468 /** 1469 * C4.1.94.3 - Loads and Stores - Advanced SIMD load/store multiple structures (post-indexed). 1470 * 1471 * Differentiate between the register and immediate offset variant (based on Rm). 1472 */ 1473 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStAdvSimdMultStructsPostIndex) 1474 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1475 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1476 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1477 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1478 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1479 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1480 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1481 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1482 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1483 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1484 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1485 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1486 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1487 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1488 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1489 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1490 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1491 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1492 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1493 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1494 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1495 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1496 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1497 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1498 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1499 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1500 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1501 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1502 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1503 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1504 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1505 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Rm == 11111 (xzr) will be treated as immediate offset encoding. */ 1506 DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStAdvSimdMultStructsPostIndex, 1507 RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19) | RT_BIT_32(20), 1508 16); 1509 1510 1400 1511 /** 1401 1512 * C4.1.94 - Loads and Stores … … 1405 1516 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStAdvSimd) 1406 1517 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructs), 1407 DIS_ARMV8_DECODE_MAP_ INVALID_ENTRY, /** @todo Advanced SIMD load/store multiple structures (post-indexed) */1518 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndex), 1408 1519 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Advanced SIMD load/store single structure */ 1409 1520 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Advanced SIMD load/store single structure (post-indexed) */ -
trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S
r106805 r106816 4150 4150 ld1 { v31.2D, v0.2D }, [sp] 4151 4151 4152 4153 ; 4154 ; Advanced SIMD load/store multiple structures, post-indexed register 4155 ; 4156 4157 st4 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0], x1 4158 st4 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], x30 4159 st4 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0], x1 4160 st4 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], x30 4161 4162 st4 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0], x1 4163 st4 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], x30 4164 st4 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0], x1 4165 st4 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], x30 4166 4167 st4 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0], x1 4168 st4 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], x30 4169 st4 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0], x1 4170 st4 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], x30 4171 4172 st4 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0], x1 4173 st4 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], x30 4174 4175 st1 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0], x1 4176 st1 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], x30 4177 st1 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0], x1 4178 st1 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], x30 4179 4180 st1 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0], x1 4181 st1 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], x30 4182 st1 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0], x1 4183 st1 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], x30 4184 4185 st1 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0], x1 4186 st1 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], x30 4187 st1 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0], x1 4188 st1 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], x30 4189 4190 st1 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0], x1 4191 st1 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], x30 4192 4193 st3 { v0.8B, v1.8B, v2.8B }, [x0], x1 4194 st3 { v31.8B, v0.8B, v1.8B }, [sp], x30 4195 st3 { v0.16B, v1.16B, v2.16B }, [x0], x1 4196 st3 { v31.16B, v0.16B, v1.16B }, [sp], x30 4197 4198 st3 { v0.4H, v1.4H, v2.4H }, [x0], x1 4199 st3 { v31.4H, v0.4H, v1.4H }, [sp], x30 4200 st3 { v0.8H, v1.8H, v2.8H }, [x0], x1 4201 st3 { v31.8H, v0.8H, v1.8H }, [sp], x30 4202 4203 st3 { v0.2S, v1.2S, v2.2S }, [x0], x1 4204 st3 { v31.2S, v0.2S, v1.2S }, [sp], x30 4205 st3 { v0.4S, v1.4S, v2.4S }, [x0], x1 4206 st3 { v31.4S, v0.4S, v1.4S }, [sp], x30 4207 4208 st3 { v0.2D, v1.2D, v2.2D }, [x0], x1 4209 st3 { v31.2D, v0.2D, v1.2D }, [sp], x30 4210 4211 st1 { v0.8B, v1.8B, v2.8B }, [x0], x1 4212 st1 { v31.8B, v0.8B, v1.8B }, [sp], x30 4213 st1 { v0.16B, v1.16B, v2.16B }, [x0], x1 4214 st1 { v31.16B, v0.16B, v1.16B }, [sp], x30 4215 4216 st1 { v0.4H, v1.4H, v2.4H }, [x0], x1 4217 st1 { v31.4H, v0.4H, v1.4H }, [sp], x30 4218 st1 { v0.8H, v1.8H, v2.8H }, [x0], x1 4219 st1 { v31.8H, v0.8H, v1.8H }, [sp], x30 4220 4221 st1 { v0.2S, v1.2S, v2.2S }, [x0], x1 4222 st1 { v31.2S, v0.2S, v1.2S }, [sp], x30 4223 st1 { v0.4S, v1.4S, v2.4S }, [x0], x1 4224 st1 { v31.4S, v0.4S, v1.4S }, [sp], x30 4225 4226 st1 { v0.2D, v1.2D, v2.2D }, [x0], x1 4227 st1 { v31.2D, v0.2D, v1.2D }, [sp], x30 4228 4229 st1 { v0.8B }, [x0], x1 4230 st1 { v31.8B }, [sp], x30 4231 st1 { v0.16B }, [x0], x1 4232 st1 { v31.16B }, [sp], x30 4233 4234 st1 { v0.4H }, [x0], x1 4235 st1 { v31.4H }, [sp], x30 4236 st1 { v0.8H }, [x0], x1 4237 st1 { v31.8H }, [sp], x30 4238 4239 st1 { v0.2S }, [x0], x1 4240 st1 { v31.2S }, [sp], x30 4241 st1 { v0.4S }, [x0], x1 4242 st1 { v31.4S }, [sp], x30 4243 4244 st1 { v0.2D }, [x0], x1 4245 st1 { v31.2D }, [sp], x30 4246 4247 st2 { v0.8B, v1.8B }, [x0], x1 4248 st2 { v31.8B, v0.8B }, [sp], x30 4249 st2 { v0.16B, v1.16B }, [x0], x1 4250 st2 { v31.16B, v0.16B }, [sp], x30 4251 4252 st2 { v0.4H, v1.4H }, [x0], x1 4253 st2 { v31.4H, v0.4H }, [sp], x30 4254 st2 { v0.8H, v1.8H }, [x0], x1 4255 st2 { v31.8H, v0.8H }, [sp], x30 4256 4257 st2 { v0.2S, v1.2S }, [x0], x1 4258 st2 { v31.2S, v0.2S }, [sp], x30 4259 st2 { v0.4S, v1.4S }, [x0], x1 4260 st2 { v31.4S, v0.4S }, [sp], x30 4261 4262 st2 { v0.2D, v1.2D }, [x0], x1 4263 st2 { v31.2D, v0.2D }, [sp], x30 4264 4265 st1 { v0.8B, v1.8B }, [x0], x1 4266 st1 { v31.8B, v0.8B }, [sp], x30 4267 st1 { v0.16B, v1.16B }, [x0], x1 4268 st1 { v31.16B, v0.16B }, [sp], x30 4269 4270 st1 { v0.4H, v1.4H }, [x0], x1 4271 st1 { v31.4H, v0.4H }, [sp], x30 4272 st1 { v0.8H, v1.8H }, [x0], x1 4273 st1 { v31.8H, v0.8H }, [sp], x30 4274 4275 st1 { v0.2S, v1.2S }, [x0], x1 4276 st1 { v31.2S, v0.2S }, [sp], x30 4277 st1 { v0.4S, v1.4S }, [x0], x1 4278 st1 { v31.4S, v0.4S }, [sp], x30 4279 4280 st1 { v0.2D, v1.2D }, [x0], x1 4281 st1 { v31.2D, v0.2D }, [sp], x30 4282 4283 4284 ld4 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0], x1 4285 ld4 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], x30 4286 ld4 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0], x1 4287 ld4 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], x30 4288 4289 ld4 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0], x1 4290 ld4 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], x30 4291 ld4 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0], x1 4292 ld4 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], x30 4293 4294 ld4 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0], x1 4295 ld4 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], x30 4296 ld4 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0], x1 4297 ld4 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], x30 4298 4299 ld4 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0], x1 4300 ld4 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], x30 4301 4302 ld1 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0], x1 4303 ld1 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], x30 4304 ld1 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0], x1 4305 ld1 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], x30 4306 4307 ld1 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0], x1 4308 ld1 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], x30 4309 ld1 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0], x1 4310 ld1 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], x30 4311 4312 ld1 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0], x1 4313 ld1 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], x30 4314 ld1 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0], x1 4315 ld1 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], x30 4316 4317 ld1 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0], x1 4318 ld1 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], x30 4319 4320 ld3 { v0.8B, v1.8B, v2.8B }, [x0], x1 4321 ld3 { v31.8B, v0.8B, v1.8B }, [sp], x30 4322 ld3 { v0.16B, v1.16B, v2.16B }, [x0], x1 4323 ld3 { v31.16B, v0.16B, v1.16B }, [sp], x30 4324 4325 ld3 { v0.4H, v1.4H, v2.4H }, [x0], x1 4326 ld3 { v31.4H, v0.4H, v1.4H }, [sp], x30 4327 ld3 { v0.8H, v1.8H, v2.8H }, [x0], x1 4328 ld3 { v31.8H, v0.8H, v1.8H }, [sp], x30 4329 4330 ld3 { v0.2S, v1.2S, v2.2S }, [x0], x1 4331 ld3 { v31.2S, v0.2S, v1.2S }, [sp], x30 4332 ld3 { v0.4S, v1.4S, v2.4S }, [x0], x1 4333 ld3 { v31.4S, v0.4S, v1.4S }, [sp], x30 4334 4335 ld3 { v0.2D, v1.2D, v2.2D }, [x0], x1 4336 ld3 { v31.2D, v0.2D, v1.2D }, [sp], x30 4337 4338 ld1 { v0.8B, v1.8B, v2.8B }, [x0], x1 4339 ld1 { v31.8B, v0.8B, v1.8B }, [sp], x30 4340 ld1 { v0.16B, v1.16B, v2.16B }, [x0], x1 4341 ld1 { v31.16B, v0.16B, v1.16B }, [sp], x30 4342 4343 ld1 { v0.4H, v1.4H, v2.4H }, [x0], x1 4344 ld1 { v31.4H, v0.4H, v1.4H }, [sp], x30 4345 ld1 { v0.8H, v1.8H, v2.8H }, [x0], x1 4346 ld1 { v31.8H, v0.8H, v1.8H }, [sp], x30 4347 4348 ld1 { v0.2S, v1.2S, v2.2S }, [x0], x1 4349 ld1 { v31.2S, v0.2S, v1.2S }, [sp], x30 4350 ld1 { v0.4S, v1.4S, v2.4S }, [x0], x1 4351 ld1 { v31.4S, v0.4S, v1.4S }, [sp], x30 4352 4353 ld1 { v0.2D, v1.2D, v2.2D }, [x0], x1 4354 ld1 { v31.2D, v0.2D, v1.2D }, [sp], x30 4355 4356 ld1 { v0.8B }, [x0], x1 4357 ld1 { v31.8B }, [sp], x30 4358 ld1 { v0.16B }, [x0], x1 4359 ld1 { v31.16B }, [sp], x30 4360 4361 ld1 { v0.4H }, [x0], x1 4362 ld1 { v31.4H }, [sp], x30 4363 ld1 { v0.8H }, [x0], x1 4364 ld1 { v31.8H }, [sp], x30 4365 4366 ld1 { v0.2S }, [x0], x1 4367 ld1 { v31.2S }, [sp], x30 4368 ld1 { v0.4S }, [x0], x1 4369 ld1 { v31.4S }, [sp], x30 4370 4371 ld1 { v0.2D }, [x0], x1 4372 ld1 { v31.2D }, [sp], x30 4373 4374 ld2 { v0.8B, v1.8B }, [x0], x1 4375 ld2 { v31.8B, v0.8B }, [sp], x30 4376 ld2 { v0.16B, v1.16B }, [x0], x1 4377 ld2 { v31.16B, v0.16B }, [sp], x30 4378 4379 ld2 { v0.4H, v1.4H }, [x0], x1 4380 ld2 { v31.4H, v0.4H }, [sp], x30 4381 ld2 { v0.8H, v1.8H }, [x0], x1 4382 ld2 { v31.8H, v0.8H }, [sp], x30 4383 4384 ld2 { v0.2S, v1.2S }, [x0], x1 4385 ld2 { v31.2S, v0.2S }, [sp], x30 4386 ld2 { v0.4S, v1.4S }, [x0], x1 4387 ld2 { v31.4S, v0.4S }, [sp], x30 4388 4389 ld2 { v0.2D, v1.2D }, [x0], x1 4390 ld2 { v31.2D, v0.2D }, [sp], x30 4391 4392 ld1 { v0.8B, v1.8B }, [x0], x1 4393 ld1 { v31.8B, v0.8B }, [sp], x30 4394 ld1 { v0.16B, v1.16B }, [x0], x1 4395 ld1 { v31.16B, v0.16B }, [sp], x30 4396 4397 ld1 { v0.4H, v1.4H }, [x0], x1 4398 ld1 { v31.4H, v0.4H }, [sp], x30 4399 ld1 { v0.8H, v1.8H }, [x0], x1 4400 ld1 { v31.8H, v0.8H }, [sp], x30 4401 4402 ld1 { v0.2S, v1.2S }, [x0], x1 4403 ld1 { v31.2S, v0.2S }, [sp], x30 4404 ld1 { v0.4S, v1.4S }, [x0], x1 4405 ld1 { v31.4S, v0.4S }, [sp], x30 4406 4407 ld1 { v0.2D, v1.2D }, [x0], x1 4408 ld1 { v31.2D, v0.2D }, [sp], x30 4409 4410 4152 4411 ; 4153 4412 ; RCW compare and swap
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