Index: /trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp	(revision 106815)
+++ /trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp	(revision 106816)
@@ -924,7 +924,4 @@
                     Assert(   (pParam->fUse & (DISUSE_PRE_INDEXED | DISUSE_POST_INDEXED))
                            != (DISUSE_PRE_INDEXED | DISUSE_POST_INDEXED));
-                    Assert(   (   RT_BOOL(pParam->fUse & (DISUSE_PRE_INDEXED | DISUSE_POST_INDEXED))
-                               != RT_BOOL(pParam->fUse & DISUSE_INDEX))
-                           || !(pParam->fUse & (DISUSE_PRE_INDEXED | DISUSE_POST_INDEXED | DISUSE_INDEX)));
 
                     PUT_C('[');
@@ -938,6 +935,23 @@
                     {
                         Assert(pParam->armv8.enmExtend == kDisArmv8OpParmExtendNone);
-                        PUT_SZ("], #");
-                        PUT_NUM_S16(pParam->armv8.u.offBase);
+                        PUT_C(']');
+                        if (pParam->fUse & DISUSE_INDEX)
+                        {
+                            PUT_SZ(", ");
+
+                            pszReg = disasmFormatArmV8Reg(pDis, pParam->armv8.GprIndex.enmRegType,
+                                                          pParam->armv8.GprIndex.idReg, &cchReg);
+                            PUT_STR(pszReg, cchReg);
+                        }
+                        else if (   pParam->armv8.u.offBase
+                                 || (pParam->fUse & (DISUSE_POST_INDEXED | DISUSE_PRE_INDEXED)))
+                        {
+                            PUT_SZ(", #");
+                            if (   pParam->armv8.u.offBase >= INT16_MIN
+                                && pParam->armv8.u.offBase <= INT16_MAX)
+                                PUT_NUM_S16(pParam->armv8.u.offBase);
+                            else
+                                PUT_NUM_S32(pParam->armv8.u.offBase);
+                        }
                     }
                     else
Index: /trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h
===================================================================
--- /trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h	(revision 106815)
+++ /trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h	(revision 106816)
@@ -1398,4 +1398,115 @@
 
 
+/* C4.1.94.3 - Loads and Stores - Advanced SIMD load/store multiple structures (post-indexed), register variant. */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStAdvSimdMultStructsPostIndexGpr)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10,  2, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ,           30,  1, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp,          0,  4, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,       5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff,         16,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed,  0,  0, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructsPostIndexGpr3)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10,  2, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ,           30,  1, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp,          0,  3, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,       5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff,         16,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed,  0,  0, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructsPostIndexGpr2)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10,  2, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ,           30,  1, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp,          0,  2, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,       5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff,         16,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed,  0,  0, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructsPostIndexGpr1)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10,  2, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ,           30,  1, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg,          0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp,          0,  1, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,       5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseGprOff,         16,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed,  0,  0, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStAdvSimdMultStructsPostIndexGpr)
+    DIS_ARMV8_OP(           0x0c800000, "st4",             OP_ARMV8_A64_ST4,     DISOPTYPE_HARMLESS),
+    INVALID_OPCODE,
+    DIS_ARMV8_OP(           0x0c802000, "st1",             OP_ARMV8_A64_ST1,     DISOPTYPE_HARMLESS),
+    INVALID_OPCODE,
+    DIS_ARMV8_OP_ALT_DECODE(0x0c804000, "st3",             OP_ARMV8_A64_ST3,     DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr3),
+    INVALID_OPCODE,
+    DIS_ARMV8_OP_ALT_DECODE(0x0c806000, "st1",             OP_ARMV8_A64_ST1,     DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr3),
+    DIS_ARMV8_OP_ALT_DECODE(0x0c807000, "st1",             OP_ARMV8_A64_ST1,     DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr1),
+    DIS_ARMV8_OP_ALT_DECODE(0x0c808000, "st2",             OP_ARMV8_A64_ST2,     DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr2),
+    INVALID_OPCODE,
+    DIS_ARMV8_OP_ALT_DECODE(0x0c80a000, "st1",             OP_ARMV8_A64_ST1,     DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr2),
+    INVALID_OPCODE,
+    INVALID_OPCODE,
+    INVALID_OPCODE,
+    INVALID_OPCODE,
+    INVALID_OPCODE,
+    DIS_ARMV8_OP(           0x0cc00000, "ld4",             OP_ARMV8_A64_LD4,     DISOPTYPE_HARMLESS),
+    INVALID_OPCODE,
+    DIS_ARMV8_OP(           0x0cc02000, "ld1",             OP_ARMV8_A64_LD1,     DISOPTYPE_HARMLESS),
+    INVALID_OPCODE,
+    DIS_ARMV8_OP_ALT_DECODE(0x0cc04000, "ld3",             OP_ARMV8_A64_LD3,     DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr3),
+    INVALID_OPCODE,
+    DIS_ARMV8_OP_ALT_DECODE(0x0cc06000, "ld1",             OP_ARMV8_A64_LD1,     DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr3),
+    DIS_ARMV8_OP_ALT_DECODE(0x0cc07000, "ld1",             OP_ARMV8_A64_LD1,     DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr1),
+    DIS_ARMV8_OP_ALT_DECODE(0x0cc08000, "ld2",             OP_ARMV8_A64_LD2,     DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr2),
+    INVALID_OPCODE,
+    DIS_ARMV8_OP_ALT_DECODE(0x0cc0a000, "ld1",             OP_ARMV8_A64_LD1,     DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexGpr2),
+    /* Rest is invalid */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStAdvSimdMultStructsPostIndexGpr, 0xbfe0f000 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeCollate,
+                        /* opcode */     RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(15)
+                        /* L      */   | RT_BIT_32(22), 12);
+
+
+/**
+ * C4.1.94.3 - Loads and Stores - Advanced SIMD load/store multiple structures (post-indexed).
+ *
+ * Differentiate between the register and immediate offset variant (based on Rm).
+ */
+DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStAdvSimdMultStructsPostIndex)
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr),
+    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Rm == 11111 (xzr) will be treated as immediate offset encoding. */
+DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStAdvSimdMultStructsPostIndex,
+                                RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19) | RT_BIT_32(20),
+                                16);
+
+
 /**
  * C4.1.94 - Loads and Stores
@@ -1405,5 +1516,5 @@
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStAdvSimd)
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructs),
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Advanced SIMD load/store multiple structures (post-indexed) */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndex),
     DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Advanced SIMD load/store single structure */
     DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Advanced SIMD load/store single structure (post-indexed) */
Index: /trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S
===================================================================
--- /trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S	(revision 106815)
+++ /trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S	(revision 106816)
@@ -4150,4 +4150,263 @@
         ld1 { v31.2D, v0.2D }, [sp]
 
+
+        ;
+        ; Advanced SIMD load/store multiple structures, post-indexed register
+        ;
+
+        st4 { v0.8B,  v1.8B, v2.8B, v3.8B }, [x0], x1
+        st4 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], x30
+        st4 { v0.16B,  v1.16B, v2.16B, v3.16B }, [x0], x1
+        st4 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], x30
+
+        st4 { v0.4H,  v1.4H, v2.4H, v3.4H }, [x0], x1
+        st4 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], x30
+        st4 { v0.8H,  v1.8H, v2.8H, v3.8H }, [x0], x1
+        st4 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], x30
+
+        st4 { v0.2S,  v1.2S, v2.2S, v3.2S }, [x0], x1
+        st4 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], x30
+        st4 { v0.4S,  v1.4S, v2.4S, v3.4S }, [x0], x1
+        st4 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], x30
+
+        st4 { v0.2D,  v1.2D, v2.2D, v3.2D }, [x0], x1
+        st4 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], x30
+
+        st1 { v0.8B,  v1.8B, v2.8B, v3.8B }, [x0], x1
+        st1 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], x30
+        st1 { v0.16B,  v1.16B, v2.16B, v3.16B }, [x0], x1
+        st1 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], x30
+
+        st1 { v0.4H,  v1.4H, v2.4H, v3.4H }, [x0], x1
+        st1 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], x30
+        st1 { v0.8H,  v1.8H, v2.8H, v3.8H }, [x0], x1
+        st1 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], x30
+
+        st1 { v0.2S,  v1.2S, v2.2S, v3.2S }, [x0], x1
+        st1 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], x30
+        st1 { v0.4S,  v1.4S, v2.4S, v3.4S }, [x0], x1
+        st1 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], x30
+
+        st1 { v0.2D,  v1.2D, v2.2D, v3.2D }, [x0], x1
+        st1 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], x30
+
+        st3 { v0.8B,  v1.8B, v2.8B }, [x0], x1
+        st3 { v31.8B, v0.8B, v1.8B }, [sp], x30
+        st3 { v0.16B,  v1.16B, v2.16B }, [x0], x1
+        st3 { v31.16B, v0.16B, v1.16B }, [sp], x30
+
+        st3 { v0.4H,  v1.4H, v2.4H }, [x0], x1
+        st3 { v31.4H, v0.4H, v1.4H }, [sp], x30
+        st3 { v0.8H,  v1.8H, v2.8H }, [x0], x1
+        st3 { v31.8H, v0.8H, v1.8H }, [sp], x30
+
+        st3 { v0.2S,  v1.2S, v2.2S }, [x0], x1
+        st3 { v31.2S, v0.2S, v1.2S }, [sp], x30
+        st3 { v0.4S,  v1.4S, v2.4S }, [x0], x1
+        st3 { v31.4S, v0.4S, v1.4S }, [sp], x30
+
+        st3 { v0.2D,  v1.2D, v2.2D }, [x0], x1
+        st3 { v31.2D, v0.2D, v1.2D }, [sp], x30
+
+        st1 { v0.8B,  v1.8B, v2.8B }, [x0], x1
+        st1 { v31.8B, v0.8B, v1.8B }, [sp], x30
+        st1 { v0.16B,  v1.16B, v2.16B }, [x0], x1
+        st1 { v31.16B, v0.16B, v1.16B }, [sp], x30
+
+        st1 { v0.4H,  v1.4H, v2.4H }, [x0], x1
+        st1 { v31.4H, v0.4H, v1.4H }, [sp], x30
+        st1 { v0.8H,  v1.8H, v2.8H }, [x0], x1
+        st1 { v31.8H, v0.8H, v1.8H }, [sp], x30
+
+        st1 { v0.2S,  v1.2S, v2.2S }, [x0], x1
+        st1 { v31.2S, v0.2S, v1.2S }, [sp], x30
+        st1 { v0.4S,  v1.4S, v2.4S }, [x0], x1
+        st1 { v31.4S, v0.4S, v1.4S }, [sp], x30
+
+        st1 { v0.2D,  v1.2D, v2.2D }, [x0], x1
+        st1 { v31.2D, v0.2D, v1.2D }, [sp], x30
+
+        st1 { v0.8B }, [x0], x1
+        st1 { v31.8B }, [sp], x30
+        st1 { v0.16B }, [x0], x1
+        st1 { v31.16B }, [sp], x30
+
+        st1 { v0.4H }, [x0], x1
+        st1 { v31.4H }, [sp], x30
+        st1 { v0.8H }, [x0], x1
+        st1 { v31.8H }, [sp], x30
+
+        st1 { v0.2S }, [x0], x1
+        st1 { v31.2S }, [sp], x30
+        st1 { v0.4S }, [x0], x1
+        st1 { v31.4S }, [sp], x30
+
+        st1 { v0.2D }, [x0], x1
+        st1 { v31.2D }, [sp], x30
+
+        st2 { v0.8B,  v1.8B }, [x0], x1
+        st2 { v31.8B, v0.8B }, [sp], x30
+        st2 { v0.16B,  v1.16B }, [x0], x1
+        st2 { v31.16B, v0.16B }, [sp], x30
+
+        st2 { v0.4H,  v1.4H }, [x0], x1
+        st2 { v31.4H, v0.4H }, [sp], x30
+        st2 { v0.8H,  v1.8H }, [x0], x1
+        st2 { v31.8H, v0.8H }, [sp], x30
+
+        st2 { v0.2S,  v1.2S }, [x0], x1
+        st2 { v31.2S, v0.2S }, [sp], x30
+        st2 { v0.4S,  v1.4S }, [x0], x1
+        st2 { v31.4S, v0.4S }, [sp], x30
+
+        st2 { v0.2D,  v1.2D }, [x0], x1
+        st2 { v31.2D, v0.2D }, [sp], x30
+
+        st1 { v0.8B,  v1.8B }, [x0], x1
+        st1 { v31.8B, v0.8B }, [sp], x30
+        st1 { v0.16B,  v1.16B }, [x0], x1
+        st1 { v31.16B, v0.16B }, [sp], x30
+
+        st1 { v0.4H,  v1.4H }, [x0], x1
+        st1 { v31.4H, v0.4H }, [sp], x30
+        st1 { v0.8H,  v1.8H }, [x0], x1
+        st1 { v31.8H, v0.8H }, [sp], x30
+
+        st1 { v0.2S,  v1.2S }, [x0], x1
+        st1 { v31.2S, v0.2S }, [sp], x30
+        st1 { v0.4S,  v1.4S }, [x0], x1
+        st1 { v31.4S, v0.4S }, [sp], x30
+
+        st1 { v0.2D,  v1.2D }, [x0], x1
+        st1 { v31.2D, v0.2D }, [sp], x30
+
+
+        ld4 { v0.8B,  v1.8B, v2.8B, v3.8B }, [x0], x1
+        ld4 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], x30
+        ld4 { v0.16B,  v1.16B, v2.16B, v3.16B }, [x0], x1
+        ld4 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], x30
+
+        ld4 { v0.4H,  v1.4H, v2.4H, v3.4H }, [x0], x1
+        ld4 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], x30
+        ld4 { v0.8H,  v1.8H, v2.8H, v3.8H }, [x0], x1
+        ld4 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], x30
+
+        ld4 { v0.2S,  v1.2S, v2.2S, v3.2S }, [x0], x1
+        ld4 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], x30
+        ld4 { v0.4S,  v1.4S, v2.4S, v3.4S }, [x0], x1
+        ld4 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], x30
+
+        ld4 { v0.2D,  v1.2D, v2.2D, v3.2D }, [x0], x1
+        ld4 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], x30
+
+        ld1 { v0.8B,  v1.8B, v2.8B, v3.8B }, [x0], x1
+        ld1 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], x30
+        ld1 { v0.16B,  v1.16B, v2.16B, v3.16B }, [x0], x1
+        ld1 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], x30
+
+        ld1 { v0.4H,  v1.4H, v2.4H, v3.4H }, [x0], x1
+        ld1 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], x30
+        ld1 { v0.8H,  v1.8H, v2.8H, v3.8H }, [x0], x1
+        ld1 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], x30
+
+        ld1 { v0.2S,  v1.2S, v2.2S, v3.2S }, [x0], x1
+        ld1 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], x30
+        ld1 { v0.4S,  v1.4S, v2.4S, v3.4S }, [x0], x1
+        ld1 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], x30
+
+        ld1 { v0.2D,  v1.2D, v2.2D, v3.2D }, [x0], x1
+        ld1 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], x30
+
+        ld3 { v0.8B,  v1.8B, v2.8B }, [x0], x1
+        ld3 { v31.8B, v0.8B, v1.8B }, [sp], x30
+        ld3 { v0.16B,  v1.16B, v2.16B }, [x0], x1
+        ld3 { v31.16B, v0.16B, v1.16B }, [sp], x30
+
+        ld3 { v0.4H,  v1.4H, v2.4H }, [x0], x1
+        ld3 { v31.4H, v0.4H, v1.4H }, [sp], x30
+        ld3 { v0.8H,  v1.8H, v2.8H }, [x0], x1
+        ld3 { v31.8H, v0.8H, v1.8H }, [sp], x30
+
+        ld3 { v0.2S,  v1.2S, v2.2S }, [x0], x1
+        ld3 { v31.2S, v0.2S, v1.2S }, [sp], x30
+        ld3 { v0.4S,  v1.4S, v2.4S }, [x0], x1
+        ld3 { v31.4S, v0.4S, v1.4S }, [sp], x30
+
+        ld3 { v0.2D,  v1.2D, v2.2D }, [x0], x1
+        ld3 { v31.2D, v0.2D, v1.2D }, [sp], x30
+
+        ld1 { v0.8B,  v1.8B, v2.8B }, [x0], x1
+        ld1 { v31.8B, v0.8B, v1.8B }, [sp], x30
+        ld1 { v0.16B,  v1.16B, v2.16B }, [x0], x1
+        ld1 { v31.16B, v0.16B, v1.16B }, [sp], x30
+
+        ld1 { v0.4H,  v1.4H, v2.4H }, [x0], x1
+        ld1 { v31.4H, v0.4H, v1.4H }, [sp], x30
+        ld1 { v0.8H,  v1.8H, v2.8H }, [x0], x1
+        ld1 { v31.8H, v0.8H, v1.8H }, [sp], x30
+
+        ld1 { v0.2S,  v1.2S, v2.2S }, [x0], x1
+        ld1 { v31.2S, v0.2S, v1.2S }, [sp], x30
+        ld1 { v0.4S,  v1.4S, v2.4S }, [x0], x1
+        ld1 { v31.4S, v0.4S, v1.4S }, [sp], x30
+
+        ld1 { v0.2D,  v1.2D, v2.2D }, [x0], x1
+        ld1 { v31.2D, v0.2D, v1.2D }, [sp], x30
+
+        ld1 { v0.8B }, [x0], x1
+        ld1 { v31.8B }, [sp], x30
+        ld1 { v0.16B }, [x0], x1
+        ld1 { v31.16B }, [sp], x30
+
+        ld1 { v0.4H }, [x0], x1
+        ld1 { v31.4H }, [sp], x30
+        ld1 { v0.8H }, [x0], x1
+        ld1 { v31.8H }, [sp], x30
+
+        ld1 { v0.2S }, [x0], x1
+        ld1 { v31.2S }, [sp], x30
+        ld1 { v0.4S }, [x0], x1
+        ld1 { v31.4S }, [sp], x30
+
+        ld1 { v0.2D }, [x0], x1
+        ld1 { v31.2D }, [sp], x30
+
+        ld2 { v0.8B,  v1.8B }, [x0], x1
+        ld2 { v31.8B, v0.8B }, [sp], x30
+        ld2 { v0.16B,  v1.16B }, [x0], x1
+        ld2 { v31.16B, v0.16B }, [sp], x30
+
+        ld2 { v0.4H,  v1.4H }, [x0], x1
+        ld2 { v31.4H, v0.4H }, [sp], x30
+        ld2 { v0.8H,  v1.8H }, [x0], x1
+        ld2 { v31.8H, v0.8H }, [sp], x30
+
+        ld2 { v0.2S,  v1.2S }, [x0], x1
+        ld2 { v31.2S, v0.2S }, [sp], x30
+        ld2 { v0.4S,  v1.4S }, [x0], x1
+        ld2 { v31.4S, v0.4S }, [sp], x30
+
+        ld2 { v0.2D,  v1.2D }, [x0], x1
+        ld2 { v31.2D, v0.2D }, [sp], x30
+
+        ld1 { v0.8B,  v1.8B }, [x0], x1
+        ld1 { v31.8B, v0.8B }, [sp], x30
+        ld1 { v0.16B,  v1.16B }, [x0], x1
+        ld1 { v31.16B, v0.16B }, [sp], x30
+
+        ld1 { v0.4H,  v1.4H }, [x0], x1
+        ld1 { v31.4H, v0.4H }, [sp], x30
+        ld1 { v0.8H,  v1.8H }, [x0], x1
+        ld1 { v31.8H, v0.8H }, [sp], x30
+
+        ld1 { v0.2S,  v1.2S }, [x0], x1
+        ld1 { v31.2S, v0.2S }, [sp], x30
+        ld1 { v0.4S,  v1.4S }, [x0], x1
+        ld1 { v31.4S, v0.4S }, [sp], x30
+
+        ld1 { v0.2D,  v1.2D }, [x0], x1
+        ld1 { v31.2D, v0.2D }, [sp], x30
+
+
         ;
         ; RCW compare and swap
