Changeset 106817 in vbox
- Timestamp:
- Nov 1, 2024 10:06:53 AM (3 months ago)
- Location:
- trunk/src/VBox/Disassembler
- Files:
-
- 4 edited
-
DisasmCore-armv8.cpp (modified) (3 diffs)
-
DisasmInternal-armv8.h (modified) (1 diff)
-
DisasmTables-armv8-a64-ld-st.cpp.h (modified) (2 diffs)
-
testcase/tstDisasmArmv8-1-asm.S (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp
r106805 r106817 122 122 static FNDISPARSEARMV8 disArmV8ParseVecRegQ; 123 123 static FNDISPARSEARMV8 disArmV8ParseVecGrp; 124 static FNDISPARSEARMV8 disArmV8ParseSimdLdStPostIndexImm; 124 125 /** @} */ 125 126 … … 188 189 disArmV8ParseVecRegElemSize, 189 190 disArmV8ParseVecRegQ, 190 disArmV8ParseVecGrp 191 disArmV8ParseVecGrp, 192 disArmV8ParseSimdLdStPostIndexImm 191 193 }; 192 194 … … 1177 1179 1178 1180 1181 static int disArmV8ParseSimdLdStPostIndexImm(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit) 1182 { 1183 RT_NOREF(pDis, u32Insn, pOp, pInsnClass, pParam, pInsnParm, pf64Bit); 1184 1185 /* 1186 * Special decoder for Advanced SIMD load/store multiple structures (post-indexed), immediate variant. 1187 * The immediate for when Q == 0 is stored in idxBitStart, and cBits when Q == 1. 1188 */ 1189 Assert(pInsnParm->cBits == 16 || pInsnParm->cBits == 32 || pInsnParm->cBits == 48 || pInsnParm->cBits == 64); 1190 Assert(pInsnParm->idxBitStart == 8 || pInsnParm->idxBitStart == 16 || pInsnParm->idxBitStart == 24 || pInsnParm->idxBitStart == 32); 1191 Assert(pParam->armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_64Bit || pParam->armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Sp); 1192 pParam->armv8.u.offBase = RT_BOOL(u32Insn & RT_BIT_32(30)) ? pInsnParm->cBits : pInsnParm->idxBitStart; 1193 return VINF_SUCCESS; 1194 } 1195 1196 1179 1197 static uint32_t disArmV8DecodeIllegal(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass) 1180 1198 { -
trunk/src/VBox/Disassembler/DisasmInternal-armv8.h
r106805 r106817 100 100 kDisParmParseVecQ, 101 101 kDisParmParseVecGrp, 102 kDisParmParseSimdLdStPostIndexImm, 102 103 kDisParmParseMax 103 104 } DISPARMPARSEIDX; -
trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h
r106816 r106817 1466 1466 1467 1467 1468 /* C4.1.94.3 - Loads and Stores - Advanced SIMD load/store multiple structures (post-indexed), register variant. */ 1469 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStAdvSimdMultStructsPostIndexImm) 1470 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1471 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1472 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1473 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 4, 0 /*idxParam*/), 1474 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1475 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdLdStPostIndexImm, 32, 64, 1 /*idxParam*/), 1476 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /*idxParam*/), 1477 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructsPostIndexImm3) 1478 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1479 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1480 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1481 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 3, 0 /*idxParam*/), 1482 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1483 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdLdStPostIndexImm, 24, 48, 1 /*idxParam*/), 1484 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /*idxParam*/), 1485 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructsPostIndexImm2) 1486 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1487 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1488 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1489 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 2, 0 /*idxParam*/), 1490 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1491 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdLdStPostIndexImm, 16, 32, 1 /*idxParam*/), 1492 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /*idxParam*/), 1493 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStAdvSimdMultStructsPostIndexImm1) 1494 DIS_ARMV8_INSN_DECODE(kDisParmParseVecRegElemSize, 10, 2, DIS_ARMV8_INSN_PARAM_UNSET), 1495 DIS_ARMV8_INSN_DECODE(kDisParmParseVecQ, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 1496 DIS_ARMV8_INSN_DECODE(kDisParmParseVecReg, 0, 5, 0 /*idxParam*/), 1497 DIS_ARMV8_INSN_DECODE(kDisParmParseVecGrp, 0, 1, 0 /*idxParam*/), 1498 DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp, 5, 5, 1 /*idxParam*/), 1499 DIS_ARMV8_INSN_DECODE(kDisParmParseSimdLdStPostIndexImm, 8, 16, 1 /*idxParam*/), 1500 DIS_ARMV8_INSN_DECODE(kDisParmParseSetPostIndexed, 0, 0, 1 /*idxParam*/), 1501 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStAdvSimdMultStructsPostIndexImm) 1502 DIS_ARMV8_OP( 0x0c9f0000, "st4", OP_ARMV8_A64_ST4, DISOPTYPE_HARMLESS), 1503 INVALID_OPCODE, 1504 DIS_ARMV8_OP( 0x0c9f2000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS), 1505 INVALID_OPCODE, 1506 DIS_ARMV8_OP_ALT_DECODE(0x0c9f4000, "st3", OP_ARMV8_A64_ST3, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexImm3), 1507 INVALID_OPCODE, 1508 DIS_ARMV8_OP_ALT_DECODE(0x0c9f6000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexImm3), 1509 DIS_ARMV8_OP_ALT_DECODE(0x0c9f7000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexImm1), 1510 DIS_ARMV8_OP_ALT_DECODE(0x0c9f8000, "st2", OP_ARMV8_A64_ST2, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexImm2), 1511 INVALID_OPCODE, 1512 DIS_ARMV8_OP_ALT_DECODE(0x0c9fa000, "st1", OP_ARMV8_A64_ST1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexImm2), 1513 INVALID_OPCODE, 1514 INVALID_OPCODE, 1515 INVALID_OPCODE, 1516 INVALID_OPCODE, 1517 INVALID_OPCODE, 1518 DIS_ARMV8_OP( 0x0cdf0000, "ld4", OP_ARMV8_A64_LD4, DISOPTYPE_HARMLESS), 1519 INVALID_OPCODE, 1520 DIS_ARMV8_OP( 0x0cdf2000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS), 1521 INVALID_OPCODE, 1522 DIS_ARMV8_OP_ALT_DECODE(0x0cdf4000, "ld3", OP_ARMV8_A64_LD3, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexImm3), 1523 INVALID_OPCODE, 1524 DIS_ARMV8_OP_ALT_DECODE(0x0cdf6000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexImm3), 1525 DIS_ARMV8_OP_ALT_DECODE(0x0cdf7000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexImm1), 1526 DIS_ARMV8_OP_ALT_DECODE(0x0cdf8000, "ld2", OP_ARMV8_A64_LD2, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexImm2), 1527 INVALID_OPCODE, 1528 DIS_ARMV8_OP_ALT_DECODE(0x0cdfa000, "ld1", OP_ARMV8_A64_LD1, DISOPTYPE_HARMLESS, LdStAdvSimdMultStructsPostIndexImm2), 1529 /* Rest is invalid */ 1530 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStAdvSimdMultStructsPostIndexImm, 0xbffff000 /*fFixedInsn*/, 1531 kDisArmV8OpcDecodeCollate, 1532 /* opcode */ RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) | RT_BIT_32(15) 1533 /* L */ | RT_BIT_32(22), 12); 1534 1535 1468 1536 /** 1469 1537 * C4.1.94.3 - Loads and Stores - Advanced SIMD load/store multiple structures (post-indexed). … … 1503 1571 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1504 1572 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexGpr), 1505 DIS_ARMV8_DECODE_MAP_ INVALID_ENTRY, /* Rm == 11111 (xzr) will be treated as immediate offset encoding. */1573 DIS_ARMV8_DECODE_MAP_ENTRY(LdStAdvSimdMultStructsPostIndexImm), /* Rm == 11111 (xzr) will be treated as immediate offset encoding. */ 1506 1574 DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStAdvSimdMultStructsPostIndex, 1507 1575 RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19) | RT_BIT_32(20), -
trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S
r106816 r106817 4410 4410 4411 4411 ; 4412 ; Advanced SIMD load/store multiple structures, post-indexed immediate 4413 ; 4414 4415 st4 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0], #32 4416 st4 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], #32 4417 st4 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0], #64 4418 st4 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], #64 4419 4420 st4 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0], #32 4421 st4 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], #32 4422 st4 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0], #64 4423 st4 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], #64 4424 4425 st4 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0], #32 4426 st4 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], #32 4427 st4 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0], #64 4428 st4 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], #64 4429 4430 st4 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0], #64 4431 st4 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], #64 4432 4433 st1 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0], #32 4434 st1 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], #32 4435 st1 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0], #64 4436 st1 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], #64 4437 4438 st1 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0], #32 4439 st1 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], #32 4440 st1 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0], #64 4441 st1 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], #64 4442 4443 st1 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0], #32 4444 st1 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], #32 4445 st1 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0], #64 4446 st1 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], #64 4447 4448 st1 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0], #64 4449 st1 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], #64 4450 4451 st3 { v0.8B, v1.8B, v2.8B }, [x0], #24 4452 st3 { v31.8B, v0.8B, v1.8B }, [sp], #24 4453 st3 { v0.16B, v1.16B, v2.16B }, [x0], #48 4454 st3 { v31.16B, v0.16B, v1.16B }, [sp], #48 4455 4456 st3 { v0.4H, v1.4H, v2.4H }, [x0], #24 4457 st3 { v31.4H, v0.4H, v1.4H }, [sp], #24 4458 st3 { v0.8H, v1.8H, v2.8H }, [x0], #48 4459 st3 { v31.8H, v0.8H, v1.8H }, [sp], #48 4460 4461 st3 { v0.2S, v1.2S, v2.2S }, [x0], #24 4462 st3 { v31.2S, v0.2S, v1.2S }, [sp], #24 4463 st3 { v0.4S, v1.4S, v2.4S }, [x0], #48 4464 st3 { v31.4S, v0.4S, v1.4S }, [sp], #48 4465 4466 st3 { v0.2D, v1.2D, v2.2D }, [x0], #48 4467 st3 { v31.2D, v0.2D, v1.2D }, [sp], #48 4468 4469 st1 { v0.8B, v1.8B, v2.8B }, [x0], #24 4470 st1 { v31.8B, v0.8B, v1.8B }, [sp], #24 4471 st1 { v0.16B, v1.16B, v2.16B }, [x0], #48 4472 st1 { v31.16B, v0.16B, v1.16B }, [sp], #48 4473 4474 st1 { v0.4H, v1.4H, v2.4H }, [x0], #24 4475 st1 { v31.4H, v0.4H, v1.4H }, [sp], #24 4476 st1 { v0.8H, v1.8H, v2.8H }, [x0], #48 4477 st1 { v31.8H, v0.8H, v1.8H }, [sp], #48 4478 4479 st1 { v0.2S, v1.2S, v2.2S }, [x0], #24 4480 st1 { v31.2S, v0.2S, v1.2S }, [sp], #24 4481 st1 { v0.4S, v1.4S, v2.4S }, [x0], #48 4482 st1 { v31.4S, v0.4S, v1.4S }, [sp], #48 4483 4484 st1 { v0.2D, v1.2D, v2.2D }, [x0], #48 4485 st1 { v31.2D, v0.2D, v1.2D }, [sp], #48 4486 4487 st1 { v0.8B }, [x0], #8 4488 st1 { v31.8B }, [sp], #8 4489 st1 { v0.16B }, [x0], #16 4490 st1 { v31.16B }, [sp], #16 4491 4492 st1 { v0.4H }, [x0], #8 4493 st1 { v31.4H }, [sp], #8 4494 st1 { v0.8H }, [x0], #16 4495 st1 { v31.8H }, [sp], #16 4496 4497 st1 { v0.2S }, [x0], #8 4498 st1 { v31.2S }, [sp], #8 4499 st1 { v0.4S }, [x0], #16 4500 st1 { v31.4S }, [sp], #16 4501 4502 st1 { v0.2D }, [x0], #16 4503 st1 { v31.2D }, [sp], #16 4504 4505 st2 { v0.8B, v1.8B }, [x0], #16 4506 st2 { v31.8B, v0.8B }, [sp], #16 4507 st2 { v0.16B, v1.16B }, [x0], #32 4508 st2 { v31.16B, v0.16B }, [sp], #32 4509 4510 st2 { v0.4H, v1.4H }, [x0], #16 4511 st2 { v31.4H, v0.4H }, [sp], #16 4512 st2 { v0.8H, v1.8H }, [x0], #32 4513 st2 { v31.8H, v0.8H }, [sp], #32 4514 4515 st2 { v0.2S, v1.2S }, [x0], #16 4516 st2 { v31.2S, v0.2S }, [sp], #16 4517 st2 { v0.4S, v1.4S }, [x0], #32 4518 st2 { v31.4S, v0.4S }, [sp], #32 4519 4520 st2 { v0.2D, v1.2D }, [x0], #32 4521 st2 { v31.2D, v0.2D }, [sp], #32 4522 4523 st1 { v0.8B, v1.8B }, [x0], #16 4524 st1 { v31.8B, v0.8B }, [sp], #16 4525 st1 { v0.16B, v1.16B }, [x0], #32 4526 st1 { v31.16B, v0.16B }, [sp], #32 4527 4528 st1 { v0.4H, v1.4H }, [x0], #16 4529 st1 { v31.4H, v0.4H }, [sp], #16 4530 st1 { v0.8H, v1.8H }, [x0], #32 4531 st1 { v31.8H, v0.8H }, [sp], #32 4532 4533 st1 { v0.2S, v1.2S }, [x0], #16 4534 st1 { v31.2S, v0.2S }, [sp], #16 4535 st1 { v0.4S, v1.4S }, [x0], #32 4536 st1 { v31.4S, v0.4S }, [sp], #32 4537 4538 st1 { v0.2D, v1.2D }, [x0], #32 4539 st1 { v31.2D, v0.2D }, [sp], #32 4540 4541 4542 ld4 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0], #32 4543 ld4 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], #32 4544 ld4 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0], #64 4545 ld4 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], #64 4546 4547 ld4 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0], #32 4548 ld4 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], #32 4549 ld4 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0], #64 4550 ld4 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], #64 4551 4552 ld4 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0], #32 4553 ld4 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], #32 4554 ld4 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0], #64 4555 ld4 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], #64 4556 4557 ld4 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0], #64 4558 ld4 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], #64 4559 4560 ld1 { v0.8B, v1.8B, v2.8B, v3.8B }, [x0], #32 4561 ld1 { v31.8B, v0.8B, v1.8B, v2.8B }, [sp], #32 4562 ld1 { v0.16B, v1.16B, v2.16B, v3.16B }, [x0], #64 4563 ld1 { v31.16B, v0.16B, v1.16B, v2.16B }, [sp], #64 4564 4565 ld1 { v0.4H, v1.4H, v2.4H, v3.4H }, [x0], #32 4566 ld1 { v31.4H, v0.4H, v1.4H, v2.4H }, [sp], #32 4567 ld1 { v0.8H, v1.8H, v2.8H, v3.8H }, [x0], #64 4568 ld1 { v31.8H, v0.8H, v1.8H, v2.8H }, [sp], #64 4569 4570 ld1 { v0.2S, v1.2S, v2.2S, v3.2S }, [x0], #32 4571 ld1 { v31.2S, v0.2S, v1.2S, v2.2S }, [sp], #32 4572 ld1 { v0.4S, v1.4S, v2.4S, v3.4S }, [x0], #64 4573 ld1 { v31.4S, v0.4S, v1.4S, v2.4S }, [sp], #64 4574 4575 ld1 { v0.2D, v1.2D, v2.2D, v3.2D }, [x0], #64 4576 ld1 { v31.2D, v0.2D, v1.2D, v2.2D }, [sp], #64 4577 4578 ld3 { v0.8B, v1.8B, v2.8B }, [x0], #24 4579 ld3 { v31.8B, v0.8B, v1.8B }, [sp], #24 4580 ld3 { v0.16B, v1.16B, v2.16B }, [x0], #48 4581 ld3 { v31.16B, v0.16B, v1.16B }, [sp], #48 4582 4583 ld3 { v0.4H, v1.4H, v2.4H }, [x0], #24 4584 ld3 { v31.4H, v0.4H, v1.4H }, [sp], #24 4585 ld3 { v0.8H, v1.8H, v2.8H }, [x0], #48 4586 ld3 { v31.8H, v0.8H, v1.8H }, [sp], #48 4587 4588 ld3 { v0.2S, v1.2S, v2.2S }, [x0], #24 4589 ld3 { v31.2S, v0.2S, v1.2S }, [sp], #24 4590 ld3 { v0.4S, v1.4S, v2.4S }, [x0], #48 4591 ld3 { v31.4S, v0.4S, v1.4S }, [sp], #48 4592 4593 ld3 { v0.2D, v1.2D, v2.2D }, [x0], #48 4594 ld3 { v31.2D, v0.2D, v1.2D }, [sp], #48 4595 4596 ld1 { v0.8B, v1.8B, v2.8B }, [x0], #24 4597 ld1 { v31.8B, v0.8B, v1.8B }, [sp], #24 4598 ld1 { v0.16B, v1.16B, v2.16B }, [x0], #48 4599 ld1 { v31.16B, v0.16B, v1.16B }, [sp], #48 4600 4601 ld1 { v0.4H, v1.4H, v2.4H }, [x0], #24 4602 ld1 { v31.4H, v0.4H, v1.4H }, [sp], #24 4603 ld1 { v0.8H, v1.8H, v2.8H }, [x0], #48 4604 ld1 { v31.8H, v0.8H, v1.8H }, [sp], #48 4605 4606 ld1 { v0.2S, v1.2S, v2.2S }, [x0], #24 4607 ld1 { v31.2S, v0.2S, v1.2S }, [sp], #24 4608 ld1 { v0.4S, v1.4S, v2.4S }, [x0], #48 4609 ld1 { v31.4S, v0.4S, v1.4S }, [sp], #48 4610 4611 ld1 { v0.2D, v1.2D, v2.2D }, [x0], #48 4612 ld1 { v31.2D, v0.2D, v1.2D }, [sp], #48 4613 4614 ld1 { v0.8B }, [x0], #8 4615 ld1 { v31.8B }, [sp], #8 4616 ld1 { v0.16B }, [x0], #16 4617 ld1 { v31.16B }, [sp], #16 4618 4619 ld1 { v0.4H }, [x0], #8 4620 ld1 { v31.4H }, [sp], #8 4621 ld1 { v0.8H }, [x0], #16 4622 ld1 { v31.8H }, [sp], #16 4623 4624 ld1 { v0.2S }, [x0], #8 4625 ld1 { v31.2S }, [sp], #8 4626 ld1 { v0.4S }, [x0], #16 4627 ld1 { v31.4S }, [sp], #16 4628 4629 ld1 { v0.2D }, [x0], #16 4630 ld1 { v31.2D }, [sp], #16 4631 4632 ld2 { v0.8B, v1.8B }, [x0], #16 4633 ld2 { v31.8B, v0.8B }, [sp], #16 4634 ld2 { v0.16B, v1.16B }, [x0], #32 4635 ld2 { v31.16B, v0.16B }, [sp], #32 4636 4637 ld2 { v0.4H, v1.4H }, [x0], #16 4638 ld2 { v31.4H, v0.4H }, [sp], #16 4639 ld2 { v0.8H, v1.8H }, [x0], #32 4640 ld2 { v31.8H, v0.8H }, [sp], #32 4641 4642 ld2 { v0.2S, v1.2S }, [x0], #16 4643 ld2 { v31.2S, v0.2S }, [sp], #16 4644 ld2 { v0.4S, v1.4S }, [x0], #32 4645 ld2 { v31.4S, v0.4S }, [sp], #32 4646 4647 ld2 { v0.2D, v1.2D }, [x0], #32 4648 ld2 { v31.2D, v0.2D }, [sp], #32 4649 4650 ld1 { v0.8B, v1.8B }, [x0], #16 4651 ld1 { v31.8B, v0.8B }, [sp], #16 4652 ld1 { v0.16B, v1.16B }, [x0], #32 4653 ld1 { v31.16B, v0.16B }, [sp], #32 4654 4655 ld1 { v0.4H, v1.4H }, [x0], #16 4656 ld1 { v31.4H, v0.4H }, [sp], #16 4657 ld1 { v0.8H, v1.8H }, [x0], #32 4658 ld1 { v31.8H, v0.8H }, [sp], #32 4659 4660 ld1 { v0.2S, v1.2S }, [x0], #16 4661 ld1 { v31.2S, v0.2S }, [sp], #16 4662 ld1 { v0.4S, v1.4S }, [x0], #32 4663 ld1 { v31.4S, v0.4S }, [sp], #32 4664 4665 ld1 { v0.2D, v1.2D }, [x0], #32 4666 ld1 { v31.2D, v0.2D }, [sp], #32 4667 4668 4669 ; 4412 4670 ; RCW compare and swap 4413 4671 ;
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