Changeset 106818 in vbox
- Timestamp:
- Nov 4, 2024 11:11:57 AM (5 months ago)
- svn:sync-xref-src-repo-rev:
- 165722
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-4-template.mac (modified) (4 diffs)
-
bs3-cpu-instr-4.c32 (modified) (70 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
r106815 r106818 1161 1161 ; SSE-128, int32 <- fp32 (packed:4; truncated) 1162 1162 EMIT_INSTR_PLUS_ICEBP cvttps2dq, XMM1, XMM2 1163 EMIT_INSTR_PLUS_ICEBP cvttps2dq, XMM1, FSxBX _O1163 EMIT_INSTR_PLUS_ICEBP cvttps2dq, XMM1, FSxBX 1164 1164 EMIT_INSTR_PLUS_ICEBP_C64 cvttps2dq, XMM8, XMM9 1165 EMIT_INSTR_PLUS_ICEBP_C64 cvttps2dq, XMM8, FSxBX _O1165 EMIT_INSTR_PLUS_ICEBP_C64 cvttps2dq, XMM8, FSxBX 1166 1166 ; AVX-128, int32 <- fp32 (packed:4; truncated) 1167 1167 EMIT_INSTR_PLUS_ICEBP vcvttps2dq, XMM1, XMM2 1168 EMIT_INSTR_PLUS_ICEBP vcvttps2dq, XMM1, FSxBX _O1168 EMIT_INSTR_PLUS_ICEBP vcvttps2dq, XMM1, FSxBX 1169 1169 EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, XMM8, XMM9 1170 EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, XMM8, FSxBX _O1170 EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, XMM8, FSxBX 1171 1171 ; AVX-256, int32 <- fp32 (packed:8; truncated) 1172 1172 EMIT_INSTR_PLUS_ICEBP vcvttps2dq, YMM1, YMM2 1173 EMIT_INSTR_PLUS_ICEBP vcvttps2dq, YMM1, FSxBX _Y1173 EMIT_INSTR_PLUS_ICEBP vcvttps2dq, YMM1, FSxBX 1174 1174 EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, YMM8, YMM9 1175 EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, YMM8, FSxBX _Y1175 EMIT_INSTR_PLUS_ICEBP_C64 vcvttps2dq, YMM8, FSxBX 1176 1176 ; AVX-128, int32 <- fp32, same-reg (packed:4; truncated) 1177 1177 EMIT_INSTR_PLUS_ICEBP cvttps2dq, XMM1, XMM1 … … 1227 1227 ; AVX-256, int32 <- fp64 (packed:4) 1228 1228 EMIT_INSTR_PLUS_ICEBP vcvtpd2dq, XMM1, YMM2 1229 EMIT_INSTR_PLUS_ICEBP vcvtpd2dq, YMM1, FSxBX1229 EMIT_INSTR_PLUS_ICEBP vcvtpd2dq, XMM1, FSxBX_Y 1230 1230 EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2dq, XMM8, YMM9 1231 EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2dq, YMM8, FSxBX1231 EMIT_INSTR_PLUS_ICEBP_C64 vcvtpd2dq, XMM8, FSxBX_Y 1232 1232 ; SSE-128, int32 <- fp64, same-reg (packed:2) 1233 1233 EMIT_INSTR_PLUS_ICEBP cvtpd2dq, XMM1, XMM1 … … 1245 1245 ; SSE-128, int32 <- fp64 (packed:2; truncated) 1246 1246 EMIT_INSTR_PLUS_ICEBP cvttpd2dq, XMM1, XMM2 1247 EMIT_INSTR_PLUS_ICEBP cvttpd2dq, XMM1, FSxBX _O1247 EMIT_INSTR_PLUS_ICEBP cvttpd2dq, XMM1, FSxBX 1248 1248 EMIT_INSTR_PLUS_ICEBP_C64 cvttpd2dq, XMM8, XMM9 1249 EMIT_INSTR_PLUS_ICEBP_C64 cvttpd2dq, XMM8, FSxBX _O1249 EMIT_INSTR_PLUS_ICEBP_C64 cvttpd2dq, XMM8, FSxBX 1250 1250 ; AVX-128, int32 <- fp64 (packed:2; truncated) 1251 1251 EMIT_INSTR_PLUS_ICEBP vcvttpd2dq, XMM1, XMM2 1252 EMIT_INSTR_PLUS_ICEBP vcvttpd2dq, XMM1, FSxBX _O1252 EMIT_INSTR_PLUS_ICEBP vcvttpd2dq, XMM1, FSxBX 1253 1253 EMIT_INSTR_PLUS_ICEBP_C64 vcvttpd2dq, XMM8, XMM9 1254 EMIT_INSTR_PLUS_ICEBP_C64 vcvttpd2dq, XMM8, FSxBX _O1254 EMIT_INSTR_PLUS_ICEBP_C64 vcvttpd2dq, XMM8, FSxBX 1255 1255 ; AVX-256, int32 <- fp64 (packed:4; truncated) 1256 1256 EMIT_INSTR_PLUS_ICEBP vcvttpd2dq, XMM1, YMM2 … … 1311 1311 ; AVX-256, fp64 <- fp32 (packed:4) 1312 1312 EMIT_INSTR_PLUS_ICEBP vcvtps2pd, YMM1, XMM2 1313 EMIT_INSTR_PLUS_ICEBP vcvtps2pd, YMM1, FSxBX _O1313 EMIT_INSTR_PLUS_ICEBP vcvtps2pd, YMM1, FSxBX 1314 1314 EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2pd, YMM8, XMM9 1315 EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2pd, YMM8, FSxBX _O1315 EMIT_INSTR_PLUS_ICEBP_C64 vcvtps2pd, YMM8, FSxBX 1316 1316 ; SSE-128, fp64 <- fp32, same-reg (packed:2) 1317 1317 EMIT_INSTR_PLUS_ICEBP cvtps2pd, XMM1, XMM1 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106815 r106818 286 286 * of instructions which convert between types. 287 287 */ 288 #define INT32_INDEF INITE_C 0x80000000UL289 #define INT64_INDEF INITE_C 0x8000000000000000ULL288 #define INT32_INDEF_C 0x80000000UL 289 #define INT64_INDEF_C 0x8000000000000000ULL 290 290 291 291 #define FP32_INT_SIGN_PART(a_uInt32) ((((uint32_t)(a_uInt32)) >> 31) & 1) … … 296 296 #define FP32_INT64(a_uInt64) FP32_INT((a_uInt64) & 0xFFFFFFFF), FP32_INT((a_uInt64) >> 32) 297 297 #define FP32_INT64_C(a_uInt64) FP32_INT64(UINT64_C(a_uInt64)) 298 #define FP32_INT_INDEF INITE FP32_INT(INT32_INDEFINITE_C)299 #define FP32_INT64_INDEF INITE FP32_INT64(INT64_INDEFINITE_C)298 #define FP32_INT_INDEF FP32_INT(INT32_INDEF_C) 299 #define FP32_INT64_INDEF FP32_INT64(INT64_INDEF_C) 300 300 301 301 #define FP64_INT_SIGN_PART(a_uInt64) ((((uint64_t)(a_uInt64)) >> 63) & 1) … … 306 306 #define FP64_INT32(a_uInt32_1, a_uInt32_2) FP64_INT(((uint64_t)(a_uInt32_1)) | (((uint64_t)(a_uInt32_2)) << 32)) 307 307 #define FP64_INT32_C(a_uInt32_1, a_uInt32_2) FP64_INT32(UINT32_C(a_uInt32_1), UINT32_C(a_uInt32_2)) 308 #define FP64_INT_INDEFINITE FP64_INT(INT64_INDEFINITE_C) 309 #define FP64_INT32_INDEFINITE(a_uInt32_2) FP64_INT32(INT32_INDEFINITE_C, a_uInt32_2) 308 #define FP64_INT_INDEF FP64_INT(INT64_INDEF_C) 309 #define FP64_INT32_INDEF(a_uInt32_2) FP64_INT32(INT32_INDEF_C, a_uInt32_2) 310 #define FP64_INT32_INDEFx2 FP64_INT32(INT32_INDEF_C, INT32_INDEF_C) 310 311 311 312 /* … … 496 497 RM_REG = 0, 497 498 RM_MEM, 498 RM_MEM8, /**< Memory operand is 8 bytes. Hack for movss and similar. */ 499 RM_MEM16, /**< Memory operand is 16 bytes. Hack for movss and similar. */ 500 RM_MEM32, /**< Memory operand is 32 bytes. Hack for movss and similar. */ 501 RM_MEM64 /**< Memory operand is 64 bytes. Hack for movss and similar. */ 499 RM_MEM8, /**< Memory operand is 8 bits. */ 500 RM_MEM16, /**< Memory operand is 16 bits. */ 501 RM_MEM32, /**< Memory operand is 32 bits. */ 502 RM_MEM64, /**< Memory operand is 64 bits. */ 503 RM_MEM128, /**< Memory operand is 128 bits. */ 504 RM_MEM256, /**< Memory operand is 256 bits. */ 502 505 }; 503 506 … … 2347 2350 if (enmRm == RM_MEM64) 2348 2351 return sizeof(uint64_t); 2352 if (enmRm == RM_MEM128) 2353 return sizeof(RTUINT128U); 2354 if (enmRm == RM_MEM256) 2355 return sizeof(RTUINT256U); 2349 2356 BS3_ASSERT(0); 2350 2357 return cbOperand; … … 2597 2604 #define BS3_XCPT_NEVER 0x40 2598 2605 #define BS3_XCPT_NOT_MF (X86_XCPT_MF | BS3_XCPT_NEVER) 2606 #define BS3_XCPT_NOT_AC (X86_XCPT_AC | BS3_XCPT_NEVER) 2599 2607 2600 2608 typedef struct BS3CPUINSTR4_TEST1_MODE_T … … 2614 2622 #define PASS_s_aValues32 PASS_s_aArray(s_aValues32) 2615 2623 #define PASS_s_aValues64 PASS_s_aArray(s_aValues64) 2624 #define PASS_s_aValuesX PASS_s_aArray(s_aValuesX) 2625 #define PASS_s_aValuesY PASS_s_aArray(s_aValuesY) 2616 2626 2617 2627 typedef struct BS3CPUINSTR4_TEST1_CTX_T … … 3013 3023 if (cErrors != Bs3TestSubErrorCount()) 3014 3024 { 3015 #define PUMEMOP_MAXSIZE sizeof("puMemOp=0x0123456789abcdef, EFLAGS=0x01234567, ")3025 #define PUMEMOP_MAXSIZE sizeof("puMemOp=0x0123456789abcdef, cbMemOp=256, ") 3016 3026 char szPuMemOpStr[PUMEMOP_MAXSIZE] = ""; 3017 3027 3018 3028 if (!pTestCtx->pConfig->fAligned) 3019 Bs3StrPrintf(szPuMemOpStr, PUMEMOP_MAXSIZE, "puMemOp=%p, EFLAGS=%#RX32, ", puMemOp, pTestCtx->pTrapFrame->Ctx.rflags.u32);3029 Bs3StrPrintf(szPuMemOpStr, PUMEMOP_MAXSIZE, "puMemOp=%p, cbMemOp=%u, ", puMemOp, cbMemOp); 3020 3030 Bs3TestFailedF("%s/%s failed (bXcptExpect=%u %s, %s%s-%u)", 3021 3031 pTestCtx->pszTestIdStr, s_apszMaskTyp[iMaskType], bXcptExpect, bs3CpuInstr4XcptName(bXcptExpect), … … 3095 3105 uint8_t BS3_FAR *puMemOp = bs3CpuInstrXBufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg], fPf); 3096 3106 uint8_t *puMemOpAlias = &g_pbBufAlias[(uintptr_t)puMemOp - (uintptr_t)pbBuf]; 3107 uint8_t const bXcptAlt = pTest->bAltXcpt != 255 && ((pTest->bAltXcpt & (BS3_XCPT_ALWAYS | BS3_XCPT_NEVER)) == 0) ? pTest->bAltXcpt : 0; 3108 uint8_t const bXcptAlways = pTest->bAltXcpt != 255 && (pTest->bAltXcpt & BS3_XCPT_ALWAYS) ? pTest->bAltXcpt & ~BS3_XCPT_ALWAYS : 0; 3109 uint8_t const bXcptNever = pTest->bAltXcpt != 255 && (pTest->bAltXcpt & BS3_XCPT_NEVER) ? pTest->bAltXcpt & ~BS3_XCPT_NEVER : 0; 3097 3110 uint8_t bXcptExpect = !g_afTypeSupports[pTest->enmType] ? X86_XCPT_UD 3098 : pTest->bAltXcpt & BS3_XCPT_ALWAYS && pTest->bAltXcpt != 255 ? pTest->bAltXcpt & ~BS3_XCPT_ALWAYS3111 : bXcptAlways ? bXcptAlways 3099 3112 : fSseInstr ? paConfigs[iCfg].bXcptSse 3100 3113 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; … … 3116 3129 if (bRing != 3) 3117 3130 bXcptExpect = X86_XCPT_DB; 3118 else if (fAvxInstr && pTest->bAltXcpt != 255)3119 bXcptExpect = pTest->bAltXcpt; /* they generally don't raise #AC */3131 else if (fAvxInstr && bXcptAlt) 3132 bXcptExpect = bXcptAlt; /* they generally don't raise #AC */ 3120 3133 } 3121 3134 3122 if ( (pTest->bAltXcpt & BS3_XCPT_NEVER) && (pTest->bAltXcpt != 255) && (bXcptExpect == (pTest->bAltXcpt & ~BS3_XCPT_NEVER)))3135 if (bXcptNever && bXcptExpect == bXcptNever) 3123 3136 bXcptExpect = X86_XCPT_DB; 3124 3137 … … 3200 3213 # define TODO_X86_MXCSR_PE_IEM_SSE 3201 3214 # define TODO_X86_MXCSR_UE_IEM 3215 # define TODO_CVTDQ2PD_M64_IEM 3202 3216 #endif /* TODO_EXPOSE_IEM_ERRATA */ 3217 3218 /** @todo Additionally, tons of things fail in IEM built without 'IEM_WITHOUT_ASSEMBLY=1'; 3219 * the 'normal' no-ifdefs path mostly succeeds WITH 'IEM_WITHOUT_ASSEMBLY=1'; cause(s) TBD. 3220 * (Problem build is hypothetically the same as 'IEM_WITH_ASSEMBLY=1'; but haven't tested that.) 3221 */ 3203 3222 3204 3223 … … 16428 16447 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 16429 16448 /*256:out */ -1 }, 16449 /* 16450 * Not invalid, but unusual: Intel define the 'indefinite integer' as 10000...0b 16451 */ 16452 /* 8*/{ { /*init dst */ { FP32_RAND_V1(0), FP32_RAND_V3(1), FP32_RAND_x6_V0 } }, 16453 { /* src mm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_RAND_x6_V2 } }, 16454 { /* => xmm */ { FP32_V(1,0,0x9e), FP32_V(1,0,0x9e), FP32_RAND_x6_V0 } }, 16455 /*mxcsr:in */ 0, 16456 /*128:out */ 0, 16457 /*256:out */ 0 }, 16430 16458 }; 16431 16459 /* … … 16435 16463 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 16436 16464 { 16437 { bs3CpuInstr4_cvtpi2ps_XMM1_MM1_icebp_c16, 255, RM_REG, T_SSE , XMM1, MM1, XMM1, PASS_s_aValues },16438 { bs3CpuInstr4_cvtpi2ps_XMM1_FSxBX_icebp_c16, BS3_XCPT_NOT_MF, RM_MEM, T_SSE , XMM1, FSxBX, XMM1, PASS_s_aValues },16465 { bs3CpuInstr4_cvtpi2ps_XMM1_MM1_icebp_c16, 255, RM_REG, T_SSE2, XMM1, MM1, XMM1, PASS_s_aValues }, 16466 { bs3CpuInstr4_cvtpi2ps_XMM1_FSxBX_icebp_c16, BS3_XCPT_NOT_MF, RM_MEM, T_SSE2, XMM1, FSxBX, XMM1, PASS_s_aValues }, 16439 16467 }; 16440 16468 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 16441 16469 { 16442 { bs3CpuInstr4_cvtpi2ps_XMM1_MM1_icebp_c32, 255, RM_REG, T_SSE , XMM1, MM1, XMM1, PASS_s_aValues },16443 { bs3CpuInstr4_cvtpi2ps_XMM1_FSxBX_icebp_c32, BS3_XCPT_NOT_MF, RM_MEM, T_SSE , XMM1, FSxBX, XMM1, PASS_s_aValues },16470 { bs3CpuInstr4_cvtpi2ps_XMM1_MM1_icebp_c32, 255, RM_REG, T_SSE2, XMM1, MM1, XMM1, PASS_s_aValues }, 16471 { bs3CpuInstr4_cvtpi2ps_XMM1_FSxBX_icebp_c32, BS3_XCPT_NOT_MF, RM_MEM, T_SSE2, XMM1, FSxBX, XMM1, PASS_s_aValues }, 16444 16472 }; 16445 16473 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 16446 16474 { 16447 { bs3CpuInstr4_cvtpi2ps_XMM1_MM1_icebp_c64, 255, RM_REG, T_SSE , XMM1, MM1, XMM1, PASS_s_aValues },16448 { bs3CpuInstr4_cvtpi2ps_XMM1_FSxBX_icebp_c64, BS3_XCPT_NOT_MF, RM_MEM, T_SSE , XMM1, FSxBX, XMM1, PASS_s_aValues },16449 { bs3CpuInstr4_cvtpi2ps_XMM8_MM1_icebp_c64, 255, RM_REG, T_SSE , XMM8, MM1, XMM8, PASS_s_aValues },16450 { bs3CpuInstr4_cvtpi2ps_XMM8_FSxBX_icebp_c64, BS3_XCPT_NOT_MF, RM_MEM, T_SSE , XMM8, FSxBX, XMM8, PASS_s_aValues },16475 { bs3CpuInstr4_cvtpi2ps_XMM1_MM1_icebp_c64, 255, RM_REG, T_SSE2, XMM1, MM1, XMM1, PASS_s_aValues }, 16476 { bs3CpuInstr4_cvtpi2ps_XMM1_FSxBX_icebp_c64, BS3_XCPT_NOT_MF, RM_MEM, T_SSE2, XMM1, FSxBX, XMM1, PASS_s_aValues }, 16477 { bs3CpuInstr4_cvtpi2ps_XMM8_MM1_icebp_c64, 255, RM_REG, T_SSE2, XMM8, MM1, XMM8, PASS_s_aValues }, 16478 { bs3CpuInstr4_cvtpi2ps_XMM8_FSxBX_icebp_c64, BS3_XCPT_NOT_MF, RM_MEM, T_SSE2, XMM8, FSxBX, XMM8, PASS_s_aValues }, 16451 16479 }; 16452 16480 … … 16478 16506 */ 16479 16507 /* 1*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16480 { /* src xmm */ { FP32_INF(1), FP32_INF(0),FP32_RAND_x6_V1 } },16481 { /* => mm */ { FP32_INT_INDEF INITE, FP32_INT_INDEFINITE, FP32_x6_UNUSED } },16508 { /* src xmm */ { FP32_INF(1), FP32_INF(0), FP32_RAND_x6_V1 } }, 16509 { /* => mm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_x6_UNUSED } }, 16482 16510 /*mxcsr:in */ 0, 16483 16511 /*128:out */ X86_MXCSR_IE, … … 16552 16580 */ 16553 16581 /*11*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16554 { /* src xmm */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1),FP32_RAND_x6_V2 } },16555 { /* => mm */ { FP32_INT_INDEF INITE, FP32_INT_INDEFINITE,FP32_x6_UNUSED } },16582 { /* src xmm */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_RAND_x6_V2 } }, 16583 { /* => mm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_x6_UNUSED } }, 16556 16584 /*mxcsr:in */ 0, 16557 16585 /*128:out */ X86_MXCSR_IE, … … 16561 16589 */ 16562 16590 /*12*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16563 { /* src xmm */ { FP32_QNAN(0), FP32_QNAN(1),FP32_RAND_x6_V2 } },16564 { /* => mm */ { FP32_INT_INDEF INITE, FP32_INT_INDEFINITE, FP32_x6_UNUSED } },16591 { /* src xmm */ { FP32_QNAN(0), FP32_QNAN(1), FP32_RAND_x6_V2 } }, 16592 { /* => mm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_x6_UNUSED } }, 16565 16593 /*mxcsr:in */ 0, 16566 16594 /*128:out */ X86_MXCSR_IE, 16567 16595 /*256:out */ -1 }, 16568 16596 { { /* unused */ { FP32_ROW_UNUSED } }, 16569 { /* src xmm */ { FP32_SNAN(1), FP32_SNAN(0),FP32_RAND_x6_V2 } },16570 { /* => mm */ { FP32_INT_INDEF INITE, FP32_INT_INDEFINITE, FP32_x6_UNUSED } },16597 { /* src xmm */ { FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_x6_V2 } }, 16598 { /* => mm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_x6_UNUSED } }, 16571 16599 /*mxcsr:in */ 0, 16572 16600 /*128:out */ X86_MXCSR_IE, … … 16576 16604 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 16577 16605 { 16578 { bs3CpuInstr4_cvtps2pi_MM1_XMM1_icebp_c16, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },16579 { bs3CpuInstr4_cvtps2pi_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },16606 { bs3CpuInstr4_cvtps2pi_MM1_XMM1_icebp_c16, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 16607 { bs3CpuInstr4_cvtps2pi_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 16580 16608 }; 16581 16609 16582 16610 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 16583 16611 { 16584 { bs3CpuInstr4_cvtps2pi_MM1_XMM1_icebp_c32, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },16585 { bs3CpuInstr4_cvtps2pi_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },16612 { bs3CpuInstr4_cvtps2pi_MM1_XMM1_icebp_c32, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 16613 { bs3CpuInstr4_cvtps2pi_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 16586 16614 }; 16587 16615 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 16588 16616 { 16589 { bs3CpuInstr4_cvtps2pi_MM1_XMM1_icebp_c64, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },16590 { bs3CpuInstr4_cvtps2pi_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },16591 { bs3CpuInstr4_cvtps2pi_MM1_XMM8_icebp_c64, 255, RM_REG, T_SSE , MM1, XMM8, NOREG, PASS_s_aValues },16617 { bs3CpuInstr4_cvtps2pi_MM1_XMM1_icebp_c64, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 16618 { bs3CpuInstr4_cvtps2pi_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 16619 { bs3CpuInstr4_cvtps2pi_MM1_XMM8_icebp_c64, 255, RM_REG, T_SSE2, MM1, XMM8, NOREG, PASS_s_aValues }, 16592 16620 }; 16593 16621 … … 16619 16647 */ 16620 16648 /* 1*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16621 { /* src xmm */ { FP32_INF(1), FP32_INF(0),FP32_RAND_x6_V1 } },16622 { /* => mm */ { FP32_INT_INDEF INITE, FP32_INT_INDEFINITE, FP32_x6_UNUSED } },16649 { /* src xmm */ { FP32_INF(1), FP32_INF(0), FP32_RAND_x6_V1 } }, 16650 { /* => mm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_x6_UNUSED } }, 16623 16651 /*mxcsr:in */ 0, 16624 16652 /*128:out */ X86_MXCSR_IE, … … 16693 16721 */ 16694 16722 /*11*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16695 { /* src xmm */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1),FP32_RAND_x6_V2 } },16696 { /* => mm */ { FP32_INT_INDEF INITE, FP32_INT_INDEFINITE,FP32_x6_UNUSED } },16723 { /* src xmm */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_RAND_x6_V2 } }, 16724 { /* => mm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_x6_UNUSED } }, 16697 16725 /*mxcsr:in */ 0, 16698 16726 /*128:out */ X86_MXCSR_IE, … … 16702 16730 */ 16703 16731 /*12*/{ { /* unused */ { FP32_ROW_UNUSED } }, 16704 { /* src xmm */ { FP32_QNAN(0), FP32_QNAN(1),FP32_RAND_x6_V2 } },16705 { /* => mm */ { FP32_INT_INDEF INITE, FP32_INT_INDEFINITE, FP32_x6_UNUSED } },16732 { /* src xmm */ { FP32_QNAN(0), FP32_QNAN(1), FP32_RAND_x6_V2 } }, 16733 { /* => mm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_x6_UNUSED } }, 16706 16734 /*mxcsr:in */ 0, 16707 16735 /*128:out */ X86_MXCSR_IE, 16708 16736 /*256:out */ -1 }, 16709 16737 { { /* unused */ { FP32_ROW_UNUSED } }, 16710 { /* src xmm */ { FP32_SNAN(1), FP32_SNAN(0),FP32_RAND_x6_V2 } },16711 { /* => mm */ { FP32_INT_INDEF INITE, FP32_INT_INDEFINITE, FP32_x6_UNUSED } },16738 { /* src xmm */ { FP32_SNAN(1), FP32_SNAN(0), FP32_RAND_x6_V2 } }, 16739 { /* => mm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_x6_UNUSED } }, 16712 16740 /*mxcsr:in */ 0, 16713 16741 /*128:out */ X86_MXCSR_IE, … … 16717 16745 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 16718 16746 { 16719 { bs3CpuInstr4_cvttps2pi_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },16720 { bs3CpuInstr4_cvttps2pi_MM1_XMM1_icebp_c16, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },16747 { bs3CpuInstr4_cvttps2pi_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 16748 { bs3CpuInstr4_cvttps2pi_MM1_XMM1_icebp_c16, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 16721 16749 }; 16722 16750 16723 16751 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 16724 16752 { 16725 { bs3CpuInstr4_cvttps2pi_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },16726 { bs3CpuInstr4_cvttps2pi_MM1_XMM1_icebp_c32, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },16753 { bs3CpuInstr4_cvttps2pi_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 16754 { bs3CpuInstr4_cvttps2pi_MM1_XMM1_icebp_c32, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 16727 16755 }; 16728 16756 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 16729 16757 { 16730 { bs3CpuInstr4_cvttps2pi_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },16731 { bs3CpuInstr4_cvttps2pi_MM1_XMM1_icebp_c64, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },16732 { bs3CpuInstr4_cvttps2pi_MM1_XMM8_icebp_c64, 255, RM_REG, T_SSE , MM1, XMM8, NOREG, PASS_s_aValues },16758 { bs3CpuInstr4_cvttps2pi_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 16759 { bs3CpuInstr4_cvttps2pi_MM1_XMM1_icebp_c64, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 16760 { bs3CpuInstr4_cvttps2pi_MM1_XMM8_icebp_c64, 255, RM_REG, T_SSE2, MM1, XMM8, NOREG, PASS_s_aValues }, 16733 16761 }; 16734 16762 … … 16843 16871 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 16844 16872 /*256:out */ -1 }, 16873 /* 16874 * Not invalid, but unusual: Intel define the 'indefinite integer' as 10000...0b 16875 */ 16876 /*13*/{ { /* src r32 */ { FP32_INT_INDEF, FP32_RAND_x7_V4 } }, 16877 { /* src xmm */ { FP32_NORM_V0(0), FP32_RAND_x7_V3 } }, 16878 { /* => xmm */ { FP32_V(1,0,0x9e), FP32_RAND_x7_V3 } }, 16879 /*mxcsr:in */ 0, 16880 /*128:out */ 0, 16881 /*256:out */ -1 }, 16845 16882 }; 16846 16883 … … 16949 16986 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 16950 16987 /*256:out */ -1 }, 16988 /* 16989 * Not invalid, but unusual: Intel define the 'indefinite integer' as 10000...0b 16990 */ 16991 /*14*/{ { /* src r64 */ { FP32_INT64_INDEF, FP32_RAND_x6_V4 } }, 16992 { /* src xmm */ { FP32_NORM_V0(0), FP32_RAND_x7_V3 } }, 16993 { /* => xmm */ { FP32_V(1,0,0xbe), FP32_RAND_x7_V3 } }, 16994 /*mxcsr:in */ 0, 16995 /*128:out */ 0, 16996 /*256:out */ -1 }, 16951 16997 }; 16952 16998 /* … … 17052 17098 * Infinity. 17053 17099 */ 17054 /* 2*/{ { /* clr r64 */ { FP32_INT64_C(0), 17055 { /* src xmm */ { FP32_INF(1), 17056 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17100 /* 2*/{ { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17101 { /* src xmm */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 17102 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17057 17103 /*mxcsr:in */ 0, 17058 17104 /*128:out */ X86_MXCSR_IE, 17059 17105 /*256:out */ -1 }, 17060 { { /* clr r64 */ { FP32_INT64_C(0), 17061 { /* src xmm */ { FP32_INF(0), 17062 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17106 { { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17107 { /* src xmm */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 17108 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17063 17109 /*mxcsr:in */ 0, 17064 17110 /*128:out */ X86_MXCSR_IE, … … 17181 17227 * Overflow (Underflow not possible). 17182 17228 */ 17183 /*22*/{ { /* clr r64 */ { FP32_INT64_C(0), 17184 { /* src xmm */ { FP32_NORM_MAX(0), 17185 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17229 /*22*/{ { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17230 { /* src xmm */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 17231 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17186 17232 /*mxcsr:in */ 0, 17187 17233 /*128:out */ X86_MXCSR_IE, 17188 17234 /*256:out */ -1 }, 17189 { { /* clr r64 */ { FP32_INT64_C(0), 17190 { /* src xmm */ { FP32_NORM_MAX(1), 17191 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17235 { { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17236 { /* src xmm */ { FP32_NORM_MAX(1), FP32_RAND_x7_V2 } }, 17237 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17192 17238 /*mxcsr:in */ 0, 17193 17239 /*128:out */ X86_MXCSR_IE, … … 17196 17242 * Invalids. 17197 17243 */ 17198 /*24*/{ { /* clr r64 */ { FP32_INT64_C(0), 17199 { /* src xmm */ { FP32_QNAN(0), 17200 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17244 /*24*/{ { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17245 { /* src xmm */ { FP32_QNAN(0), FP32_RAND_x7_V2 } }, 17246 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17201 17247 /*mxcsr:in */ 0, 17202 17248 /*128:out */ X86_MXCSR_IE, 17203 17249 /*256:out */ -1 }, 17204 { { /* clr r64 */ { FP32_INT64_C(0), 17205 { /* src xmm */ { FP32_SNAN(1), 17206 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17250 { { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17251 { /* src xmm */ { FP32_SNAN(1), FP32_RAND_x7_V2 } }, 17252 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17207 17253 /*mxcsr:in */ 0, 17208 17254 /*128:out */ X86_MXCSR_IE, … … 17230 17276 */ 17231 17277 /* 2*/{ { /* unused */ { FP32_ROW_UNUSED } }, 17232 { /* src xmm */ { FP32_INF(1), 17233 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17278 { /* src xmm */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 17279 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17234 17280 /*mxcsr:in */ 0, 17235 17281 /*128:out */ X86_MXCSR_IE, 17236 17282 /*256:out */ -1 }, 17237 17283 { { /* unused */ { FP32_ROW_UNUSED } }, 17238 { /* src xmm */ { FP32_INF(0), 17239 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17284 { /* src xmm */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 17285 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17240 17286 /*mxcsr:in */ 0, 17241 17287 /*128:out */ X86_MXCSR_IE, … … 17383 17429 */ 17384 17430 /*26*/{ { /* unused */ { FP32_ROW_UNUSED } }, 17385 { /* src xmm */ { FP32_NORM_MAX(0), 17386 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17431 { /* src xmm */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 17432 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17387 17433 /*mxcsr:in */ 0, 17388 17434 /*128:out */ X86_MXCSR_IE, 17389 17435 /*256:out */ -1 }, 17390 17436 { { /* unused */ { FP32_ROW_UNUSED } }, 17391 { /* src xmm */ { FP32_NORM_MAX(1), 17392 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17437 { /* src xmm */ { FP32_NORM_MAX(1), FP32_RAND_x7_V2 } }, 17438 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17393 17439 /*mxcsr:in */ 0, 17394 17440 /*128:out */ X86_MXCSR_IE, … … 17398 17444 */ 17399 17445 /*28*/{ { /* unused */ { FP32_ROW_UNUSED } }, 17400 { /* src xmm */ { FP32_QNAN(0), 17401 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17446 { /* src xmm */ { FP32_QNAN(0), FP32_RAND_x7_V2 } }, 17447 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17402 17448 /*mxcsr:in */ 0, 17403 17449 /*128:out */ X86_MXCSR_IE, 17404 17450 /*256:out */ -1 }, 17405 17451 { { /* unused */ { FP32_ROW_UNUSED } }, 17406 { /* src xmm */ { FP32_SNAN(1), 17407 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17452 { /* src xmm */ { FP32_SNAN(1), FP32_RAND_x7_V2 } }, 17453 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17408 17454 /*mxcsr:in */ 0, 17409 17455 /*128:out */ X86_MXCSR_IE, … … 17493 17539 * Infinity. 17494 17540 */ 17495 /* 2*/{ { /* clr r64 */ { FP32_INT64_C(0), 17496 { /* src xmm */ { FP32_INF(1), 17497 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17541 /* 2*/{ { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17542 { /* src xmm */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 17543 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17498 17544 /*mxcsr:in */ 0, 17499 17545 /*128:out */ X86_MXCSR_IE, 17500 17546 /*256:out */ -1 }, 17501 { { /* clr r64 */ { FP32_INT64_C(0), 17502 { /* src xmm */ { FP32_INF(0), 17503 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17547 { { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17548 { /* src xmm */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 17549 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17504 17550 /*mxcsr:in */ 0, 17505 17551 /*128:out */ X86_MXCSR_IE, … … 17622 17668 * Overflow (Underflow not possible). 17623 17669 */ 17624 /*22*/{ { /* clr r64 */ { FP32_INT64_C(0), 17625 { /* src xmm */ { FP32_NORM_MAX(0), 17626 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17670 /*22*/{ { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17671 { /* src xmm */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 17672 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17627 17673 /*mxcsr:in */ 0, 17628 17674 /*128:out */ X86_MXCSR_IE, 17629 17675 /*256:out */ -1 }, 17630 { { /* clr r64 */ { FP32_INT64_C(0), 17631 { /* src xmm */ { FP32_NORM_MAX(1), 17632 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17676 { { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17677 { /* src xmm */ { FP32_NORM_MAX(1), FP32_RAND_x7_V2 } }, 17678 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17633 17679 /*mxcsr:in */ 0, 17634 17680 /*128:out */ X86_MXCSR_IE, … … 17637 17683 * Invalids. 17638 17684 */ 17639 /*24*/{ { /* clr r64 */ { FP32_INT64_C(0), 17640 { /* src xmm */ { FP32_QNAN(0), 17641 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17685 /*24*/{ { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17686 { /* src xmm */ { FP32_QNAN(0), FP32_RAND_x7_V2 } }, 17687 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17642 17688 /*mxcsr:in */ 0, 17643 17689 /*128:out */ X86_MXCSR_IE, 17644 17690 /*256:out */ -1 }, 17645 { { /* clr r64 */ { FP32_INT64_C(0), 17646 { /* src xmm */ { FP32_SNAN(1), 17647 { /* => r32 */ { FP32_INT_INDEF INITE,FP32_x7_UNUSED } },17691 { { /* clr r64 */ { FP32_INT64_C(0), FP32_x6_UNUSED } }, 17692 { /* src xmm */ { FP32_SNAN(1), FP32_RAND_x7_V2 } }, 17693 { /* => r32 */ { FP32_INT_INDEF, FP32_x7_UNUSED } }, 17648 17694 /*mxcsr:in */ 0, 17649 17695 /*128:out */ X86_MXCSR_IE, … … 17671 17717 */ 17672 17718 /* 2*/{ { /* unused */ { FP32_ROW_UNUSED } }, 17673 { /* src xmm */ { FP32_INF(1), 17674 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17719 { /* src xmm */ { FP32_INF(1), FP32_RAND_x7_V1 } }, 17720 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17675 17721 /*mxcsr:in */ 0, 17676 17722 /*128:out */ X86_MXCSR_IE, 17677 17723 /*256:out */ -1 }, 17678 17724 { { /* unused */ { FP32_ROW_UNUSED } }, 17679 { /* src xmm */ { FP32_INF(0), 17680 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17725 { /* src xmm */ { FP32_INF(0), FP32_RAND_x7_V1 } }, 17726 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17681 17727 /*mxcsr:in */ 0, 17682 17728 /*128:out */ X86_MXCSR_IE, … … 17824 17870 */ 17825 17871 /*26*/{ { /* unused */ { FP32_ROW_UNUSED } }, 17826 { /* src xmm */ { FP32_NORM_MAX(0), 17827 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17872 { /* src xmm */ { FP32_NORM_MAX(0), FP32_RAND_x7_V2 } }, 17873 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17828 17874 /*mxcsr:in */ 0, 17829 17875 /*128:out */ X86_MXCSR_IE, 17830 17876 /*256:out */ -1 }, 17831 17877 { { /* unused */ { FP32_ROW_UNUSED } }, 17832 { /* src xmm */ { FP32_NORM_MAX(1), 17833 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17878 { /* src xmm */ { FP32_NORM_MAX(1), FP32_RAND_x7_V2 } }, 17879 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17834 17880 /*mxcsr:in */ 0, 17835 17881 /*128:out */ X86_MXCSR_IE, … … 17839 17885 */ 17840 17886 /*28*/{ { /* unused */ { FP32_ROW_UNUSED } }, 17841 { /* src xmm */ { FP32_QNAN(0), 17842 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17887 { /* src xmm */ { FP32_QNAN(0), FP32_RAND_x7_V2 } }, 17888 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17843 17889 /*mxcsr:in */ 0, 17844 17890 /*128:out */ X86_MXCSR_IE, 17845 17891 /*256:out */ -1 }, 17846 17892 { { /* unused */ { FP32_ROW_UNUSED } }, 17847 { /* src xmm */ { FP32_SNAN(1), 17848 { /* => r64 */ { FP32_INT64_INDEF INITE, FP32_x6_UNUSED } },17893 { /* src xmm */ { FP32_SNAN(1), FP32_RAND_x7_V2 } }, 17894 { /* => r64 */ { FP32_INT64_INDEF, FP32_x6_UNUSED } }, 17849 17895 /*mxcsr:in */ 0, 17850 17896 /*128:out */ X86_MXCSR_IE, … … 17919 17965 * Zero. 17920 17966 */ 17921 /* 0*/{ { /* unused */ { FP64_ROW_UNUSED 17922 { /* src mm */ { FP64_INT32_C(0, 17923 { /* => xmm */ { FP64_0(0), 17967 /* 0*/{ { /* unused */ { FP64_ROW_UNUSED } }, 17968 { /* src mm */ { FP64_INT32_C(0, 0) } }, 17969 { /* => xmm */ { FP64_0(0), FP64_0(0) } }, 17924 17970 /*mxcsr:in */ 0, 17925 17971 /*128:out */ 0, … … 17977 18023 /*128:out */ X86_MXCSR_RC_ZERO, 17978 18024 /*256:out */ -1 }, 17979 }; 18025 /* 18026 * Not invalid, but unusual: Intel define the 'indefinite integer' as 10000...0b 18027 */ 18028 /* 9*/{ { /* unused */ { FP64_ROW_UNUSED } }, 18029 { /* src mm */ { FP64_INT32_INDEF( -47) } }, 18030 { /* => xmm */ { FP64_V(1,0x0,0x41e), FP64_V(1,0x7800000000000,0x404) } }, 18031 /*mxcsr:in */ 0, 18032 /*128:out */ 0, 18033 /*256:out */ -1 }, 17980 18034 /* 17981 18035 * Precision, Infinity, Overflow, Underflow, Denormal, Invalid not possible. 17982 18036 */ 18037 }; 17983 18038 17984 18039 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 17985 18040 { 17986 { bs3CpuInstr4_cvtpi2pd_XMM1_MM1_icebp_c16, 255, RM_REG, T_SSE , XMM1, MM1, NOREG, PASS_s_aValues },17987 { bs3CpuInstr4_cvtpi2pd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE , XMM1, FSxBX, NOREG, PASS_s_aValues },18041 { bs3CpuInstr4_cvtpi2pd_XMM1_MM1_icebp_c16, 255, RM_REG, T_SSE2, XMM1, MM1, NOREG, PASS_s_aValues }, 18042 { bs3CpuInstr4_cvtpi2pd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 17988 18043 }; 17989 18044 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 17990 18045 { 17991 { bs3CpuInstr4_cvtpi2pd_XMM1_MM1_icebp_c32, 255, RM_REG, T_SSE , XMM1, MM1, NOREG, PASS_s_aValues },17992 { bs3CpuInstr4_cvtpi2pd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE , XMM1, FSxBX, NOREG, PASS_s_aValues },18046 { bs3CpuInstr4_cvtpi2pd_XMM1_MM1_icebp_c32, 255, RM_REG, T_SSE2, XMM1, MM1, NOREG, PASS_s_aValues }, 18047 { bs3CpuInstr4_cvtpi2pd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 17993 18048 }; 17994 18049 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 17995 18050 { 17996 { bs3CpuInstr4_cvtpi2pd_XMM1_MM1_icebp_c64, 255, RM_REG, T_SSE , XMM1, MM1, NOREG, PASS_s_aValues },17997 { bs3CpuInstr4_cvtpi2pd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE , XMM1, FSxBX, NOREG, PASS_s_aValues },17998 { bs3CpuInstr4_cvtpi2pd_XMM8_MM1_icebp_c64, 255, RM_REG, T_SSE , XMM8, MM1, NOREG, PASS_s_aValues },17999 { bs3CpuInstr4_cvtpi2pd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE , XMM8, FSxBX, NOREG, PASS_s_aValues },18051 { bs3CpuInstr4_cvtpi2pd_XMM1_MM1_icebp_c64, 255, RM_REG, T_SSE2, XMM1, MM1, NOREG, PASS_s_aValues }, 18052 { bs3CpuInstr4_cvtpi2pd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 18053 { bs3CpuInstr4_cvtpi2pd_XMM8_MM1_icebp_c64, 255, RM_REG, T_SSE2, XMM8, MM1, NOREG, PASS_s_aValues }, 18054 { bs3CpuInstr4_cvtpi2pd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, XMM8, FSxBX, NOREG, PASS_s_aValues }, 18000 18055 }; 18001 18056 … … 18027 18082 */ 18028 18083 /* 1*/{ { /* unused */ { FP64_ROW_UNUSED } }, 18029 { /* src xmm */ { FP64_INF(1), FP64_INF(0)} },18030 { /* => mm */ { FP64_INT32 (INT32_INDEFINITE_C, INT32_INDEFINITE_C)} },18084 { /* src xmm */ { FP64_INF(1), FP64_INF(0) } }, 18085 { /* => mm */ { FP64_INT32_INDEFx2 } }, 18031 18086 /*mxcsr:in */ 0, 18032 18087 /*128:out */ X86_MXCSR_IE, … … 18095 18150 */ 18096 18151 /*10*/{ { /* unused */ { FP64_ROW_UNUSED } }, 18097 { /* src xmm */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1)} },18098 { /* => mm */ { FP64_INT32 (INT32_INDEFINITE_C, INT32_INDEFINITE_C)} },18152 { /* src xmm */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 18153 { /* => mm */ { FP64_INT32_INDEFx2 } }, 18099 18154 /*mxcsr:in */ 0, 18100 18155 /*128:out */ X86_MXCSR_IE, 18101 18156 /*256:out */ -1 }, 18102 18157 { { /* unused */ { FP64_ROW_UNUSED } }, 18103 { /* src xmm */ { FP64_NORM_SAFE_INT_MAX(1), 18104 { /* => mm */ { FP64_INT32(INT32_INDEF INITE_C, INT32_INDEFINITE_C)} },18158 { /* src xmm */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, 18159 { /* => mm */ { FP64_INT32(INT32_INDEF_C, INT32_INDEF_C) } }, 18105 18160 /*mxcsr:in */ 0, 18106 18161 /*128:out */ X86_MXCSR_IE, … … 18110 18165 */ 18111 18166 /*12*/{ { /* unused */ { FP64_ROW_UNUSED } }, 18112 { /* src xmm */ { FP64_QNAN(0), FP64_QNAN(1)} },18113 { /* => mm */ { FP64_INT32 (INT32_INDEFINITE_C, INT32_INDEFINITE_C)} },18167 { /* src xmm */ { FP64_QNAN(0), FP64_QNAN(1) } }, 18168 { /* => mm */ { FP64_INT32_INDEFx2 } }, 18114 18169 /*mxcsr:in */ 0, 18115 18170 /*128:out */ X86_MXCSR_IE, 18116 18171 /*256:out */ -1 }, 18117 18172 { { /* unused */ { FP64_ROW_UNUSED } }, 18118 { /* src xmm */ { FP64_SNAN(1), FP64_SNAN(0)} },18119 { /* => mm */ { FP64_INT32 (INT32_INDEFINITE_C, INT32_INDEFINITE_C)} },18173 { /* src xmm */ { FP64_SNAN(1), FP64_SNAN(0) } }, 18174 { /* => mm */ { FP64_INT32_INDEFx2 } }, 18120 18175 /*mxcsr:in */ 0, 18121 18176 /*128:out */ X86_MXCSR_IE, … … 18125 18180 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 18126 18181 { 18127 { bs3CpuInstr4_cvtpd2pi_MM1_XMM1_icebp_c16, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },18128 { bs3CpuInstr4_cvtpd2pi_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },18182 { bs3CpuInstr4_cvtpd2pi_MM1_XMM1_icebp_c16, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 18183 { bs3CpuInstr4_cvtpd2pi_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 18129 18184 }; 18130 18185 18131 18186 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 18132 18187 { 18133 { bs3CpuInstr4_cvtpd2pi_MM1_XMM1_icebp_c32, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },18134 { bs3CpuInstr4_cvtpd2pi_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },18188 { bs3CpuInstr4_cvtpd2pi_MM1_XMM1_icebp_c32, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 18189 { bs3CpuInstr4_cvtpd2pi_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 18135 18190 }; 18136 18191 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 18137 18192 { 18138 { bs3CpuInstr4_cvtpd2pi_MM1_XMM1_icebp_c64, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },18139 { bs3CpuInstr4_cvtpd2pi_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },18140 { bs3CpuInstr4_cvtpd2pi_MM1_XMM8_icebp_c64, 255, RM_REG, T_SSE , MM1, XMM8, NOREG, PASS_s_aValues },18193 { bs3CpuInstr4_cvtpd2pi_MM1_XMM1_icebp_c64, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 18194 { bs3CpuInstr4_cvtpd2pi_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 18195 { bs3CpuInstr4_cvtpd2pi_MM1_XMM8_icebp_c64, 255, RM_REG, T_SSE2, MM1, XMM8, NOREG, PASS_s_aValues }, 18141 18196 }; 18142 18197 … … 18168 18223 */ 18169 18224 /* 1*/{ { /* unused */ { FP64_ROW_UNUSED } }, 18170 { /* src xmm */ { FP64_INF(1), FP64_INF(0)} },18171 { /* => mm */ { FP64_INT32 (INT32_INDEFINITE_C, INT32_INDEFINITE_C)} },18225 { /* src xmm */ { FP64_INF(1), FP64_INF(0) } }, 18226 { /* => mm */ { FP64_INT32_INDEFx2 } }, 18172 18227 /*mxcsr:in */ 0, 18173 18228 /*128:out */ X86_MXCSR_IE, … … 18236 18291 */ 18237 18292 /*10*/{ { /* unused */ { FP64_ROW_UNUSED } }, 18238 { /* src xmm */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1)} },18239 { /* => mm */ { FP64_INT32 (INT32_INDEFINITE_C, INT32_INDEFINITE_C)} },18293 { /* src xmm */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 18294 { /* => mm */ { FP64_INT32_INDEFx2 } }, 18240 18295 /*mxcsr:in */ 0, 18241 18296 /*128:out */ X86_MXCSR_IE, 18242 18297 /*256:out */ -1 }, 18243 18298 { { /* unused */ { FP64_ROW_UNUSED } }, 18244 { /* src xmm */ { FP64_NORM_SAFE_INT_MAX(1), 18245 { /* => mm */ { FP64_INT32(INT32_INDEF INITE_C, INT32_INDEFINITE_C)} },18299 { /* src xmm */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, 18300 { /* => mm */ { FP64_INT32(INT32_INDEF_C, INT32_INDEF_C) } }, 18246 18301 /*mxcsr:in */ 0, 18247 18302 /*128:out */ X86_MXCSR_IE, … … 18251 18306 */ 18252 18307 /*12*/{ { /* unused */ { FP64_ROW_UNUSED } }, 18253 { /* src xmm */ { FP64_QNAN(0), FP64_QNAN(1)} },18254 { /* => mm */ { FP64_INT32 (INT32_INDEFINITE_C, INT32_INDEFINITE_C)} },18308 { /* src xmm */ { FP64_QNAN(0), FP64_QNAN(1) } }, 18309 { /* => mm */ { FP64_INT32_INDEFx2 } }, 18255 18310 /*mxcsr:in */ 0, 18256 18311 /*128:out */ X86_MXCSR_IE, 18257 18312 /*256:out */ -1 }, 18258 18313 { { /* unused */ { FP64_ROW_UNUSED } }, 18259 { /* src xmm */ { FP64_SNAN(1), FP64_SNAN(0)} },18260 { /* => mm */ { FP64_INT32 (INT32_INDEFINITE_C, INT32_INDEFINITE_C)} },18314 { /* src xmm */ { FP64_SNAN(1), FP64_SNAN(0) } }, 18315 { /* => mm */ { FP64_INT32_INDEFx2 } }, 18261 18316 /*mxcsr:in */ 0, 18262 18317 /*128:out */ X86_MXCSR_IE, … … 18266 18321 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 18267 18322 { 18268 { bs3CpuInstr4_cvttpd2pi_MM1_XMM1_icebp_c16, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },18269 { bs3CpuInstr4_cvttpd2pi_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },18323 { bs3CpuInstr4_cvttpd2pi_MM1_XMM1_icebp_c16, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 18324 { bs3CpuInstr4_cvttpd2pi_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 18270 18325 }; 18271 18326 18272 18327 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 18273 18328 { 18274 { bs3CpuInstr4_cvttpd2pi_MM1_XMM1_icebp_c32, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },18275 { bs3CpuInstr4_cvttpd2pi_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },18329 { bs3CpuInstr4_cvttpd2pi_MM1_XMM1_icebp_c32, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 18330 { bs3CpuInstr4_cvttpd2pi_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 18276 18331 }; 18277 18332 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 18278 18333 { 18279 { bs3CpuInstr4_cvttpd2pi_MM1_XMM1_icebp_c64, 255, RM_REG, T_SSE , MM1, XMM1, NOREG, PASS_s_aValues },18280 { bs3CpuInstr4_cvttpd2pi_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE , MM1, FSxBX, NOREG, PASS_s_aValues },18281 { bs3CpuInstr4_cvttpd2pi_MM1_XMM8_icebp_c64, 255, RM_REG, T_SSE , MM1, XMM8, NOREG, PASS_s_aValues },18334 { bs3CpuInstr4_cvttpd2pi_MM1_XMM1_icebp_c64, 255, RM_REG, T_SSE2, MM1, XMM1, NOREG, PASS_s_aValues }, 18335 { bs3CpuInstr4_cvttpd2pi_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, MM1, FSxBX, NOREG, PASS_s_aValues }, 18336 { bs3CpuInstr4_cvttpd2pi_MM1_XMM8_icebp_c64, 255, RM_REG, T_SSE2, MM1, XMM8, NOREG, PASS_s_aValues }, 18282 18337 }; 18283 18338 … … 18389 18444 /*128:out */ X86_MXCSR_RC_ZERO, 18390 18445 /*256:out */ -1 }, 18446 /* 18447 * Not invalid, but unusual: Intel define the 'indefinite integer' as 10000...0b 18448 */ 18449 /*13*/{ { /* src r32 */ { FP64_INT32_INDEF(0) } }, 18450 { /* src xmm */ { FP64_2(1), FP64_RAND_x3_V2 } }, 18451 { /* => xmm */ { FP64_V(1,0x0,0x41e), FP64_RAND_x3_V2 } }, 18452 /*mxcsr:in */ 0, 18453 /*128:out */ 0, 18454 /*256:out */ -1 }, 18391 18455 }; 18392 18456 … … 18503 18567 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 18504 18568 { 18505 { bs3CpuInstr4_cvtsi2sd_XMM1_EAX_icebp_c16, 255, RM_REG, T_SSE ,XMM1, XMM1, EAX, PASS_s_aValues32 },18506 { bs3CpuInstr4_cvtsi2sd_XMM1_FSxBX_D_icebp_c16, 255, RM_MEM, T_SSE ,XMM1, XMM1, FSxBX, PASS_s_aValues32 },18569 { bs3CpuInstr4_cvtsi2sd_XMM1_EAX_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM1, EAX, PASS_s_aValues32 }, 18570 { bs3CpuInstr4_cvtsi2sd_XMM1_FSxBX_D_icebp_c16, 255, RM_MEM, T_SSE2, XMM1, XMM1, FSxBX, PASS_s_aValues32 }, 18507 18571 18508 18572 { bs3CpuInstr4_vcvtsi2sd_XMM1_XMM2_EAX_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, EAX, PASS_s_aValues32 }, … … 18520 18584 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 18521 18585 { 18522 { bs3CpuInstr4_cvtsi2sd_XMM1_EAX_icebp_c32, 255, RM_REG, T_SSE ,XMM1, XMM1, EAX, PASS_s_aValues32 },18523 { bs3CpuInstr4_cvtsi2sd_XMM1_FSxBX_D_icebp_c32, 255, RM_MEM, T_SSE ,XMM1, XMM1, FSxBX, PASS_s_aValues32 },18586 { bs3CpuInstr4_cvtsi2sd_XMM1_EAX_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM1, EAX, PASS_s_aValues32 }, 18587 { bs3CpuInstr4_cvtsi2sd_XMM1_FSxBX_D_icebp_c32, 255, RM_MEM, T_SSE2, XMM1, XMM1, FSxBX, PASS_s_aValues32 }, 18524 18588 18525 18589 { bs3CpuInstr4_vcvtsi2sd_XMM1_XMM2_EAX_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, EAX, PASS_s_aValues32 }, … … 18536 18600 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 18537 18601 { 18538 { bs3CpuInstr4_cvtsi2sd_XMM1_EAX_icebp_c64, 255, RM_REG, T_SSE ,XMM1, XMM1, EAX, PASS_s_aValues32 },18539 { bs3CpuInstr4_cvtsi2sd_XMM1_FSxBX_D_icebp_c64, 255, RM_MEM, T_SSE ,XMM1, XMM1, FSxBX, PASS_s_aValues32 },18540 { bs3CpuInstr4_cvtsi2sd_XMM8_R8D_icebp_c64, 255, RM_REG, T_SSE ,XMM8, XMM8, R8D, PASS_s_aValues32 },18541 { bs3CpuInstr4_cvtsi2sd_XMM8_FSxBX_D_icebp_c64, 255, RM_MEM, T_SSE ,XMM8, XMM8, FSxBX, PASS_s_aValues32 },18542 18543 { bs3CpuInstr4_cvtsi2sd_XMM1_RAX_icebp_c64, 255, RM_REG, T_SSE ,XMM1, XMM1, RAX, PASS_s_aValues64 },18544 { bs3CpuInstr4_cvtsi2sd_XMM1_FSxBX_Q_icebp_c64, 255, RM_MEM, T_SSE ,XMM1, XMM1, FSxBX, PASS_s_aValues64 },18545 { bs3CpuInstr4_cvtsi2sd_XMM8_R8_icebp_c64, 255, RM_REG, T_SSE ,XMM8, XMM8, R8, PASS_s_aValues64 },18546 { bs3CpuInstr4_cvtsi2sd_XMM8_FSxBX_Q_icebp_c64, 255, RM_MEM, T_SSE ,XMM8, XMM8, FSxBX, PASS_s_aValues64 },18602 { bs3CpuInstr4_cvtsi2sd_XMM1_EAX_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM1, EAX, PASS_s_aValues32 }, 18603 { bs3CpuInstr4_cvtsi2sd_XMM1_FSxBX_D_icebp_c64, 255, RM_MEM, T_SSE2, XMM1, XMM1, FSxBX, PASS_s_aValues32 }, 18604 { bs3CpuInstr4_cvtsi2sd_XMM8_R8D_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM8, R8D, PASS_s_aValues32 }, 18605 { bs3CpuInstr4_cvtsi2sd_XMM8_FSxBX_D_icebp_c64, 255, RM_MEM, T_SSE2, XMM8, XMM8, FSxBX, PASS_s_aValues32 }, 18606 18607 { bs3CpuInstr4_cvtsi2sd_XMM1_RAX_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM1, RAX, PASS_s_aValues64 }, 18608 { bs3CpuInstr4_cvtsi2sd_XMM1_FSxBX_Q_icebp_c64, 255, RM_MEM, T_SSE2, XMM1, XMM1, FSxBX, PASS_s_aValues64 }, 18609 { bs3CpuInstr4_cvtsi2sd_XMM8_R8_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM8, R8, PASS_s_aValues64 }, 18610 { bs3CpuInstr4_cvtsi2sd_XMM8_FSxBX_Q_icebp_c64, 255, RM_MEM, T_SSE2, XMM8, XMM8, FSxBX, PASS_s_aValues64 }, 18547 18611 18548 18612 { bs3CpuInstr4_vcvtsi2sd_XMM1_XMM2_EAX_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, EAX, PASS_s_aValues32 }, … … 18600 18664 */ 18601 18665 /* 2*/{ { /* clr r64 */ { FP64_INT_C(0) } }, 18602 { /* src xmm */ { FP64_INF(1), 18603 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },18666 { /* src xmm */ { FP64_INF(1), FP64_RAND_x3_V1 } }, 18667 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 18604 18668 /*mxcsr:in */ 0, 18605 18669 /*128:out */ X86_MXCSR_IE, 18606 18670 /*256:out */ -1 }, 18607 18671 { { /* clr r64 */ { FP64_INT_C(0) } }, 18608 { /* src xmm */ { FP64_INF(0), 18609 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },18672 { /* src xmm */ { FP64_INF(0), FP64_RAND_x3_V1 } }, 18673 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 18610 18674 /*mxcsr:in */ 0, 18611 18675 /*128:out */ X86_MXCSR_IE, … … 18718 18782 /*20*/{ { /* clr r64 */ { FP64_INT_C(0) } }, 18719 18783 { /* src xmm */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_x3_V2 } }, 18720 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },18784 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 18721 18785 /*mxcsr:in */ 0, 18722 18786 /*128:out */ X86_MXCSR_IE, … … 18724 18788 { { /* clr r64 */ { FP64_INT_C(0) } }, 18725 18789 { /* src xmm */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_x3_V2 } }, 18726 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },18790 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 18727 18791 /*mxcsr:in */ 0, 18728 18792 /*128:out */ X86_MXCSR_IE, 18729 18793 /*256:out */ -1 }, 18730 18794 { { /* clr r64 */ { FP64_INT_C(0) } }, 18731 { /* src xmm */ { FP64_NORM_MAX(0), 18732 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },18795 { /* src xmm */ { FP64_NORM_MAX(0), FP64_RAND_x3_V2 } }, 18796 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 18733 18797 /*mxcsr:in */ 0, 18734 18798 /*128:out */ X86_MXCSR_IE, 18735 18799 /*256:out */ -1 }, 18736 18800 { { /* clr r64 */ { FP64_INT_C(0) } }, 18737 { /* src xmm */ { FP64_NORM_MAX(1), 18738 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },18801 { /* src xmm */ { FP64_NORM_MAX(1), FP64_RAND_x3_V2 } }, 18802 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 18739 18803 /*mxcsr:in */ 0, 18740 18804 /*128:out */ X86_MXCSR_IE, … … 18744 18808 */ 18745 18809 /*24*/{ { /* clr r64 */ { FP64_INT_C(0) } }, 18746 { /* src xmm */ { FP64_QNAN(0), 18747 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },18810 { /* src xmm */ { FP64_QNAN(0), FP64_RAND_x3_V2 } }, 18811 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 18748 18812 /*mxcsr:in */ 0, 18749 18813 /*128:out */ X86_MXCSR_IE, 18750 18814 /*256:out */ -1 }, 18751 18815 { { /* clr r64 */ { FP64_INT_C(0) } }, 18752 { /* src xmm */ { FP64_SNAN(1), 18753 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },18816 { /* src xmm */ { FP64_SNAN(1), FP64_RAND_x3_V2 } }, 18817 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 18754 18818 /*mxcsr:in */ 0, 18755 18819 /*128:out */ X86_MXCSR_IE, … … 18762 18826 */ 18763 18827 /* 0*/{ { /* unused */ { FP64_ROW_UNUSED } }, 18764 { /* src xmm */ { FP64_0(0) } },18765 { /* => r64 */ { FP64_INT_C(0) } },18828 { /* src xmm */ { FP64_0(0) } }, 18829 { /* => r64 */ { FP64_INT_C(0) } }, 18766 18830 /*mxcsr:in */ 0, 18767 18831 /*128:out */ 0, 18768 18832 /*256:out */ -1 }, 18769 18833 { { /* unused */ { FP64_ROW_UNUSED } }, 18770 { /* src xmm */ { FP64_0(1) } },18771 { /* => r64 */ { FP64_INT_C(0) } },18834 { /* src xmm */ { FP64_0(1) } }, 18835 { /* => r64 */ { FP64_INT_C(0) } }, 18772 18836 /*mxcsr:in */ 0, 18773 18837 /*128:out */ 0, … … 18777 18841 */ 18778 18842 /* 2*/{ { /* unused */ { FP64_ROW_UNUSED } }, 18779 { /* src xmm */ { FP64_INF(1) } },18780 { /* => r64 */ { FP64_INT_INDEF INITE} },18843 { /* src xmm */ { FP64_INF(1) } }, 18844 { /* => r64 */ { FP64_INT_INDEF } }, 18781 18845 /*mxcsr:in */ 0, 18782 18846 /*128:out */ X86_MXCSR_IE, 18783 18847 /*256:out */ -1 }, 18784 18848 { { /* unused */ { FP64_ROW_UNUSED } }, 18785 { /* src xmm */ { FP64_INF(0) } },18786 { /* => r64 */ { FP64_INT_INDEF INITE} },18849 { /* src xmm */ { FP64_INF(0) } }, 18850 { /* => r64 */ { FP64_INT_INDEF } }, 18787 18851 /*mxcsr:in */ 0, 18788 18852 /*128:out */ X86_MXCSR_IE, … … 18929 18993 * Overflow (Underflow not possible). 18930 18994 */ 18931 /*26*/{ { /* unused */ { FP64_ROW_UNUSED } },18995 /*26*/{ { /* unused */ { FP64_ROW_UNUSED } }, 18932 18996 { /* src xmm */ { FP64_NORM_MAX(0) } }, 18933 { /* => r64 */ { FP64_INT_INDEF INITE} },18997 { /* => r64 */ { FP64_INT_INDEF } }, 18934 18998 /*mxcsr:in */ 0, 18935 18999 /*128:out */ X86_MXCSR_IE, 18936 19000 /*256:out */ -1 }, 19001 { { /* unused */ { FP64_ROW_UNUSED } }, 19002 { /* src xmm */ { FP64_NORM_MAX(1) } }, 19003 { /* => r64 */ { FP64_INT_INDEF } }, 19004 /*mxcsr:in */ 0, 19005 /*128:out */ X86_MXCSR_IE, 19006 /*256:out */ -1 }, 19007 /* 19008 * Invalids. 19009 */ 19010 /*28*/{ { /* unused */ { FP64_ROW_UNUSED } }, 19011 { /* src xmm */ { FP64_QNAN(0) } }, 19012 { /* => r64 */ { FP64_INT_INDEF } }, 19013 /*mxcsr:in */ 0, 19014 /*128:out */ X86_MXCSR_IE, 19015 /*256:out */ -1 }, 18937 19016 { { /* unused */ { FP64_ROW_UNUSED } }, 18938 { /* src xmm */ { FP64_ NORM_MAX(1)} },18939 { /* => r64 */ { FP64_INT_INDEF INITE} },19017 { /* src xmm */ { FP64_SNAN(1) } }, 19018 { /* => r64 */ { FP64_INT_INDEF } }, 18940 19019 /*mxcsr:in */ 0, 18941 19020 /*128:out */ X86_MXCSR_IE, 18942 19021 /*256:out */ -1 }, 18943 /*18944 * Invalids.18945 */18946 /*28*/{ { /* unused */ { FP64_ROW_UNUSED } },18947 { /* src xmm */ { FP64_QNAN(0) } },18948 { /* => r64 */ { FP64_INT_INDEFINITE } },18949 /*mxcsr:in */ 0,18950 /*128:out */ X86_MXCSR_IE,18951 /*256:out */ -1 },18952 { { /* unused */ { FP64_ROW_UNUSED } },18953 { /* src xmm */ { FP64_SNAN(1) } },18954 { /* => r64 */ { FP64_INT_INDEFINITE } },18955 /*mxcsr:in */ 0,18956 /*128:out */ X86_MXCSR_IE,18957 /*256:out */ -1 },18958 19022 }; 18959 19023 18960 19024 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 18961 19025 { 18962 { bs3CpuInstr4_cvtsd2si_EAX_XMM1_icebp_c16, 255, RM_REG, T_SSE ,EAX, XMM1, NOREG, PASS_s_aValues32 },18963 { bs3CpuInstr4_cvtsd2si_EAX_FSxBX_icebp_c16, 255, RM_MEM, T_SSE ,EAX, FSxBX, NOREG, PASS_s_aValues32 },19026 { bs3CpuInstr4_cvtsd2si_EAX_XMM1_icebp_c16, 255, RM_REG, T_SSE2, EAX, XMM1, NOREG, PASS_s_aValues32 }, 19027 { bs3CpuInstr4_cvtsd2si_EAX_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, EAX, FSxBX, NOREG, PASS_s_aValues32 }, 18964 19028 18965 19029 { bs3CpuInstr4_vcvtsd2si_EAX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, EAX, XMM1, NOREG, PASS_s_aValues32 }, … … 18972 19036 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 18973 19037 { 18974 { bs3CpuInstr4_cvtsd2si_EAX_XMM1_icebp_c32, 255, RM_REG, T_SSE ,EAX, XMM1, NOREG, PASS_s_aValues32 },18975 { bs3CpuInstr4_cvtsd2si_EAX_FSxBX_icebp_c32, 255, RM_MEM, T_SSE ,EAX, FSxBX, NOREG, PASS_s_aValues32 },19038 { bs3CpuInstr4_cvtsd2si_EAX_XMM1_icebp_c32, 255, RM_REG, T_SSE2, EAX, XMM1, NOREG, PASS_s_aValues32 }, 19039 { bs3CpuInstr4_cvtsd2si_EAX_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, EAX, FSxBX, NOREG, PASS_s_aValues32 }, 18976 19040 18977 19041 { bs3CpuInstr4_vcvtsd2si_EAX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, EAX, XMM1, NOREG, PASS_s_aValues32 }, … … 18983 19047 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 18984 19048 { 18985 { bs3CpuInstr4_cvtsd2si_EAX_XMM1_icebp_c64, 255, RM_REG, T_SSE ,EAX, XMM1, RAX, PASS_s_aValues32 },18986 { bs3CpuInstr4_cvtsd2si_EAX_FSxBX_icebp_c64, 255, RM_MEM, T_SSE ,EAX, FSxBX, RAX, PASS_s_aValues32 },18987 18988 { bs3CpuInstr4_cvtsd2si_R8D_XMM8_icebp_c64, 255, RM_REG, T_SSE ,R8D, XMM8, R8, PASS_s_aValues32 },18989 { bs3CpuInstr4_cvtsd2si_R8D_FSxBX_icebp_c64, 255, RM_MEM, T_SSE ,R8D, FSxBX, R8, PASS_s_aValues32 },19049 { bs3CpuInstr4_cvtsd2si_EAX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, EAX, XMM1, RAX, PASS_s_aValues32 }, 19050 { bs3CpuInstr4_cvtsd2si_EAX_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, EAX, FSxBX, RAX, PASS_s_aValues32 }, 19051 19052 { bs3CpuInstr4_cvtsd2si_R8D_XMM8_icebp_c64, 255, RM_REG, T_SSE2, R8D, XMM8, R8, PASS_s_aValues32 }, 19053 { bs3CpuInstr4_cvtsd2si_R8D_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, R8D, FSxBX, R8, PASS_s_aValues32 }, 18990 19054 18991 19055 { bs3CpuInstr4_vcvtsd2si_EAX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, EAX, XMM1, RAX, PASS_s_aValues32 }, … … 18995 19059 { bs3CpuInstr4_vcvtsd2si_R8D_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, R8D, FSxBX, R8, PASS_s_aValues32 }, 18996 19060 18997 { bs3CpuInstr4_cvtsd2si_RAX_XMM1_icebp_c64, 255, RM_REG, T_SSE ,RAX, XMM1, NOREG, PASS_s_aValues64 },18998 { bs3CpuInstr4_cvtsd2si_RAX_FSxBX_icebp_c64, 255, RM_MEM, T_SSE ,RAX, FSxBX, NOREG, PASS_s_aValues64 },18999 19000 { bs3CpuInstr4_cvtsd2si_R8_XMM8_icebp_c64, 255, RM_REG, T_SSE ,R8, XMM8, NOREG, PASS_s_aValues64 },19001 { bs3CpuInstr4_cvtsd2si_R8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE ,R8, FSxBX, NOREG, PASS_s_aValues64 },19061 { bs3CpuInstr4_cvtsd2si_RAX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, RAX, XMM1, NOREG, PASS_s_aValues64 }, 19062 { bs3CpuInstr4_cvtsd2si_RAX_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, RAX, FSxBX, NOREG, PASS_s_aValues64 }, 19063 19064 { bs3CpuInstr4_cvtsd2si_R8_XMM8_icebp_c64, 255, RM_REG, T_SSE2, R8, XMM8, NOREG, PASS_s_aValues64 }, 19065 { bs3CpuInstr4_cvtsd2si_R8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, R8, FSxBX, NOREG, PASS_s_aValues64 }, 19002 19066 19003 19067 { bs3CpuInstr4_vcvtsd2si_RAX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, RAX, XMM1, NOREG, PASS_s_aValues64 }, … … 19041 19105 */ 19042 19106 /* 2*/{ { /* clr r64 */ { FP64_INT_C(0) } }, 19043 { /* src xmm */ { FP64_INF(1), 19044 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },19107 { /* src xmm */ { FP64_INF(1), FP64_RAND_x3_V1 } }, 19108 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 19045 19109 /*mxcsr:in */ 0, 19046 19110 /*128:out */ X86_MXCSR_IE, 19047 19111 /*256:out */ -1 }, 19048 19112 { { /* clr r64 */ { FP64_INT_C(0) } }, 19049 { /* src xmm */ { FP64_INF(0), 19050 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },19113 { /* src xmm */ { FP64_INF(0), FP64_RAND_x3_V1 } }, 19114 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 19051 19115 /*mxcsr:in */ 0, 19052 19116 /*128:out */ X86_MXCSR_IE, … … 19159 19223 /*20*/{ { /* clr r64 */ { FP64_INT_C(0) } }, 19160 19224 { /* src xmm */ { FP64_NORM_SAFE_INT_MAX(1), FP64_RAND_x3_V2 } }, 19161 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },19225 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 19162 19226 /*mxcsr:in */ 0, 19163 19227 /*128:out */ X86_MXCSR_IE, … … 19165 19229 { { /* clr r64 */ { FP64_INT_C(0) } }, 19166 19230 { /* src xmm */ { FP64_NORM_SAFE_INT_MAX(0), FP64_RAND_x3_V2 } }, 19167 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },19231 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 19168 19232 /*mxcsr:in */ 0, 19169 19233 /*128:out */ X86_MXCSR_IE, 19170 19234 /*256:out */ -1 }, 19171 19235 { { /* clr r64 */ { FP64_INT_C(0) } }, 19172 { /* src xmm */ { FP64_NORM_MAX(0), 19173 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },19236 { /* src xmm */ { FP64_NORM_MAX(0), FP64_RAND_x3_V2 } }, 19237 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 19174 19238 /*mxcsr:in */ 0, 19175 19239 /*128:out */ X86_MXCSR_IE, 19176 19240 /*256:out */ -1 }, 19177 19241 { { /* clr r64 */ { FP64_INT_C(0) } }, 19178 { /* src xmm */ { FP64_NORM_MAX(1), 19179 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },19242 { /* src xmm */ { FP64_NORM_MAX(1), FP64_RAND_x3_V2 } }, 19243 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 19180 19244 /*mxcsr:in */ 0, 19181 19245 /*128:out */ X86_MXCSR_IE, … … 19185 19249 */ 19186 19250 /*24*/{ { /* clr r64 */ { FP64_INT_C(0) } }, 19187 { /* src xmm */ { FP64_QNAN(0), 19188 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },19251 { /* src xmm */ { FP64_QNAN(0), FP64_RAND_x3_V2 } }, 19252 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 19189 19253 /*mxcsr:in */ 0, 19190 19254 /*128:out */ X86_MXCSR_IE, 19191 19255 /*256:out */ -1 }, 19192 19256 { { /* clr r64 */ { FP64_INT_C(0) } }, 19193 { /* src xmm */ { FP64_SNAN(1), 19194 { /* => r32 */ { FP64_INT32_INDEF INITE(0) } },19257 { /* src xmm */ { FP64_SNAN(1), FP64_RAND_x3_V2 } }, 19258 { /* => r32 */ { FP64_INT32_INDEF(0) } }, 19195 19259 /*mxcsr:in */ 0, 19196 19260 /*128:out */ X86_MXCSR_IE, … … 19218 19282 */ 19219 19283 /* 2*/{ { /* unused */ { FP64_ROW_UNUSED } }, 19220 { /* src xmm */ { FP64_INF(1) } },19221 { /* => r64 */ { FP64_INT_INDEF INITE} },19284 { /* src xmm */ { FP64_INF(1) } }, 19285 { /* => r64 */ { FP64_INT_INDEF } }, 19222 19286 /*mxcsr:in */ 0, 19223 19287 /*128:out */ X86_MXCSR_IE, 19224 19288 /*256:out */ -1 }, 19225 19289 { { /* unused */ { FP64_ROW_UNUSED } }, 19226 { /* src xmm */ { FP64_INF(0) } },19227 { /* => r64 */ { FP64_INT_INDEF INITE} },19290 { /* src xmm */ { FP64_INF(0) } }, 19291 { /* => r64 */ { FP64_INT_INDEF } }, 19228 19292 /*mxcsr:in */ 0, 19229 19293 /*128:out */ X86_MXCSR_IE, … … 19370 19434 * Overflow (Underflow not possible). 19371 19435 */ 19372 /*26*/{ { /* unused */ { FP64_ROW_UNUSED } },19436 /*26*/{ { /* unused */ { FP64_ROW_UNUSED } }, 19373 19437 { /* src xmm */ { FP64_NORM_MAX(0) } }, 19374 { /* => r64 */ { FP64_INT_INDEF INITE} },19438 { /* => r64 */ { FP64_INT_INDEF } }, 19375 19439 /*mxcsr:in */ 0, 19376 19440 /*128:out */ X86_MXCSR_IE, 19377 19441 /*256:out */ -1 }, 19442 { { /* unused */ { FP64_ROW_UNUSED } }, 19443 { /* src xmm */ { FP64_NORM_MAX(1) } }, 19444 { /* => r64 */ { FP64_INT_INDEF } }, 19445 /*mxcsr:in */ 0, 19446 /*128:out */ X86_MXCSR_IE, 19447 /*256:out */ -1 }, 19448 /* 19449 * Invalids. 19450 */ 19451 /*28*/{ { /* unused */ { FP64_ROW_UNUSED } }, 19452 { /* src xmm */ { FP64_QNAN(0) } }, 19453 { /* => r64 */ { FP64_INT_INDEF } }, 19454 /*mxcsr:in */ 0, 19455 /*128:out */ X86_MXCSR_IE, 19456 /*256:out */ -1 }, 19378 19457 { { /* unused */ { FP64_ROW_UNUSED } }, 19379 { /* src xmm */ { FP64_ NORM_MAX(1)} },19380 { /* => r64 */ { FP64_INT_INDEF INITE} },19458 { /* src xmm */ { FP64_SNAN(1) } }, 19459 { /* => r64 */ { FP64_INT_INDEF } }, 19381 19460 /*mxcsr:in */ 0, 19382 19461 /*128:out */ X86_MXCSR_IE, 19383 19462 /*256:out */ -1 }, 19384 /*19385 * Invalids.19386 */19387 /*28*/{ { /* unused */ { FP64_ROW_UNUSED } },19388 { /* src xmm */ { FP64_QNAN(0) } },19389 { /* => r64 */ { FP64_INT_INDEFINITE } },19390 /*mxcsr:in */ 0,19391 /*128:out */ X86_MXCSR_IE,19392 /*256:out */ -1 },19393 { { /* unused */ { FP64_ROW_UNUSED } },19394 { /* src xmm */ { FP64_SNAN(1) } },19395 { /* => r64 */ { FP64_INT_INDEFINITE } },19396 /*mxcsr:in */ 0,19397 /*128:out */ X86_MXCSR_IE,19398 /*256:out */ -1 },19399 19463 }; 19400 19464 19401 19465 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 19402 19466 { 19403 { bs3CpuInstr4_cvttsd2si_EAX_XMM1_icebp_c16, 255, RM_REG, T_SSE ,EAX, XMM1, NOREG, PASS_s_aValues32 },19404 { bs3CpuInstr4_cvttsd2si_EAX_FSxBX_icebp_c16, 255, RM_MEM, T_SSE ,EAX, FSxBX, NOREG, PASS_s_aValues32 },19467 { bs3CpuInstr4_cvttsd2si_EAX_XMM1_icebp_c16, 255, RM_REG, T_SSE2, EAX, XMM1, NOREG, PASS_s_aValues32 }, 19468 { bs3CpuInstr4_cvttsd2si_EAX_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, EAX, FSxBX, NOREG, PASS_s_aValues32 }, 19405 19469 19406 19470 { bs3CpuInstr4_vcvttsd2si_EAX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, EAX, XMM1, NOREG, PASS_s_aValues32 }, … … 19413 19477 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 19414 19478 { 19415 { bs3CpuInstr4_cvttsd2si_EAX_XMM1_icebp_c32, 255, RM_REG, T_SSE ,EAX, XMM1, NOREG, PASS_s_aValues32 },19416 { bs3CpuInstr4_cvttsd2si_EAX_FSxBX_icebp_c32, 255, RM_MEM, T_SSE ,EAX, FSxBX, NOREG, PASS_s_aValues32 },19479 { bs3CpuInstr4_cvttsd2si_EAX_XMM1_icebp_c32, 255, RM_REG, T_SSE2, EAX, XMM1, NOREG, PASS_s_aValues32 }, 19480 { bs3CpuInstr4_cvttsd2si_EAX_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, EAX, FSxBX, NOREG, PASS_s_aValues32 }, 19417 19481 19418 19482 { bs3CpuInstr4_vcvttsd2si_EAX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, EAX, XMM1, NOREG, PASS_s_aValues32 }, … … 19424 19488 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 19425 19489 { 19426 { bs3CpuInstr4_cvttsd2si_EAX_XMM1_icebp_c64, 255, RM_REG, T_SSE ,EAX, XMM1, RAX, PASS_s_aValues32 },19427 { bs3CpuInstr4_cvttsd2si_EAX_FSxBX_icebp_c64, 255, RM_MEM, T_SSE ,EAX, FSxBX, RAX, PASS_s_aValues32 },19428 19429 { bs3CpuInstr4_cvttsd2si_R8D_XMM8_icebp_c64, 255, RM_REG, T_SSE ,R8D, XMM8, R8, PASS_s_aValues32 },19430 { bs3CpuInstr4_cvttsd2si_R8D_FSxBX_icebp_c64, 255, RM_MEM, T_SSE ,R8D, FSxBX, R8, PASS_s_aValues32 },19490 { bs3CpuInstr4_cvttsd2si_EAX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, EAX, XMM1, RAX, PASS_s_aValues32 }, 19491 { bs3CpuInstr4_cvttsd2si_EAX_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, EAX, FSxBX, RAX, PASS_s_aValues32 }, 19492 19493 { bs3CpuInstr4_cvttsd2si_R8D_XMM8_icebp_c64, 255, RM_REG, T_SSE2, R8D, XMM8, R8, PASS_s_aValues32 }, 19494 { bs3CpuInstr4_cvttsd2si_R8D_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, R8D, FSxBX, R8, PASS_s_aValues32 }, 19431 19495 19432 19496 { bs3CpuInstr4_vcvttsd2si_EAX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, EAX, XMM1, RAX, PASS_s_aValues32 }, … … 19436 19500 { bs3CpuInstr4_vcvttsd2si_R8D_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, R8D, FSxBX, R8, PASS_s_aValues32 }, 19437 19501 19438 { bs3CpuInstr4_cvttsd2si_RAX_XMM1_icebp_c64, 255, RM_REG, T_SSE ,RAX, XMM1, NOREG, PASS_s_aValues64 },19439 { bs3CpuInstr4_cvttsd2si_RAX_FSxBX_icebp_c64, 255, RM_MEM, T_SSE ,RAX, FSxBX, NOREG, PASS_s_aValues64 },19440 19441 { bs3CpuInstr4_cvttsd2si_R8_XMM8_icebp_c64, 255, RM_REG, T_SSE ,R8, XMM8, NOREG, PASS_s_aValues64 },19442 { bs3CpuInstr4_cvttsd2si_R8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE ,R8, FSxBX, NOREG, PASS_s_aValues64 },19502 { bs3CpuInstr4_cvttsd2si_RAX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, RAX, XMM1, NOREG, PASS_s_aValues64 }, 19503 { bs3CpuInstr4_cvttsd2si_RAX_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, RAX, FSxBX, NOREG, PASS_s_aValues64 }, 19504 19505 { bs3CpuInstr4_cvttsd2si_R8_XMM8_icebp_c64, 255, RM_REG, T_SSE2, R8, XMM8, NOREG, PASS_s_aValues64 }, 19506 { bs3CpuInstr4_cvttsd2si_R8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, R8, FSxBX, NOREG, PASS_s_aValues64 }, 19443 19507 19444 19508 { bs3CpuInstr4_vcvttsd2si_RAX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, RAX, XMM1, NOREG, PASS_s_aValues64 }, … … 19453 19517 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 19454 19518 g_aXcptConfig3, RT_ELEMENTS(g_aXcptConfig3)); 19519 } 19520 19521 19522 /* 19523 * CVTDQ2PS. 19524 */ 19525 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_cvtdq2ps(uint8_t bMode) 19526 { 19527 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = 19528 { 19529 /* 19530 * Zero. 19531 */ 19532 /* 0*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19533 { /* src ymm */ { FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0) } }, 19534 { /* => ymm */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 19535 /*mxcsr:in */ 0, 19536 /*128:out */ 0, 19537 /*256:out */ 0 }, 19538 /* 19539 * Normals & Precision. 19540 */ 19541 /* 1*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19542 { /* src ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123457), FP32_INT_C(-123457), FP32_INT_C(-1), FP32_INT_C(1) } }, 19543 { /* => ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_V(1,0x7fffff,0x96), FP32_V(0,0x7fffff,0x96), FP32_V(0,0x712080,0x8f), FP32_V(1,0x712080,0x8f), FP32_1(1), FP32_1(0) } }, 19544 /*mxcsr:in */ 0, 19545 /*128:out */ 0, 19546 /*256:out */ 0 }, 19547 { { /* unused */ { FP32_ROW_UNUSED } }, 19548 { /* src ymm */ { FP32_INT_C(-2), FP32_INT_C(2), FP32_INT(INT32_MAX), FP32_INT(-INT32_MAX), FP32_INT_C(123456789), FP32_INT_C(-123456789), FP32_INT_C(-47), FP32_INT_C(42) } }, 19549 { /* => ymm */ { FP32_2(1), FP32_2(0), FP32_V(0,0,0x9e), FP32_V(1,0,0x9e), FP32_V(0,0x6b79a3,0x99), FP32_V(1,0x6b79a3,0x99), FP32_V(1,0x3c0000,0x84), FP32_V(0,0x280000,0x84) } }, 19550 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 19551 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE, 19552 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE }, 19553 { { /* unused */ { FP32_ROW_UNUSED } }, 19554 { /* src ymm */ { FP32_INT_C(-2), FP32_INT_C(2), FP32_INT(INT32_MAX), FP32_INT(-INT32_MAX), FP32_INT_C(123456789), FP32_INT_C(-123456789), FP32_INT_C(-47), FP32_INT_C(42) } }, 19555 { /* => ymm */ { FP32_2(1), FP32_2(0), FP32_V(0,0,0x9e), FP32_V(1,0,0x9e), FP32_V(0,0x6b79a3,0x99), FP32_V(1,0x6b79a3,0x99), FP32_V(1,0x3c0000,0x84), FP32_V(0,0x280000,0x84) } }, 19556 /*mxcsr:in */ 0, 19557 /*128:out */ X86_MXCSR_PE, 19558 /*256:out */ X86_MXCSR_PE }, 19559 { { /* unused */ { FP32_ROW_UNUSED } }, 19560 { /* src ymm */ { FP32_INT_C(-2), FP32_INT_C(2), FP32_INT(INT32_MAX), FP32_INT(-INT32_MAX), FP32_INT_C(123456789), FP32_INT_C(-123456789), FP32_INT_C(-47), FP32_INT_C(42) } }, 19561 { /* => ymm */ { FP32_2(1), FP32_2(0), FP32_V(0,0,0x9e), FP32_V(1,0x7fffff,0x9d), FP32_V(0,0x6b79a3,0x99), FP32_V(1,0x6b79a2,0x99), FP32_V(1,0x3c0000,0x84), FP32_V(0,0x280000,0x84) } }, 19562 /*2147483648.0*/ /*-2147483520.0*/ /*123456792.0*/ /*-123456784.0*/ 19563 /*mxcsr:in */ X86_MXCSR_RC_UP, 19564 /*128:out */ X86_MXCSR_RC_UP | X86_MXCSR_PE, 19565 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_PE }, 19566 { { /* unused */ { FP32_ROW_UNUSED } }, 19567 { /* src ymm */ { FP32_INT_C(-2), FP32_INT_C(2), FP32_INT(INT32_MAX), FP32_INT(-INT32_MAX), FP32_INT_C(123456789), FP32_INT_C(-123456789), FP32_INT_C(-47), FP32_INT_C(42) } }, 19568 { /* => ymm */ { FP32_2(1), FP32_2(0), FP32_V(0,0x7fffff,0x9d), FP32_V(1,0,0x9e), FP32_V(0,0x6b79a2,0x99), FP32_V(1,0x6b79a3,0x99), FP32_V(1,0x3c0000,0x84), FP32_V(0,0x280000,0x84) } }, 19569 /*2147483520.0*/ /*-2147483648.0*/ /*123456784.0*/ /*-123456792.0*/ 19570 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 19571 /*128:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_PE, 19572 /*256:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, 19573 { { /* unused */ { FP32_ROW_UNUSED } }, 19574 { /* src ymm */ { FP32_INT_C(-2), FP32_INT_C(2), FP32_INT(INT32_MAX), FP32_INT(-INT32_MAX), FP32_INT_C(123456789), FP32_INT_C(-123456789), FP32_INT_C(-47), FP32_INT_C(42) } }, 19575 { /* => ymm */ { FP32_2(1), FP32_2(0), FP32_V(0,0x7fffff,0x9d), FP32_V(1,0x7fffff,0x9d), FP32_V(0,0x6b79a2,0x99), FP32_V(1,0x6b79a2,0x99), FP32_V(1,0x3c0000,0x84), FP32_V(0,0x280000,0x84) } }, 19576 /*2147483520.0*/ /*-2147483520.0*/ /*123456784.0*/ /*-123456784.0*/ 19577 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 19578 /*128:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE, 19579 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 19580 /* 19581 * Not invalid, but unusual: Intel define the 'indefinite integer' as 10000...0b 19582 */ 19583 /* 7*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19584 { /* src ymm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF } }, 19585 { /* => ymm */ { FP32_V(1,0,0x9e), FP32_V(1,0,0x9e), FP32_V(1,0,0x9e), FP32_V(1,0,0x9e), FP32_V(1,0,0x9e), FP32_V(1,0,0x9e), FP32_V(1,0,0x9e), FP32_V(1,0,0x9e) } }, 19586 /*mxcsr:in */ 0, 19587 /*128:out */ 0, 19588 /*256:out */ 0 }, 19589 /* 19590 * Infinity, Overflow, Underflow, Denormal, Invalid not possible. 19591 */ 19592 }; 19593 19594 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 19595 { 19596 { bs3CpuInstr4_cvtdq2ps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 19597 { bs3CpuInstr4_cvtdq2ps_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19598 19599 { bs3CpuInstr4_vcvtdq2ps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 19600 { bs3CpuInstr4_vcvtdq2ps_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19601 19602 { bs3CpuInstr4_vcvtdq2ps_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, YMM2, NOREG, PASS_s_aValues }, 19603 { bs3CpuInstr4_vcvtdq2ps_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 19604 19605 { bs3CpuInstr4_cvtdq2ps_XMM1_XMM1_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 19606 { bs3CpuInstr4_vcvtdq2ps_XMM1_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 19607 { bs3CpuInstr4_vcvtdq2ps_YMM1_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, YMM1, NOREG, PASS_s_aValues }, 19608 }; 19609 19610 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 19611 { 19612 { bs3CpuInstr4_cvtdq2ps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 19613 { bs3CpuInstr4_cvtdq2ps_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19614 19615 { bs3CpuInstr4_vcvtdq2ps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 19616 { bs3CpuInstr4_vcvtdq2ps_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19617 19618 { bs3CpuInstr4_vcvtdq2ps_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, YMM2, NOREG, PASS_s_aValues }, 19619 { bs3CpuInstr4_vcvtdq2ps_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 19620 19621 { bs3CpuInstr4_cvtdq2ps_XMM1_XMM1_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 19622 { bs3CpuInstr4_vcvtdq2ps_XMM1_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 19623 { bs3CpuInstr4_vcvtdq2ps_YMM1_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, YMM1, NOREG, PASS_s_aValues }, 19624 }; 19625 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 19626 { 19627 { bs3CpuInstr4_cvtdq2ps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 19628 { bs3CpuInstr4_cvtdq2ps_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19629 19630 { bs3CpuInstr4_vcvtdq2ps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 19631 { bs3CpuInstr4_vcvtdq2ps_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19632 19633 { bs3CpuInstr4_vcvtdq2ps_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, YMM2, NOREG, PASS_s_aValues }, 19634 { bs3CpuInstr4_vcvtdq2ps_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 19635 19636 { bs3CpuInstr4_cvtdq2ps_XMM1_XMM1_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 19637 { bs3CpuInstr4_vcvtdq2ps_XMM1_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 19638 { bs3CpuInstr4_vcvtdq2ps_YMM1_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, YMM1, NOREG, PASS_s_aValues }, 19639 19640 { bs3CpuInstr4_cvtdq2ps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM9, NOREG, PASS_s_aValues }, 19641 { bs3CpuInstr4_cvtdq2ps_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM8, FSxBX, NOREG, PASS_s_aValues }, 19642 19643 { bs3CpuInstr4_vcvtdq2ps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM9, NOREG, PASS_s_aValues }, 19644 { bs3CpuInstr4_vcvtdq2ps_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM8, FSxBX, NOREG, PASS_s_aValues }, 19645 19646 { bs3CpuInstr4_vcvtdq2ps_YMM8_YMM9_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, YMM9, NOREG, PASS_s_aValues }, 19647 { bs3CpuInstr4_vcvtdq2ps_YMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM8, FSxBX, NOREG, PASS_s_aValues }, 19648 19649 { bs3CpuInstr4_cvtdq2ps_XMM8_XMM8_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM8, NOREG, PASS_s_aValues }, 19650 { bs3CpuInstr4_vcvtdq2ps_XMM8_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM8, NOREG, PASS_s_aValues }, 19651 { bs3CpuInstr4_vcvtdq2ps_YMM8_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, YMM8, NOREG, PASS_s_aValues }, 19652 }; 19653 19654 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 19655 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 19656 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 19657 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); 19658 } 19659 19660 19661 /* 19662 * CVTPS2DQ. 19663 */ 19664 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_cvtps2dq(uint8_t bMode) 19665 { 19666 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = 19667 { 19668 /* 19669 * Zero. 19670 */ 19671 /* 0*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19672 { /* src ymm */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 19673 { /* => ymm */ { FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0) } }, 19674 /*mxcsr:in */ 0, 19675 /*128:out */ 0, 19676 /*256:out */ 0 }, 19677 /* 19678 * Infinity. 19679 */ 19680 /* 1*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19681 { /* src ymm */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 19682 { /* => ymm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF } }, 19683 /*mxcsr:in */ 0, 19684 /*128:out */ X86_MXCSR_IE, 19685 /*256:out */ X86_MXCSR_IE }, 19686 /* 19687 * Normals & Precision. 19688 */ 19689 /* 2*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19690 { /* src ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0,0x712073,0x8f)/*123456.9*/, FP32_V(1,0x712073,0x8f)/*-123456.9*/, FP32_V(1,0x766666,0x7e)/*-0.9*/, FP32_V(0,0x766666,0x7e)/*0.9*/ } }, 19691 { /* => ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123457), FP32_INT_C(-123457), FP32_INT_C(-1), FP32_INT_C(1) } }, 19692 /*mxcsr:in */ 0, 19693 /*128:out */ 0, 19694 /*256:out */ X86_MXCSR_PE }, 19695 { { /* unused */ { FP32_ROW_UNUSED } }, 19696 { /* src ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0,0x712073,0x8f)/*123456.9*/, FP32_V(1,0x712073,0x8f)/*-123456.9*/, FP32_V(1,0x766666,0x7e)/*-0.9*/, FP32_V(0,0x766666,0x7e)/*0.9*/ } }, 19697 { /* => ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123456), FP32_INT_C(-123457), FP32_INT_C(-1), FP32_INT_C(0) } }, 19698 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 19699 /*128:out */ X86_MXCSR_RC_DOWN, 19700 /*256:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, 19701 { { /* unused */ { FP32_ROW_UNUSED } }, 19702 { /* src ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0,0x712073,0x8f)/*123456.9*/, FP32_V(1,0x712073,0x8f)/*-123456.9*/, FP32_V(1,0x766666,0x7e)/*-0.9*/, FP32_V(0,0x766666,0x7e)/*0.9*/ } }, 19703 { /* => ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123457), FP32_INT_C(-123456), FP32_INT_C(0), FP32_INT_C(1) } }, 19704 /*mxcsr:in */ X86_MXCSR_RC_UP, 19705 /*128:out */ X86_MXCSR_RC_UP, 19706 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_PE }, 19707 { { /* unused */ { FP32_ROW_UNUSED } }, 19708 { /* src ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0,0x712073,0x8f)/*123456.9*/, FP32_V(1,0x712073,0x8f)/*-123456.9*/, FP32_V(1,0x766666,0x7e)/*-0.9*/, FP32_V(0,0x766666,0x7e)/*0.9*/ } }, 19709 { /* => ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(0), FP32_INT_C(0) } }, 19710 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 19711 /*128:out */ X86_MXCSR_RC_ZERO, 19712 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 19713 { { /* unused */ { FP32_ROW_UNUSED } }, 19714 { /* src ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0,0x712073,0x8f)/*123456.9*/, FP32_V(1,0x712073,0x8f)/*-123456.9*/, FP32_V(1,0x766666,0x7e)/*-0.9*/, FP32_V(0,0x766666,0x7e)/*0.9*/ } }, 19715 { /* => ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123457), FP32_INT_C(-123457), FP32_INT_C(-1), FP32_INT_C(1) } }, 19716 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 19717 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 19718 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE }, 19719 /* 19720 * Denormals. 19721 */ 19722 /* 7*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19723 { /* src ymm */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_V0(1), FP32_DENORM_V1(0), FP32_DENORM_V2(1), FP32_DENORM_V3(0) } }, 19724 { /* => ymm */ { FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0) } }, 19725 /*mxcsr:in */ 0, 19726 /*128:out */ X86_MXCSR_PE, 19727 /*256:out */ X86_MXCSR_PE }, 19728 { { /* unused */ { FP32_ROW_UNUSED } }, 19729 { /* src ymm */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_V0(1), FP32_DENORM_V1(0), FP32_DENORM_V2(1), FP32_DENORM_V3(0) } }, 19730 { /* => ymm */ { FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0) } }, 19731 /*mxcsr:in */ X86_MXCSR_DAZ, 19732 /*128:out */ X86_MXCSR_DAZ, 19733 /*256:out */ X86_MXCSR_DAZ }, 19734 /* 19735 * Overflow (Underflow not possible). 19736 */ 19737 /* 9*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19738 { /* src ymm */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_RAND_V1(1), FP32_NORM_V5(0), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_NORM_V3(1), FP32_NORM_V3(0) } }, 19739 { /* => ymm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF } }, 19740 /*mxcsr:in */ 0, 19741 /*128:out */ X86_MXCSR_IE, 19742 /*256:out */ X86_MXCSR_IE }, 19743 /* 19744 * Invalids. 19745 */ 19746 /*10*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19747 { /* src ymm */ { FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_QNAN_V1(1), FP32_QNAN_V5(0), FP32_QNAN_V7(1), FP32_QNAN_V2(0), FP32_QNAN_V3(1), FP32_QNAN_V3(0) } }, 19748 { /* => ymm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF } }, 19749 /*mxcsr:in */ 0, 19750 /*128:out */ X86_MXCSR_IE, 19751 /*256:out */ X86_MXCSR_IE }, 19752 { { /* unused */ { FP32_ROW_UNUSED } }, 19753 { /* src ymm */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(1), FP32_SNAN_V1(1), FP32_SNAN_V5(0), FP32_SNAN_V7(1), FP32_SNAN_V2(0), FP32_SNAN_V3(1), FP32_SNAN_V3(0) } }, 19754 { /* => ymm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF } }, 19755 /*mxcsr:in */ 0, 19756 /*128:out */ X86_MXCSR_IE, 19757 /*256:out */ X86_MXCSR_IE }, 19758 }; 19759 19760 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 19761 { 19762 { bs3CpuInstr4_cvtps2dq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 19763 { bs3CpuInstr4_cvtps2dq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19764 19765 { bs3CpuInstr4_vcvtps2dq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 19766 { bs3CpuInstr4_vcvtps2dq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19767 19768 { bs3CpuInstr4_vcvtps2dq_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, YMM2, NOREG, PASS_s_aValues }, 19769 { bs3CpuInstr4_vcvtps2dq_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 19770 19771 { bs3CpuInstr4_cvtps2dq_XMM1_XMM1_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 19772 { bs3CpuInstr4_vcvtps2dq_XMM1_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 19773 { bs3CpuInstr4_vcvtps2dq_YMM1_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, YMM1, NOREG, PASS_s_aValues }, 19774 }; 19775 19776 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 19777 { 19778 { bs3CpuInstr4_cvtps2dq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 19779 { bs3CpuInstr4_cvtps2dq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19780 19781 { bs3CpuInstr4_vcvtps2dq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 19782 { bs3CpuInstr4_vcvtps2dq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19783 19784 { bs3CpuInstr4_vcvtps2dq_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, YMM2, NOREG, PASS_s_aValues }, 19785 { bs3CpuInstr4_vcvtps2dq_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 19786 19787 { bs3CpuInstr4_cvtps2dq_XMM1_XMM1_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 19788 { bs3CpuInstr4_vcvtps2dq_XMM1_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 19789 { bs3CpuInstr4_vcvtps2dq_YMM1_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, YMM1, NOREG, PASS_s_aValues }, 19790 }; 19791 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 19792 { 19793 { bs3CpuInstr4_cvtps2dq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 19794 { bs3CpuInstr4_cvtps2dq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19795 19796 { bs3CpuInstr4_vcvtps2dq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 19797 { bs3CpuInstr4_vcvtps2dq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19798 19799 { bs3CpuInstr4_vcvtps2dq_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, YMM2, NOREG, PASS_s_aValues }, 19800 { bs3CpuInstr4_vcvtps2dq_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 19801 19802 { bs3CpuInstr4_cvtps2dq_XMM1_XMM1_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 19803 { bs3CpuInstr4_vcvtps2dq_XMM1_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 19804 { bs3CpuInstr4_vcvtps2dq_YMM1_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, YMM1, NOREG, PASS_s_aValues }, 19805 19806 { bs3CpuInstr4_cvtps2dq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM9, NOREG, PASS_s_aValues }, 19807 { bs3CpuInstr4_cvtps2dq_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM8, FSxBX, NOREG, PASS_s_aValues }, 19808 19809 { bs3CpuInstr4_vcvtps2dq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM9, NOREG, PASS_s_aValues }, 19810 { bs3CpuInstr4_vcvtps2dq_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM8, FSxBX, NOREG, PASS_s_aValues }, 19811 19812 { bs3CpuInstr4_vcvtps2dq_YMM8_YMM9_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, YMM9, NOREG, PASS_s_aValues }, 19813 { bs3CpuInstr4_vcvtps2dq_YMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM8, FSxBX, NOREG, PASS_s_aValues }, 19814 19815 { bs3CpuInstr4_cvtps2dq_XMM8_XMM8_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM8, NOREG, PASS_s_aValues }, 19816 { bs3CpuInstr4_vcvtps2dq_XMM8_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM8, NOREG, PASS_s_aValues }, 19817 { bs3CpuInstr4_vcvtps2dq_YMM8_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, YMM8, NOREG, PASS_s_aValues }, 19818 }; 19819 19820 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 19821 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 19822 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 19823 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); 19824 } 19825 19826 19827 /* 19828 * CVTTPS2DQ. 19829 */ 19830 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_cvttps2dq(uint8_t bMode) 19831 { 19832 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues[] = 19833 { 19834 /* 19835 * Zero. 19836 */ 19837 /* 0*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19838 { /* src ymm */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 19839 { /* => ymm */ { FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0) } }, 19840 /*mxcsr:in */ 0, 19841 /*128:out */ 0, 19842 /*256:out */ 0 }, 19843 /* 19844 * Infinity. 19845 */ 19846 /* 1*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19847 { /* src ymm */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 19848 { /* => ymm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF } }, 19849 /*mxcsr:in */ 0, 19850 /*128:out */ X86_MXCSR_IE, 19851 /*256:out */ X86_MXCSR_IE }, 19852 /* 19853 * Normals & Precision. 19854 */ 19855 /* 2*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19856 { /* src ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0,0x712073,0x8f)/*123456.9*/, FP32_V(1,0x712073,0x8f)/*-123456.9*/, FP32_V(1,0x766666,0x7e)/*-0.9*/, FP32_V(0,0x766666,0x7e)/*0.9*/ } }, 19857 { /* => ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(0), FP32_INT_C(0) } }, 19858 /*mxcsr:in */ 0, 19859 /*128:out */ 0, 19860 /*256:out */ X86_MXCSR_PE }, 19861 { { /* unused */ { FP32_ROW_UNUSED } }, 19862 { /* src ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0,0x712073,0x8f)/*123456.9*/, FP32_V(1,0x712073,0x8f)/*-123456.9*/, FP32_V(1,0x766666,0x7e)/*-0.9*/, FP32_V(0,0x766666,0x7e)/*0.9*/ } }, 19863 { /* => ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(0), FP32_INT_C(0) } }, 19864 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 19865 /*128:out */ X86_MXCSR_RC_DOWN, 19866 /*256:out */ X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, 19867 { { /* unused */ { FP32_ROW_UNUSED } }, 19868 { /* src ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0,0x712073,0x8f)/*123456.9*/, FP32_V(1,0x712073,0x8f)/*-123456.9*/, FP32_V(1,0x766666,0x7e)/*-0.9*/, FP32_V(0,0x766666,0x7e)/*0.9*/ } }, 19869 { /* => ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(0), FP32_INT_C(0) } }, 19870 /*mxcsr:in */ X86_MXCSR_RC_UP, 19871 /*128:out */ X86_MXCSR_RC_UP, 19872 /*256:out */ X86_MXCSR_RC_UP | X86_MXCSR_PE }, 19873 { { /* unused */ { FP32_ROW_UNUSED } }, 19874 { /* src ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0,0x712073,0x8f)/*123456.9*/, FP32_V(1,0x712073,0x8f)/*-123456.9*/, FP32_V(1,0x766666,0x7e)/*-0.9*/, FP32_V(0,0x766666,0x7e)/*0.9*/ } }, 19875 { /* => ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(0), FP32_INT_C(0) } }, 19876 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 19877 /*128:out */ X86_MXCSR_RC_ZERO, 19878 /*256:out */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, 19879 { { /* unused */ { FP32_ROW_UNUSED } }, 19880 { /* src ymm */ { FP32_V(0,0x712000,0x8f), FP32_V(1,0x712000,0x8f), FP32_NORM_SAFE_INT_MAX(1), FP32_NORM_SAFE_INT_MAX(0), FP32_V(0,0x712073,0x8f)/*123456.9*/, FP32_V(1,0x712073,0x8f)/*-123456.9*/, FP32_V(1,0x766666,0x7e)/*-0.9*/, FP32_V(0,0x766666,0x7e)/*0.9*/ } }, 19881 { /* => ymm */ { FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(-16777215), FP32_INT_C(16777215), FP32_INT_C(123456), FP32_INT_C(-123456), FP32_INT_C(0), FP32_INT_C(0) } }, 19882 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 19883 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 19884 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ | X86_MXCSR_PE }, 19885 /* 19886 * Denormals. 19887 */ 19888 /* 7*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19889 { /* src ymm */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_V0(1), FP32_DENORM_V1(0), FP32_DENORM_V2(1), FP32_DENORM_V3(0) } }, 19890 { /* => ymm */ { FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0) } }, 19891 /*mxcsr:in */ 0, 19892 /*128:out */ X86_MXCSR_PE, 19893 /*256:out */ X86_MXCSR_PE }, 19894 { { /* unused */ { FP32_ROW_UNUSED } }, 19895 { /* src ymm */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(0), FP32_DENORM_MIN(1), FP32_DENORM_V0(1), FP32_DENORM_V1(0), FP32_DENORM_V2(1), FP32_DENORM_V3(0) } }, 19896 { /* => ymm */ { FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0), FP32_INT(0) } }, 19897 /*mxcsr:in */ X86_MXCSR_DAZ, 19898 /*128:out */ X86_MXCSR_DAZ, 19899 /*256:out */ X86_MXCSR_DAZ }, 19900 /* 19901 * Overflow (Underflow not possible). 19902 */ 19903 /* 9*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19904 { /* src ymm */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_RAND_V1(1), FP32_NORM_V5(0), FP32_RAND_V7(1), FP32_RAND_V2(0), FP32_NORM_V3(1), FP32_NORM_V3(0) } }, 19905 { /* => ymm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF } }, 19906 /*mxcsr:in */ 0, 19907 /*128:out */ X86_MXCSR_IE, 19908 /*256:out */ X86_MXCSR_IE }, 19909 /* 19910 * Invalids. 19911 */ 19912 /*10*/{ { /* unused */ { FP32_ROW_UNUSED } }, 19913 { /* src ymm */ { FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_QNAN_V1(1), FP32_QNAN_V5(0), FP32_QNAN_V7(1), FP32_QNAN_V2(0), FP32_QNAN_V3(1), FP32_QNAN_V3(0) } }, 19914 { /* => ymm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF } }, 19915 /*mxcsr:in */ 0, 19916 /*128:out */ X86_MXCSR_IE, 19917 /*256:out */ X86_MXCSR_IE }, 19918 { { /* unused */ { FP32_ROW_UNUSED } }, 19919 { /* src ymm */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(1), FP32_SNAN_V1(1), FP32_SNAN_V5(0), FP32_SNAN_V7(1), FP32_SNAN_V2(0), FP32_SNAN_V3(1), FP32_SNAN_V3(0) } }, 19920 { /* => ymm */ { FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF, FP32_INT_INDEF } }, 19921 /*mxcsr:in */ 0, 19922 /*128:out */ X86_MXCSR_IE, 19923 /*256:out */ X86_MXCSR_IE }, 19924 }; 19925 19926 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 19927 { 19928 { bs3CpuInstr4_cvttps2dq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 19929 { bs3CpuInstr4_cvttps2dq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19930 19931 { bs3CpuInstr4_vcvttps2dq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 19932 { bs3CpuInstr4_vcvttps2dq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19933 19934 { bs3CpuInstr4_vcvttps2dq_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, YMM2, NOREG, PASS_s_aValues }, 19935 { bs3CpuInstr4_vcvttps2dq_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 19936 19937 { bs3CpuInstr4_cvttps2dq_XMM1_XMM1_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 19938 { bs3CpuInstr4_vcvttps2dq_XMM1_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 19939 { bs3CpuInstr4_vcvttps2dq_YMM1_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, YMM1, NOREG, PASS_s_aValues }, 19940 }; 19941 19942 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 19943 { 19944 { bs3CpuInstr4_cvttps2dq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 19945 { bs3CpuInstr4_cvttps2dq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19946 19947 { bs3CpuInstr4_vcvttps2dq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 19948 { bs3CpuInstr4_vcvttps2dq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19949 19950 { bs3CpuInstr4_vcvttps2dq_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, YMM2, NOREG, PASS_s_aValues }, 19951 { bs3CpuInstr4_vcvttps2dq_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 19952 19953 { bs3CpuInstr4_cvttps2dq_XMM1_XMM1_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 19954 { bs3CpuInstr4_vcvttps2dq_XMM1_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 19955 { bs3CpuInstr4_vcvttps2dq_YMM1_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, YMM1, NOREG, PASS_s_aValues }, 19956 }; 19957 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 19958 { 19959 { bs3CpuInstr4_cvttps2dq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 19960 { bs3CpuInstr4_cvttps2dq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19961 19962 { bs3CpuInstr4_vcvttps2dq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 19963 { bs3CpuInstr4_vcvttps2dq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 19964 19965 { bs3CpuInstr4_vcvttps2dq_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, YMM2, NOREG, PASS_s_aValues }, 19966 { bs3CpuInstr4_vcvttps2dq_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 19967 19968 { bs3CpuInstr4_cvttps2dq_XMM1_XMM1_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 19969 { bs3CpuInstr4_vcvttps2dq_XMM1_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 19970 { bs3CpuInstr4_vcvttps2dq_YMM1_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, YMM1, NOREG, PASS_s_aValues }, 19971 19972 { bs3CpuInstr4_cvttps2dq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM9, NOREG, PASS_s_aValues }, 19973 { bs3CpuInstr4_cvttps2dq_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM8, FSxBX, NOREG, PASS_s_aValues }, 19974 19975 { bs3CpuInstr4_vcvttps2dq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM9, NOREG, PASS_s_aValues }, 19976 { bs3CpuInstr4_vcvttps2dq_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM8, FSxBX, NOREG, PASS_s_aValues }, 19977 19978 { bs3CpuInstr4_vcvttps2dq_YMM8_YMM9_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, YMM9, NOREG, PASS_s_aValues }, 19979 { bs3CpuInstr4_vcvttps2dq_YMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, YMM8, FSxBX, NOREG, PASS_s_aValues }, 19980 19981 { bs3CpuInstr4_cvttps2dq_XMM8_XMM8_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM8, NOREG, PASS_s_aValues }, 19982 { bs3CpuInstr4_vcvttps2dq_XMM8_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM8, NOREG, PASS_s_aValues }, 19983 { bs3CpuInstr4_vcvttps2dq_YMM8_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, YMM8, NOREG, PASS_s_aValues }, 19984 }; 19985 19986 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 19987 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 19988 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 19989 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); 19990 } 19991 19992 19993 /* 19994 * CVTDQ2PD. 19995 */ 19996 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_cvtdq2pd(uint8_t bMode) 19997 { 19998 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] = 19999 { 20000 /* 20001 * Zero. 20002 */ 20003 /* 0*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20004 { /* src xmm */ { FP64_INT32_C(0, 0), FP64_INT32_C(0, 0) } }, 20005 { /* => ymm */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 20006 /*mxcsr:in */ 0, 20007 /*128:out */ 0, 20008 /*256:out */ 0 }, 20009 /* 20010 * Normals. 20011 */ 20012 /* 1*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20013 { /* src xmm */ { FP64_INT32_C(123456789, -123456789), FP64_INT32_C(-47, 42) } }, 20014 { /* => ymm */ { FP64_V(0,0xd6f3454000000,0x419), FP64_V(1,0xd6f3454000000,0x419), FP64_V(1,0x7800000000000,0x404), FP64_V(0,0x5000000000000,0x404) } }, 20015 /*123456789.0*/ /*-123456789.0*/ /*-47.0*/ /*42.0*/ 20016 /*mxcsr:in */ 0, 20017 /*128:out */ 0, 20018 /*256:out */ 0 }, 20019 { { /* unused */ { FP64_ROW_UNUSED } }, 20020 { /* src xmm */ { FP64_INT32(INT32_MAX, -2), FP64_INT32_C(-1, -0) } }, 20021 { /* => ymm */ { FP64_V(0,0xfffffffc00000,0x41d), FP64_2(1), FP64_1(1), FP64_0(0) } }, 20022 /*2147483648.0*/ 20023 /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 20024 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ, 20025 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DAZ }, 20026 { { /* unused */ { FP64_ROW_UNUSED } }, 20027 { /* src xmm */ { FP64_INT32(INT32_MAX, 2), FP64_INT32_C(1, 0) } }, 20028 { /* => ymm */ { FP64_V(0,0xfffffffc00000,0x41d), FP64_2(0), FP64_1(0), FP64_0(0) } }, 20029 /*2147483648.0*/ 20030 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 20031 /*128:out */ X86_MXCSR_RC_DOWN, 20032 /*256:out */ X86_MXCSR_RC_DOWN }, 20033 { { /* unused */ { FP64_ROW_UNUSED } }, 20034 { /* src xmm */ { FP64_INT32(INT32_MAX, -INT32_MAX), FP64_INT32_C(123456789, -123456789) } }, 20035 { /* => ymm */ { FP64_V(0,0xfffffffc00000,0x41d), FP64_V(1,0xfffffffc00000,0x41d), FP64_V(0,0xd6f3454000000,0x419), FP64_V(1,0xd6f3454000000,0x419) } }, 20036 /*2147483648.0*/ /*-2147483648.0*/ /*123456789.0*/ /*-123456789.0*/ 20037 /*mxcsr:in */ X86_MXCSR_RC_UP, 20038 /*128:out */ X86_MXCSR_RC_UP, 20039 /*256:out */ X86_MXCSR_RC_UP }, 20040 { { /* unused */ { FP64_ROW_UNUSED } }, 20041 { /* src xmm */ { FP64_INT32(INT32_MAX, -INT32_MAX), FP64_INT32_C(123456789, -123456789) } }, 20042 { /* => ymm */ { FP64_V(0,0xfffffffc00000,0x41d), FP64_V(1,0xfffffffc00000,0x41d), FP64_V(0,0xd6f3454000000,0x419), FP64_V(1,0xd6f3454000000,0x419) } }, 20043 /*2147483648.0*/ /*-2147483648.0*/ /*123456789.0*/ /*-123456789.0*/ 20044 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 20045 /*128:out */ X86_MXCSR_RC_ZERO, 20046 /*256:out */ X86_MXCSR_RC_ZERO }, 20047 /* 20048 * Not invalid, but unusual: Intel define the 'indefinite integer' as 10000...0b 20049 */ 20050 /* 6*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20051 { /* src xmm */ { FP64_INT32_INDEF( -47), FP64_INT32_INDEF( -47) } }, 20052 { /* => ymm */ { FP64_V(1,0x0,0x41e), FP64_V(1,0x7800000000000,0x404), FP64_V(1,0x0,0x41e), FP64_V(1,0x7800000000000,0x404) } }, 20053 /*mxcsr:in */ 0, 20054 /*128:out */ 0, 20055 /*256:out */ 0 }, 20056 /* 20057 * Precision, Infinity, Overflow, Underflow, Denormal, Invalid not possible. 20058 */ 20059 }; 20060 20061 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 20062 { 20063 { bs3CpuInstr4_cvtdq2pd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 20064 #ifdef TODO_CVTDQ2PD_M64_IEM /** @todo THIS FAILS ON IEM: unexpected #GP */ 20065 { bs3CpuInstr4_cvtdq2pd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 20066 #endif /* TODO_CVTDQ2PD_M64_IEM */ 20067 20068 { bs3CpuInstr4_vcvtdq2pd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 20069 { bs3CpuInstr4_vcvtdq2pd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 20070 20071 { bs3CpuInstr4_vcvtdq2pd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, XMM2, NOREG, PASS_s_aValues }, 20072 { bs3CpuInstr4_vcvtdq2pd_YMM1_FSxBX_icebp_c16, BS3_XCPT_NOT_AC, RM_MEM128, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 20073 20074 { bs3CpuInstr4_cvtdq2pd_XMM1_XMM1_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 20075 { bs3CpuInstr4_vcvtdq2pd_XMM1_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 20076 { bs3CpuInstr4_vcvtdq2pd_YMM1_XMM1_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, XMM1, NOREG, PASS_s_aValues }, 20077 }; 20078 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 20079 { 20080 { bs3CpuInstr4_cvtdq2pd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 20081 #ifdef TODO_CVTDQ2PD_M64_IEM /** @todo THIS FAILS ON IEM: unexpected #GP */ 20082 { bs3CpuInstr4_cvtdq2pd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 20083 #endif /* TODO_CVTDQ2PD_M64_IEM */ 20084 20085 { bs3CpuInstr4_vcvtdq2pd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 20086 { bs3CpuInstr4_vcvtdq2pd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 20087 20088 { bs3CpuInstr4_vcvtdq2pd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, XMM2, NOREG, PASS_s_aValues }, 20089 { bs3CpuInstr4_vcvtdq2pd_YMM1_FSxBX_icebp_c32, BS3_XCPT_NOT_AC, RM_MEM128, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 20090 20091 { bs3CpuInstr4_cvtdq2pd_XMM1_XMM1_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 20092 { bs3CpuInstr4_vcvtdq2pd_XMM1_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 20093 { bs3CpuInstr4_vcvtdq2pd_YMM1_XMM1_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, XMM1, NOREG, PASS_s_aValues }, 20094 }; 20095 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 20096 { 20097 { bs3CpuInstr4_cvtdq2pd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValues }, 20098 #ifdef TODO_CVTDQ2PD_M64_IEM /** @todo THIS FAILS ON IEM: unexpected #GP */ 20099 { bs3CpuInstr4_cvtdq2pd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValues }, 20100 #endif /* TODO_CVTDQ2PD_M64_IEM */ 20101 20102 { bs3CpuInstr4_vcvtdq2pd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValues }, 20103 { bs3CpuInstr4_vcvtdq2pd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValues }, 20104 20105 { bs3CpuInstr4_vcvtdq2pd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, XMM2, NOREG, PASS_s_aValues }, 20106 { bs3CpuInstr4_vcvtdq2pd_YMM1_FSxBX_icebp_c64, BS3_XCPT_NOT_AC, RM_MEM128, T_AVX_256, YMM1, FSxBX, NOREG, PASS_s_aValues }, 20107 20108 { bs3CpuInstr4_cvtdq2pd_XMM1_XMM1_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValues }, 20109 { bs3CpuInstr4_vcvtdq2pd_XMM1_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValues }, 20110 { bs3CpuInstr4_vcvtdq2pd_YMM1_XMM1_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, XMM1, NOREG, PASS_s_aValues }, 20111 20112 { bs3CpuInstr4_cvtdq2pd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM9, NOREG, PASS_s_aValues }, 20113 #ifdef TODO_CVTDQ2PD_M64_IEM /** @todo THIS FAILS ON IEM: unexpected #GP */ 20114 { bs3CpuInstr4_cvtdq2pd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM8, FSxBX, NOREG, PASS_s_aValues }, 20115 #endif /* TODO_CVTDQ2PD_M64_IEM */ 20116 20117 { bs3CpuInstr4_vcvtdq2pd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM9, NOREG, PASS_s_aValues }, 20118 { bs3CpuInstr4_vcvtdq2pd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM8, FSxBX, NOREG, PASS_s_aValues }, 20119 20120 { bs3CpuInstr4_vcvtdq2pd_YMM8_XMM9_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, XMM9, NOREG, PASS_s_aValues }, 20121 { bs3CpuInstr4_vcvtdq2pd_YMM8_FSxBX_icebp_c64, BS3_XCPT_NOT_AC, RM_MEM128, T_AVX_128, YMM8, FSxBX, NOREG, PASS_s_aValues }, 20122 20123 { bs3CpuInstr4_cvtdq2pd_XMM8_XMM8_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM8, NOREG, PASS_s_aValues }, 20124 { bs3CpuInstr4_vcvtdq2pd_XMM8_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM8, NOREG, PASS_s_aValues }, 20125 { bs3CpuInstr4_vcvtdq2pd_YMM8_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, XMM8, NOREG, PASS_s_aValues }, 20126 }; 20127 20128 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 20129 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 20130 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 20131 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 20132 } 20133 20134 20135 /* 20136 * CVTPD2DQ. 20137 */ 20138 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_cvtpd2dq(uint8_t bMode) 20139 { 20140 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesX[] = 20141 { 20142 /* 20143 * Zero. 20144 */ 20145 /* 0*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20146 { /* src xmm */ { FP64_0(0), FP64_0(0) } }, 20147 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT_C(0) } }, 20148 /*mxcsr:in */ 0, 20149 /*128:out */ 0, 20150 /*256:out */ -1 }, 20151 /* 20152 * Infinity. 20153 */ 20154 /* 1*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20155 { /* src xmm */ { FP64_INF(1), FP64_INF(0) } }, 20156 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT_C(0) } }, 20157 /*mxcsr:in */ 0, 20158 /*128:out */ X86_MXCSR_IE, 20159 /*256:out */ -1 }, 20160 /* 20161 * Normals & Precision. 20162 */ 20163 /* 2*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20164 { /* src xmm */ { FP64_V(0,0xe240000000000,0x40f), FP64_V(1,0xe240000000000,0x40f) } }, 20165 /*123456*/ /*-123456*/ 20166 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT_C(0) } }, 20167 /*mxcsr:in */ 0, 20168 /*128:out */ 0, 20169 /*256:out */ -1 }, 20170 { { /* unused */ { FP64_ROW_UNUSED } }, 20171 { /* src xmm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f) } }, 20172 /*123456.9*/ /*-123456.9*/ 20173 { /* => xmm */ { FP64_INT32_C(123457, -123457), FP64_INT_C(0) } }, 20174 /*mxcsr:in */ 0, 20175 /*128:out */ X86_MXCSR_PE, 20176 /*256:out */ -1 }, 20177 { { /* unused */ { FP64_ROW_UNUSED } }, 20178 { /* src xmm */ { FP64_V(1,0xccccccccccccd,0x3fe), FP64_V(0,0xccccccccccccd,0x3fe) } }, 20179 /*-0.9*/ /*0.9*/ 20180 { /* => xmm */ { FP64_INT32_C(-1, 1), FP64_INT_C(0) } }, 20181 /*mxcsr:in */ X86_MXCSR_FZ, 20182 /*128:out */ X86_MXCSR_PE | X86_MXCSR_FZ, 20183 /*256:out */ -1 }, 20184 20185 { { /* unused */ { FP64_ROW_UNUSED } }, 20186 { /* src xmm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f) } }, 20187 /*123456.9*/ /*-123456.9*/ 20188 { /* => xmm */ { FP64_INT32_C(123456, -123457), FP64_INT_C(0) } }, 20189 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 20190 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 20191 /*256:out */ -1 }, 20192 { { /* unused */ { FP64_ROW_UNUSED } }, 20193 { /* src xmm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f) } }, 20194 /*123456.9*/ /*-123456.9*/ 20195 { /* => xmm */ { FP64_INT32_C(123457, -123456), FP64_INT_C(0) } }, 20196 /*mxcsr:in */ X86_MXCSR_RC_UP, 20197 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP, 20198 /*256:out */ -1 }, 20199 { { /* unused */ { FP64_ROW_UNUSED } }, 20200 { /* src xmm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f) } }, 20201 /*123456.9*/ /*-123456.9*/ 20202 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT_C(0) } }, 20203 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 20204 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 20205 /*256:out */ -1 }, 20206 /* 20207 * Denormals. 20208 */ 20209 /* 8*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20210 { /* src xmm */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(1) } }, 20211 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT_C(0) } }, 20212 /*mxcsr:in */ 0, 20213 /*128:out */ X86_MXCSR_PE, 20214 /*256:out */ -1 }, 20215 { { /* unused */ { FP64_ROW_UNUSED } }, 20216 { /* src xmm */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(1) } }, 20217 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT_C(0) } }, 20218 /*mxcsr:in */ X86_MXCSR_DAZ, 20219 /*128:out */ X86_MXCSR_DAZ, 20220 /*256:out */ -1 }, 20221 /* 20222 * Overflow (Underflow not possible). 20223 */ 20224 /*10*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20225 { /* src xmm */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 20226 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT_C(0) } }, 20227 /*mxcsr:in */ 0, 20228 /*128:out */ X86_MXCSR_IE, 20229 /*256:out */ -1 }, 20230 { { /* unused */ { FP64_ROW_UNUSED } }, 20231 { /* src xmm */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, 20232 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT_C(0) } }, 20233 /*mxcsr:in */ 0, 20234 /*128:out */ X86_MXCSR_IE, 20235 /*256:out */ -1 }, 20236 /* 20237 * Invalids. 20238 */ 20239 /*12*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20240 { /* src xmm */ { FP64_QNAN(0), FP64_QNAN(1) } }, 20241 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT_C(0) } }, 20242 /*mxcsr:in */ 0, 20243 /*128:out */ X86_MXCSR_IE, 20244 /*256:out */ -1 }, 20245 { { /* unused */ { FP64_ROW_UNUSED } }, 20246 { /* src xmm */ { FP64_SNAN(1), FP64_SNAN(0) } }, 20247 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT_C(0) } }, 20248 /*mxcsr:in */ 0, 20249 /*128:out */ X86_MXCSR_IE, 20250 /*256:out */ -1 }, 20251 }; 20252 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesY[] = 20253 { 20254 /* 20255 * Zero. 20256 */ 20257 /* 0*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20258 { /* src ymm */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 20259 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT32_C(0, 0) } }, 20260 /*mxcsr:in */ 0, 20261 /*128:out */ 0, 20262 /*256:out */ 0 }, 20263 /* 20264 * Infinity. 20265 */ 20266 /* 1*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20267 { /* src ymm */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } }, 20268 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT32_INDEFx2 } }, 20269 /*mxcsr:in */ 0, 20270 /*128:out */ X86_MXCSR_IE, 20271 /*256:out */ X86_MXCSR_IE }, 20272 /* 20273 * Normals & Precision. 20274 */ 20275 /* 2*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20276 { /* src ymm */ { FP64_V(0,0xe240000000000,0x40f), FP64_V(1,0xe240000000000,0x40f), FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f) } }, 20277 /*123456*/ /*-123456*/ /*123456.9*/ /*-123456.9*/ 20278 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT32_C(123457, -123457) } }, 20279 /*mxcsr:in */ 0, 20280 /*128:out */ 0, 20281 /*256:out */ X86_MXCSR_PE }, 20282 { { /* unused */ { FP64_ROW_UNUSED } }, 20283 { /* src ymm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f), FP64_V(1,0xccccccccccccd,0x3fe), FP64_V(0,0xccccccccccccd,0x3fe) } }, 20284 /*123456.9*/ /*-123456.9*/ /*-0.9*/ /*0.9*/ 20285 { /* => xmm */ { FP64_INT32_C(123457, -123457), FP64_INT32_C(-1, 1) } }, 20286 /*mxcsr:in */ X86_MXCSR_FZ, 20287 /*128:out */ X86_MXCSR_PE | X86_MXCSR_FZ, 20288 /*256:out */ X86_MXCSR_PE | X86_MXCSR_FZ }, 20289 { { /* unused */ { FP64_ROW_UNUSED } }, 20290 { /* src ymm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f), FP64_V(1,0xccccccccccccd,0x3fe), FP64_V(0,0xccccccccccccd,0x3fe) } }, 20291 /*123456.9*/ /*-123456.9*/ /*-0.9*/ /*0.9*/ 20292 { /* => xmm */ { FP64_INT32_C(123456, -123457), FP64_INT32_C(-1, 0) } }, 20293 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 20294 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 20295 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN }, 20296 { { /* unused */ { FP64_ROW_UNUSED } }, 20297 { /* src ymm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f), FP64_V(1,0xccccccccccccd,0x3fe), FP64_V(0,0xccccccccccccd,0x3fe) } }, 20298 /*123456.9*/ /*-123456.9*/ /*-0.9*/ /*0.9*/ 20299 { /* => xmm */ { FP64_INT32_C(123457, -123456), FP64_INT32_C(0, 1) } }, 20300 /*mxcsr:in */ X86_MXCSR_RC_UP, 20301 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP, 20302 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP }, 20303 { { /* unused */ { FP64_ROW_UNUSED } }, 20304 { /* src ymm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f), FP64_V(1,0xccccccccccccd,0x3fe), FP64_V(0,0xccccccccccccd,0x3fe) } }, 20305 /*123456.9*/ /*-123456.9*/ /*-0.9*/ /*0.9*/ 20306 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT32_C(0, 0) } }, 20307 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 20308 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 20309 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO }, 20310 /* 20311 * Denormals. 20312 */ 20313 /* 7*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20314 { /* src ymm */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1) } }, 20315 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT32_C(0, 0) } }, 20316 /*mxcsr:in */ 0, 20317 /*128:out */ X86_MXCSR_PE, 20318 /*256:out */ X86_MXCSR_PE }, 20319 { { /* unused */ { FP64_ROW_UNUSED } }, 20320 { /* src ymm */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1) } }, 20321 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT32_C(0, 0) } }, 20322 /*mxcsr:in */ X86_MXCSR_DAZ, 20323 /*128:out */ X86_MXCSR_DAZ, 20324 /*256:out */ X86_MXCSR_DAZ }, 20325 /* 20326 * Overflow (Underflow not possible). 20327 */ 20328 /* 9*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20329 { /* src ymm */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, 20330 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT32_INDEFx2 } }, 20331 /*mxcsr:in */ 0, 20332 /*128:out */ X86_MXCSR_IE, 20333 /*256:out */ X86_MXCSR_IE }, 20334 /* 20335 * Invalids. 20336 */ 20337 /*10*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20338 { /* src ymm */ { FP64_QNAN(0), FP64_QNAN(1), FP64_SNAN(1), FP64_SNAN(0) } }, 20339 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT32_INDEFx2 } }, 20340 /*mxcsr:in */ 0, 20341 /*128:out */ X86_MXCSR_IE, 20342 /*256:out */ X86_MXCSR_IE }, 20343 }; 20344 20345 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 20346 { 20347 { bs3CpuInstr4_cvtpd2dq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20348 { bs3CpuInstr4_cvtpd2dq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, 20349 20350 { bs3CpuInstr4_vcvtpd2dq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20351 { bs3CpuInstr4_vcvtpd2dq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, 20352 20353 { bs3CpuInstr4_vcvtpd2dq_XMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, XMM1, YMM2, NOREG, PASS_s_aValuesY }, 20354 { bs3CpuInstr4_vcvtpd2dq_XMM1_FSxBX_Y_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, XMM1, FSxBX, NOREG, PASS_s_aValuesY }, 20355 20356 { bs3CpuInstr4_cvtpd2dq_XMM1_XMM1_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20357 { bs3CpuInstr4_vcvtpd2dq_XMM1_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20358 { bs3CpuInstr4_vcvtpd2dq_XMM1_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, XMM1, YMM1, NOREG, PASS_s_aValuesY }, 20359 }; 20360 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 20361 { 20362 { bs3CpuInstr4_cvtpd2dq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20363 { bs3CpuInstr4_cvtpd2dq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, 20364 20365 { bs3CpuInstr4_vcvtpd2dq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20366 { bs3CpuInstr4_vcvtpd2dq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, 20367 20368 { bs3CpuInstr4_vcvtpd2dq_XMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, XMM1, YMM2, NOREG, PASS_s_aValuesY }, 20369 { bs3CpuInstr4_vcvtpd2dq_XMM1_FSxBX_Y_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, XMM1, FSxBX, NOREG, PASS_s_aValuesY }, 20370 20371 { bs3CpuInstr4_cvtpd2dq_XMM1_XMM1_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20372 { bs3CpuInstr4_vcvtpd2dq_XMM1_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20373 { bs3CpuInstr4_vcvtpd2dq_XMM1_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, XMM1, YMM1, NOREG, PASS_s_aValuesY }, 20374 }; 20375 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 20376 { 20377 { bs3CpuInstr4_cvtpd2dq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20378 { bs3CpuInstr4_cvtpd2dq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, 20379 20380 { bs3CpuInstr4_vcvtpd2dq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20381 { bs3CpuInstr4_vcvtpd2dq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, 20382 20383 { bs3CpuInstr4_vcvtpd2dq_XMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, XMM1, YMM2, NOREG, PASS_s_aValuesY }, 20384 { bs3CpuInstr4_vcvtpd2dq_XMM1_FSxBX_Y_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, XMM1, FSxBX, NOREG, PASS_s_aValuesY }, 20385 20386 { bs3CpuInstr4_cvtpd2dq_XMM1_XMM1_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20387 { bs3CpuInstr4_vcvtpd2dq_XMM1_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20388 { bs3CpuInstr4_vcvtpd2dq_XMM1_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, XMM1, YMM1, NOREG, PASS_s_aValuesY }, 20389 20390 { bs3CpuInstr4_cvtpd2dq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM9, NOREG, PASS_s_aValuesX }, 20391 { bs3CpuInstr4_cvtpd2dq_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM8, FSxBX, NOREG, PASS_s_aValuesX }, 20392 20393 { bs3CpuInstr4_vcvtpd2dq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM9, NOREG, PASS_s_aValuesX }, 20394 { bs3CpuInstr4_vcvtpd2dq_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM8, FSxBX, NOREG, PASS_s_aValuesX }, 20395 20396 { bs3CpuInstr4_vcvtpd2dq_XMM8_YMM9_icebp_c64, 255, RM_REG, T_AVX_256, XMM8, YMM9, NOREG, PASS_s_aValuesY }, 20397 { bs3CpuInstr4_vcvtpd2dq_XMM8_FSxBX_Y_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, XMM8, FSxBX, NOREG, PASS_s_aValuesY }, 20398 20399 { bs3CpuInstr4_cvtpd2dq_XMM8_XMM8_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM8, NOREG, PASS_s_aValuesX }, 20400 { bs3CpuInstr4_vcvtpd2dq_XMM8_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM8, NOREG, PASS_s_aValuesX }, 20401 { bs3CpuInstr4_vcvtpd2dq_XMM8_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, XMM8, YMM8, NOREG, PASS_s_aValuesY }, 20402 }; 20403 20404 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 20405 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 20406 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 20407 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); 20408 } 20409 20410 20411 /* 20412 * CVTTPD2DQ. 20413 */ 20414 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_cvttpd2dq(uint8_t bMode) 20415 { 20416 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesX[] = 20417 { 20418 /* 20419 * Zero. 20420 */ 20421 /* 0*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20422 { /* src xmm */ { FP64_0(0), FP64_0(0) } }, 20423 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT_C(0) } }, 20424 /*mxcsr:in */ 0, 20425 /*128:out */ 0, 20426 /*256:out */ -1 }, 20427 /* 20428 * Infinity. 20429 */ 20430 /* 1*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20431 { /* src xmm */ { FP64_INF(1), FP64_INF(0) } }, 20432 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT_C(0) } }, 20433 /*mxcsr:in */ 0, 20434 /*128:out */ X86_MXCSR_IE, 20435 /*256:out */ -1 }, 20436 /* 20437 * Normals & Precision. 20438 */ 20439 /* 2*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20440 { /* src xmm */ { FP64_V(0,0xe240000000000,0x40f), FP64_V(1,0xe240000000000,0x40f) } }, 20441 /*123456*/ /*-123456*/ 20442 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT_C(0) } }, 20443 /*mxcsr:in */ 0, 20444 /*128:out */ 0, 20445 /*256:out */ -1 }, 20446 { { /* unused */ { FP64_ROW_UNUSED } }, 20447 { /* src xmm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f) } }, 20448 /*123456.9*/ /*-123456.9*/ 20449 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT_C(0) } }, 20450 /*mxcsr:in */ 0, 20451 /*128:out */ X86_MXCSR_PE, 20452 /*256:out */ -1 }, 20453 { { /* unused */ { FP64_ROW_UNUSED } }, 20454 { /* src xmm */ { FP64_V(1,0xccccccccccccd,0x3fe), FP64_V(0,0xccccccccccccd,0x3fe) } }, 20455 /*-0.9*/ /*0.9*/ 20456 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT_C(0) } }, 20457 /*mxcsr:in */ X86_MXCSR_FZ, 20458 /*128:out */ X86_MXCSR_PE | X86_MXCSR_FZ, 20459 /*256:out */ -1 }, 20460 20461 { { /* unused */ { FP64_ROW_UNUSED } }, 20462 { /* src xmm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f) } }, 20463 /*123456.9*/ /*-123456.9*/ 20464 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT_C(0) } }, 20465 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 20466 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 20467 /*256:out */ -1 }, 20468 { { /* unused */ { FP64_ROW_UNUSED } }, 20469 { /* src xmm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f) } }, 20470 /*123456.9*/ /*-123456.9*/ 20471 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT_C(0) } }, 20472 /*mxcsr:in */ X86_MXCSR_RC_UP, 20473 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP, 20474 /*256:out */ -1 }, 20475 { { /* unused */ { FP64_ROW_UNUSED } }, 20476 { /* src xmm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f) } }, 20477 /*123456.9*/ /*-123456.9*/ 20478 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT_C(0) } }, 20479 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 20480 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 20481 /*256:out */ -1 }, 20482 /* 20483 * Denormals. 20484 */ 20485 /* 8*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20486 { /* src xmm */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(1) } }, 20487 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT_C(0) } }, 20488 /*mxcsr:in */ 0, 20489 /*128:out */ X86_MXCSR_PE, 20490 /*256:out */ -1 }, 20491 { { /* unused */ { FP64_ROW_UNUSED } }, 20492 { /* src xmm */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(1) } }, 20493 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT_C(0) } }, 20494 /*mxcsr:in */ X86_MXCSR_DAZ, 20495 /*128:out */ X86_MXCSR_DAZ, 20496 /*256:out */ -1 }, 20497 /* 20498 * Overflow (Underflow not possible). 20499 */ 20500 /*10*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20501 { /* src xmm */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 20502 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT_C(0) } }, 20503 /*mxcsr:in */ 0, 20504 /*128:out */ X86_MXCSR_IE, 20505 /*256:out */ -1 }, 20506 { { /* unused */ { FP64_ROW_UNUSED } }, 20507 { /* src xmm */ { FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, 20508 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT_C(0) } }, 20509 /*mxcsr:in */ 0, 20510 /*128:out */ X86_MXCSR_IE, 20511 /*256:out */ -1 }, 20512 /* 20513 * Invalids. 20514 */ 20515 /*12*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20516 { /* src xmm */ { FP64_QNAN(0), FP64_QNAN(1) } }, 20517 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT_C(0) } }, 20518 /*mxcsr:in */ 0, 20519 /*128:out */ X86_MXCSR_IE, 20520 /*256:out */ -1 }, 20521 { { /* unused */ { FP64_ROW_UNUSED } }, 20522 { /* src xmm */ { FP64_SNAN(1), FP64_SNAN(0) } }, 20523 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT_C(0) } }, 20524 /*mxcsr:in */ 0, 20525 /*128:out */ X86_MXCSR_IE, 20526 /*256:out */ -1 }, 20527 }; 20528 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesY[] = 20529 { 20530 /* 20531 * Zero. 20532 */ 20533 /* 0*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20534 { /* src ymm */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } }, 20535 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT32_C(0, 0) } }, 20536 /*mxcsr:in */ 0, 20537 /*128:out */ 0, 20538 /*256:out */ 0 }, 20539 /* 20540 * Infinity. 20541 */ 20542 /* 1*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20543 { /* src ymm */ { FP64_INF(1), FP64_INF(0), FP64_INF(0), FP64_INF(1) } }, 20544 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT32_INDEFx2 } }, 20545 /*mxcsr:in */ 0, 20546 /*128:out */ X86_MXCSR_IE, 20547 /*256:out */ X86_MXCSR_IE }, 20548 /* 20549 * Normals & Precision. 20550 */ 20551 /* 2*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20552 { /* src ymm */ { FP64_V(0,0xe240000000000,0x40f), FP64_V(1,0xe240000000000,0x40f), FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f) } }, 20553 /*123456*/ /*-123456*/ /*123456.9*/ /*-123456.9*/ 20554 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT32_C(123456, -123456) } }, 20555 /*mxcsr:in */ 0, 20556 /*128:out */ 0, 20557 /*256:out */ X86_MXCSR_PE }, 20558 { { /* unused */ { FP64_ROW_UNUSED } }, 20559 { /* src ymm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f), FP64_V(1,0xccccccccccccd,0x3fe), FP64_V(0,0xccccccccccccd,0x3fe) } }, 20560 /*123456.9*/ /*-123456.9*/ /*-0.9*/ /*0.9*/ 20561 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT32_C(0, 0) } }, 20562 /*mxcsr:in */ X86_MXCSR_FZ, 20563 /*128:out */ X86_MXCSR_PE | X86_MXCSR_FZ, 20564 /*256:out */ X86_MXCSR_PE | X86_MXCSR_FZ }, 20565 { { /* unused */ { FP64_ROW_UNUSED } }, 20566 { /* src ymm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f), FP64_V(1,0xccccccccccccd,0x3fe), FP64_V(0,0xccccccccccccd,0x3fe) } }, 20567 /*123456.9*/ /*-123456.9*/ /*-0.9*/ /*0.9*/ 20568 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT32_C(0, 0) } }, 20569 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 20570 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 20571 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN }, 20572 { { /* unused */ { FP64_ROW_UNUSED } }, 20573 { /* src ymm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f), FP64_V(1,0xccccccccccccd,0x3fe), FP64_V(0,0xccccccccccccd,0x3fe) } }, 20574 /*123456.9*/ /*-123456.9*/ /*-0.9*/ /*0.9*/ 20575 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT32_C(0, 0) } }, 20576 /*mxcsr:in */ X86_MXCSR_RC_UP, 20577 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP, 20578 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP }, 20579 { { /* unused */ { FP64_ROW_UNUSED } }, 20580 { /* src ymm */ { FP64_V(0,0xe240e66666666,0x40f), FP64_V(1,0xe240e66666666,0x40f), FP64_V(1,0xccccccccccccd,0x3fe), FP64_V(0,0xccccccccccccd,0x3fe) } }, 20581 /*123456.9*/ /*-123456.9*/ /*-0.9*/ /*0.9*/ 20582 { /* => xmm */ { FP64_INT32_C(123456, -123456), FP64_INT32_C(0, 0) } }, 20583 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 20584 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 20585 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO }, 20586 /* 20587 * Denormals. 20588 */ 20589 /* 7*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20590 { /* src ymm */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1) } }, 20591 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT32_C(0, 0) } }, 20592 /*mxcsr:in */ 0, 20593 /*128:out */ X86_MXCSR_PE, 20594 /*256:out */ X86_MXCSR_PE }, 20595 { { /* unused */ { FP64_ROW_UNUSED } }, 20596 { /* src ymm */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_MIN(0), FP64_DENORM_MAX(1) } }, 20597 { /* => xmm */ { FP64_INT32_C(0, 0), FP64_INT32_C(0, 0) } }, 20598 /*mxcsr:in */ X86_MXCSR_DAZ, 20599 /*128:out */ X86_MXCSR_DAZ, 20600 /*256:out */ X86_MXCSR_DAZ }, 20601 /* 20602 * Overflow (Underflow not possible). 20603 */ 20604 /* 9*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20605 { /* src ymm */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1), FP64_NORM_SAFE_INT_MAX(1), FP64_NORM_SAFE_INT_MAX(0) } }, 20606 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT32_INDEFx2 } }, 20607 /*mxcsr:in */ 0, 20608 /*128:out */ X86_MXCSR_IE, 20609 /*256:out */ X86_MXCSR_IE }, 20610 /* 20611 * Invalids. 20612 */ 20613 /*10*/{ { /* unused */ { FP64_ROW_UNUSED } }, 20614 { /* src ymm */ { FP64_QNAN(0), FP64_QNAN(1), FP64_SNAN(1), FP64_SNAN(0) } }, 20615 { /* => xmm */ { FP64_INT32_INDEFx2, FP64_INT32_INDEFx2 } }, 20616 /*mxcsr:in */ 0, 20617 /*128:out */ X86_MXCSR_IE, 20618 /*256:out */ X86_MXCSR_IE }, 20619 }; 20620 20621 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 20622 { 20623 { bs3CpuInstr4_cvttpd2dq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20624 { bs3CpuInstr4_cvttpd2dq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, 20625 20626 { bs3CpuInstr4_vcvttpd2dq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20627 { bs3CpuInstr4_vcvttpd2dq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, // need to tag with RM_MEM_16? 20628 20629 { bs3CpuInstr4_vcvttpd2dq_XMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, XMM1, YMM2, NOREG, PASS_s_aValuesY }, 20630 { bs3CpuInstr4_vcvttpd2dq_XMM1_FSxBX_Y_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, XMM1, FSxBX, NOREG, PASS_s_aValuesY }, // need to tag with RM_MEM_32? 20631 20632 { bs3CpuInstr4_cvttpd2dq_XMM1_XMM1_icebp_c16, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20633 { bs3CpuInstr4_vcvttpd2dq_XMM1_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20634 { bs3CpuInstr4_vcvttpd2dq_XMM1_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, XMM1, YMM1, NOREG, PASS_s_aValuesY }, 20635 }; 20636 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 20637 { 20638 { bs3CpuInstr4_cvttpd2dq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20639 { bs3CpuInstr4_cvttpd2dq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, 20640 20641 { bs3CpuInstr4_vcvttpd2dq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20642 { bs3CpuInstr4_vcvttpd2dq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, // need to tag with RM_MEM_16? 20643 20644 { bs3CpuInstr4_vcvttpd2dq_XMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, XMM1, YMM2, NOREG, PASS_s_aValuesY }, 20645 { bs3CpuInstr4_vcvttpd2dq_XMM1_FSxBX_Y_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, XMM1, FSxBX, NOREG, PASS_s_aValuesY }, // need to tag with RM_MEM_32? 20646 20647 { bs3CpuInstr4_cvttpd2dq_XMM1_XMM1_icebp_c32, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20648 { bs3CpuInstr4_vcvttpd2dq_XMM1_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20649 { bs3CpuInstr4_vcvttpd2dq_XMM1_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, XMM1, YMM1, NOREG, PASS_s_aValuesY }, 20650 }; 20651 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 20652 { 20653 { bs3CpuInstr4_cvttpd2dq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20654 { bs3CpuInstr4_cvttpd2dq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, 20655 20656 { bs3CpuInstr4_vcvttpd2dq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_s_aValuesX }, 20657 { bs3CpuInstr4_vcvttpd2dq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM1, FSxBX, NOREG, PASS_s_aValuesX }, // need to tag with RM_MEM_16? 20658 20659 { bs3CpuInstr4_vcvttpd2dq_XMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, XMM1, YMM2, NOREG, PASS_s_aValuesY }, 20660 { bs3CpuInstr4_vcvttpd2dq_XMM1_FSxBX_Y_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, XMM1, FSxBX, NOREG, PASS_s_aValuesY }, // need to tag with RM_MEM_32? 20661 20662 { bs3CpuInstr4_cvttpd2dq_XMM1_XMM1_icebp_c64, 255, RM_REG, T_SSE2, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20663 { bs3CpuInstr4_vcvttpd2dq_XMM1_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_s_aValuesX }, 20664 { bs3CpuInstr4_vcvttpd2dq_XMM1_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, XMM1, YMM1, NOREG, PASS_s_aValuesY }, 20665 20666 { bs3CpuInstr4_cvttpd2dq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM9, NOREG, PASS_s_aValuesX }, 20667 { bs3CpuInstr4_cvttpd2dq_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_SSE2, XMM8, FSxBX, NOREG, PASS_s_aValuesX }, 20668 20669 { bs3CpuInstr4_vcvttpd2dq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM9, NOREG, PASS_s_aValuesX }, 20670 { bs3CpuInstr4_vcvttpd2dq_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, XMM8, FSxBX, NOREG, PASS_s_aValuesX }, // need to tag with RM_MEM_16? 20671 20672 { bs3CpuInstr4_vcvttpd2dq_XMM8_YMM9_icebp_c64, 255, RM_REG, T_AVX_256, XMM8, YMM9, NOREG, PASS_s_aValuesY }, 20673 { bs3CpuInstr4_vcvttpd2dq_XMM8_FSxBX_Y_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, XMM8, FSxBX, NOREG, PASS_s_aValuesY }, // need to tag with RM_MEM_32? 20674 20675 { bs3CpuInstr4_cvttpd2dq_XMM8_XMM8_icebp_c64, 255, RM_REG, T_SSE2, XMM8, XMM8, NOREG, PASS_s_aValuesX }, 20676 { bs3CpuInstr4_vcvttpd2dq_XMM8_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM8, NOREG, PASS_s_aValuesX }, 20677 { bs3CpuInstr4_vcvttpd2dq_XMM8_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, YMM8, NOREG, PASS_s_aValuesY }, 20678 }; 20679 20680 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 20681 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 20682 return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 20683 g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2)); 19455 20684 } 19456 20685 … … 19525 20754 { "[v]cvtsd2si", bs3CpuInstr4_v_cvtsd2si, 0 }, 19526 20755 { "[v]cvttsd2si", bs3CpuInstr4_v_cvttsd2si, 0 }, 20756 { "[v]cvtdq2ps", bs3CpuInstr4_v_cvtdq2ps, 0 }, 20757 { "[v]cvtps2dq", bs3CpuInstr4_v_cvtps2dq, 0 }, 20758 { "[v]cvttps2dq", bs3CpuInstr4_v_cvttps2dq, 0 }, 20759 { "[v]cvtdq2pd", bs3CpuInstr4_v_cvtdq2pd, 0 }, 20760 { "[v]cvtpd2dq", bs3CpuInstr4_v_cvtpd2dq, 0 }, 20761 { "[v]cvttpd2dq", bs3CpuInstr4_v_cvttpd2dq, 0 }, 19527 20762 #endif 19528 20763 };
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