Changeset 106947 in vbox for trunk/src/VBox/ValidationKit
- Timestamp:
- Nov 12, 2024 5:32:50 AM (2 months ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-4-template.mac (modified) (1 diff)
-
bs3-cpu-instr-4.c32 (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
r106943 r106947 919 919 EMIT_INSTR_PLUS_ICEBP_C64 vdpps, YMM8, YMM8, YMM8, 0E1h 920 920 EMIT_INSTR_PLUS_ICEBP_C64 vdpps, YMM8, YMM8, FSxBX, 0E1h 921 922 ; 923 ;; dppd 924 ; 925 EMIT_INSTR_PLUS_ICEBP dppd, XMM1, XMM2, 000h 926 EMIT_INSTR_PLUS_ICEBP dppd, XMM1, XMM2, 0FFh 927 EMIT_INSTR_PLUS_ICEBP dppd, XMM1, XMM2, 022h 928 EMIT_INSTR_PLUS_ICEBP dppd, XMM1, FSxBX, 000h 929 EMIT_INSTR_PLUS_ICEBP dppd, XMM1, FSxBX, 0FFh 930 EMIT_INSTR_PLUS_ICEBP dppd, XMM1, FSxBX, 022h 931 EMIT_INSTR_PLUS_ICEBP_C64 dppd, XMM8, XMM9, 022h 932 EMIT_INSTR_PLUS_ICEBP_C64 dppd, XMM8, FSxBX, 022h 933 934 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM2, XMM3, 000h 935 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM2, XMM3, 0FFh 936 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM2, XMM3, 022h 937 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM2, FSxBX, 000h 938 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM2, FSxBX, 0FFh 939 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM2, FSxBX, 022h 940 EMIT_INSTR_PLUS_ICEBP_C64 vdppd, XMM8, XMM9, XMM10, 022h 941 EMIT_INSTR_PLUS_ICEBP_C64 vdppd, XMM8, XMM9, FSxBX, 022h 942 943 EMIT_INSTR_PLUS_ICEBP dppd, XMM1, XMM1, 022h 944 EMIT_INSTR_PLUS_ICEBP_C64 dppd, XMM8, XMM8, 022h 945 946 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM1, XMM1, 022h 947 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM2, XMM1, 022h 948 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM1, XMM2, 022h 949 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM2, XMM2, 022h 950 EMIT_INSTR_PLUS_ICEBP vdppd, XMM1, XMM1, FSxBX, 022h 951 EMIT_INSTR_PLUS_ICEBP_C64 vdppd, XMM8, XMM8, XMM8, 022h 952 EMIT_INSTR_PLUS_ICEBP_C64 vdppd, XMM8, XMM8, FSxBX, 022h 921 953 922 954 ; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106943 r106947 16446 16446 */ 16447 16447 }; 16448 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesE1[] = 16449 { 16450 /* 16451 * Zero. 16452 */ 16453 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 16454 { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 16455 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16456 /*mxcsr:in */ 0, 16457 /*128:out */ 0, 16458 /*256:out */ 0 }, 16459 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 16460 { /*src2 */ { FP32_1(0), FP32_1(1), FP32_2(0), FP32_2(1), FP32_NORM_V0(0), FP32_NORM_V0(1), FP32_RAND_V0(0), FP32_RAND_V0(1) } }, 16461 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16462 /*mxcsr:in */ 0, 16463 /*128:out */ 0, 16464 /*256:out */ 0 }, 16465 /* 16466 * Infinity. 16467 */ 16468 /* 2*/{ { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 16469 { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 16470 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16471 /*mxcsr:in */ 0, 16472 /*128:out */ 0, 16473 /*256:out */ 0 }, 16474 { { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 16475 { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } }, 16476 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16477 /*mxcsr:in */ 0, /* oo + -oo = IE */ 16478 /*128:out */ 0, 16479 /*256:out */ X86_MXCSR_IE }, 16480 { { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16481 { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } }, 16482 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16483 /*mxcsr:in */ 0, /* no IE: the oo * 0 dot-product is skipped */ 16484 /*128:out */ 0, 16485 /*256:out */ 0 }, 16486 { { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } }, 16487 { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } }, 16488 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16489 /*mxcsr:in */ 0, /* big * big = oo (OE); big * -big = -oo (OE) */ 16490 /*128:out */ X86_MXCSR_OE | X86_MXCSR_PE, 16491 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE }, 16492 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } }, 16493 { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, 16494 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) /* unused */ } }, 16495 /*mxcsr:in */ 0, /* big * big = oo (OE); big * -big = -oo (OE) */ 16496 /*128:out */ 0, /* OE hits in multiply step, before IE in addition step */ 16497 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED }, 16498 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1) } }, 16499 { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } }, 16500 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16501 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /* big * big = oo (OE) is skipped; big * -big = -oo (OE); -oo + -oo = -oo (!IE) */ 16502 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM, 16503 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED | BS3_MXCSR_PM_FIXED }, 16504 /* 16505 * Normals, Precision, Overflow. 16506 */ 16507 /* 8*/{ { /*src1 */ { FP32_1(0), FP32_1(1), FP32_2(0), FP32_2(1), FP32_1(0), FP32_1(1), FP32_2(0), FP32_2(1) } }, 16508 { /*src2 */ { FP32_1(0), FP32_1(1), FP32_2(0), FP32_2(1), FP32_1(1), FP32_1(0), FP32_2(0), FP32_2(0) } }, 16509 { /* => */ { FP32_V(0,0x100000,0x82), FP32_0(0), FP32_0(0), FP32_0(0), FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16510 /*9.0*/ 16511 /*mxcsr:in */ 0, 16512 /*128:out */ 0, 16513 /*256:out */ 0 }, 16514 { { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } }, 16515 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } }, 16516 { /* => */ { FP32_ROW_UNUSED } }, 16517 /*mxcsr:in */ 0, 16518 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 16519 /*256:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED }, 16520 { { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1) } }, 16521 { /*src2 */ { FP32_2(0), FP32_2(1), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(1), FP32_2(0) } }, 16522 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16523 /*mxcsr:in */ X86_MXCSR_OM, 16524 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 16525 /*256:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED }, 16526 /** @todo more normals; rounding controls affecting different steps of the calculation */ 16527 /* 16528 * Denormals, Underflow. 16529 */ 16530 /*11*/{ { /*src1 */ { FP32_DENORM_V0(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_V3(1), FP32_DENORM_V4(0), FP32_DENORM_V5(1), FP32_DENORM_V6(1), FP32_DENORM_V7(0) } }, 16531 { /*src2 */ { FP32_DENORM_V4(0), FP32_DENORM_V5(0), FP32_DENORM_V6(1), FP32_DENORM_V7(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_V1(0), FP32_DENORM_V0(0) } }, 16532 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16533 /*mxcsr:in */ 0, 16534 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED, 16535 /*256:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE }, 16536 { { /*src1 */ { FP32_DENORM_V0(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_V3(1), FP32_DENORM_V4(0), FP32_DENORM_V5(1), FP32_DENORM_V6(1), FP32_DENORM_V7(0) } }, 16537 { /*src2 */ { FP32_DENORM_V4(0), FP32_DENORM_V5(0), FP32_DENORM_V6(1), FP32_DENORM_V7(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_V1(0), FP32_DENORM_V0(0) } }, 16538 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16539 /*mxcsr:in */ X86_MXCSR_UM, 16540 /*128:out */ X86_MXCSR_UM | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 16541 /*256:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE }, 16542 { { /*src1 */ { FP32_DENORM_V0(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_V3(1), FP32_DENORM_V4(0), FP32_DENORM_V5(1), FP32_DENORM_V6(1), FP32_DENORM_V7(0) } }, 16543 { /*src2 */ { FP32_DENORM_V4(0), FP32_DENORM_V5(0), FP32_DENORM_V6(1), FP32_DENORM_V7(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_V1(0), FP32_DENORM_V0(0) } }, 16544 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16545 /*mxcsr:in */ X86_MXCSR_DM, 16546 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED, 16547 /*256:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE }, 16548 { { /*src1 */ { FP32_DENORM_V0(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_V3(1), FP32_DENORM_V4(0), FP32_DENORM_V5(1), FP32_DENORM_V6(1), FP32_DENORM_V7(0) } }, 16549 { /*src2 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_DENORM_V6(1), FP32_DENORM_V7(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_V1(0), FP32_DENORM_V0(0) } }, 16550 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16551 /*mxcsr:in */ X86_MXCSR_DAZ, 16552 /*128:out */ X86_MXCSR_DAZ, 16553 /*256:out */ X86_MXCSR_DAZ }, 16554 #define TINY_MAXx6 FP32_V(0,0x3ffffe,3) /* 6 * FP32_DENORM_MAX(0) */ 16555 #define TINY_MINx6 FP32_V(0,6,0) /* 6 * FP32_DENORM_MIN(0) */ 16556 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0) } }, 16557 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } }, 16558 { /* => */ { TINY_MAXx6, FP32_0(0), FP32_0(0), FP32_0(0) /* unused */ } }, 16559 /*mxcsr:in */ 0, 16560 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE, 16561 /*256:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED }, 16562 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0) } }, 16563 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } }, 16564 { /* => */ { TINY_MAXx6, FP32_0(0), FP32_0(0), FP32_0(0) /* unused */ } }, 16565 /*mxcsr:in */ 0, 16566 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE, 16567 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED }, 16568 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0) } }, 16569 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } }, 16570 { /* => */ { TINY_MAXx6, FP32_0(0), FP32_0(0), FP32_0(0), TINY_MINx6, FP32_0(0), FP32_0(0), FP32_0(0) } }, 16571 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM, 16572 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE, 16573 /*256:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | X86_MXCSR_PE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED }, 16574 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0) } }, 16575 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } }, 16576 { /* => */ { TINY_MAXx6, FP32_0(0), FP32_0(0), FP32_0(0), TINY_MINx6, FP32_0(0), FP32_0(0), FP32_0(0) } }, 16577 /*mxcsr:in */ X86_MXCSR_FZ, 16578 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_PE, 16579 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED }, 16580 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0) } }, 16581 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } }, 16582 { /* => */ { TINY_MAXx6, FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16583 /*mxcsr:in */ X86_MXCSR_UM | X86_MXCSR_FZ, 16584 /*128:out */ X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_PE, 16585 /*256:out */ X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED }, 16586 #undef TINY_MAXx6 16587 #undef TINY_MINx6 16588 /* 16589 * Invalids. 16590 */ 16591 /*20*/{ { /*src1 */ { FP32_QNAN_V5(0), FP32_QNAN_V2(1), FP32_QNAN_V0(1), FP32_QNAN_V0(0), FP32_QNAN_V3(1), FP32_QNAN_V7(0), FP32_QNAN(0), FP32_QNAN_V4(1) } }, 16592 { /*src2 */ { FP32_QNAN(1), FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(1), FP32_QNAN_V7(1), FP32_QNAN_V6(1), FP32_QNAN_MAX(1) } }, 16593 { /* => */ { FP32_QNAN_V1(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN_V7(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16594 /*mxcsr:in */ 0, /* output swaps src2 input pairs?!? -- result from i7-10700 */ 16595 /*128:out */ 0, 16596 /*256:out */ 0 }, 16597 { { /*src1 */ { FP32_SNAN_V5(0), FP32_SNAN_V2(1), FP32_SNAN_V0(1), FP32_SNAN_V0(0), FP32_SNAN_V3(1), FP32_SNAN_V7(0), FP32_SNAN(0), FP32_SNAN_V4(1) } }, 16598 { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V1(0), FP32_SNAN_MAX(0), FP32_SNAN_V6(0), FP32_SNAN_V5(1), FP32_SNAN_V7(1), FP32_SNAN_V6(1), FP32_SNAN_MAX(1) } }, 16599 { /* => */ { FP32_QNAN_V1(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN_V7(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16600 /*mxcsr:in */ 0, /* output has swapped src2 input pairs?!? -- result from i7-10700 */ 16601 /*128:out */ X86_MXCSR_IE, 16602 /*256:out */ X86_MXCSR_IE }, 16603 { { /*src1 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0) } }, 16604 { /*src2 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_QNAN_MAX(1) } }, 16605 { /* => */ { FP32_V(0,0x400000,0x80), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16606 /*3.0*/ 16607 /*mxcsr:in */ 0, /* output grabs the one NaN -- result from i7-10700 */ 16608 /*128:out */ 0, 16609 /*256:out */ 0 }, 16610 { { /*src1 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0) } }, 16611 { /*src2 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_QNAN_MAX(1), FP32_1(0), FP32_1(0), FP32_1(0) } }, 16612 { /* => */ { FP32_V(0,0x400000,0x80), FP32_0(0), FP32_0(0), FP32_0(0), FP32_V(0,0x400000,0x80), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16613 /*3.0*/ /*3.0*/ 16614 /*mxcsr:in */ 0, /* the NaN isn't in the specified set of calculations */ 16615 /*128:out */ 0, 16616 /*256:out */ 0 }, 16617 { { /*src1 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_QNAN_MAX(1), FP32_1(0) } }, 16618 { /*src2 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0) } }, 16619 { /* => */ { FP32_V(0,0x400000,0x80), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16620 /*3.0*/ 16621 /*mxcsr:in */ 0, /* output grabs the one NaN -- result from i7-10700 */ 16622 /*128:out */ 0, 16623 /*256:out */ 0 }, 16624 { { /*src1 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0) } }, 16625 { /*src2 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_SNAN_MAX(1) } }, 16626 { /* => */ { FP32_V(0,0x400000,0x80), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16627 /*3.0*/ 16628 /*mxcsr:in */ 0, /* output grabs the one NaN -- result from i7-10700 */ 16629 /*128:out */ 0, 16630 /*256:out */ X86_MXCSR_IE }, 16631 }; 16448 16632 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesFF[] = 16449 16633 { … … 16548 16732 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE, 16549 16733 /*256:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE }, 16734 { { /*src1 */ { FP32_DENORM_V0(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_V3(1), FP32_DENORM_V4(0), FP32_DENORM_V5(1), FP32_DENORM_V6(1), FP32_DENORM_V7(0) } }, 16735 { /*src2 */ { FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_DENORM_V6(1), FP32_DENORM_V7(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_V1(0), FP32_DENORM_V0(0) } }, 16736 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16737 /*mxcsr:in */ X86_MXCSR_DAZ, 16738 /*128:out */ X86_MXCSR_DAZ, 16739 /*256:out */ X86_MXCSR_DAZ }, 16550 16740 #define TINY_MAXx8 FP32_V(0,0x7ffffe,3) /* 8 * FP32_DENORM_MAX(0) */ 16551 16741 #define TINY_MINx8 FP32_V(0,8,0) /* 8 * FP32_DENORM_MIN(0) */ … … 16579 16769 * Invalids. 16580 16770 */ 16581 /*1 6|17*/{ { /*src1 */ { FP32_QNAN_V5(0), FP32_QNAN_V2(1), FP32_QNAN_V0(1), FP32_QNAN_V0(0), FP32_QNAN_V3(1), FP32_QNAN_V7(0), FP32_QNAN(0), FP32_QNAN_V4(1) } },16771 /*17|18*/{ { /*src1 */ { FP32_QNAN_V5(0), FP32_QNAN_V2(1), FP32_QNAN_V0(1), FP32_QNAN_V0(0), FP32_QNAN_V3(1), FP32_QNAN_V7(0), FP32_QNAN(0), FP32_QNAN_V4(1) } }, 16582 16772 { /*src2 */ { FP32_QNAN(1), FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(1), FP32_QNAN_V7(1), FP32_QNAN_V6(1), FP32_QNAN_MAX(1) } }, 16583 16773 { /* => */ { FP32_QNAN_V1(0), FP32_QNAN(1), FP32_QNAN_V6(0), FP32_QNAN_MAX(0), FP32_QNAN_V7(1), FP32_QNAN_V5(1), FP32_QNAN_MAX(1), FP32_QNAN_V6(1) } }, … … 16620 16810 /*256:out */ X86_MXCSR_IE }, 16621 16811 }; 16622 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues E1[] =16812 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesSR[] = 16623 16813 { 16624 16814 /* 16625 16815 * Zero. 16626 16816 */ 16627 /* 0*/{ { /* src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1)} },16628 { /*src 2*/ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },16817 /* 0*/{ { /*unused */ { FP32_ROW_UNUSED } }, 16818 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } }, 16629 16819 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } }, 16630 /*mxcsr:in */ 0,16631 /*128:out */ 0,16632 /*256:out */ 0 },16633 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },16634 { /*src2 */ { FP32_1(0), FP32_1(1), FP32_2(0), FP32_2(1), FP32_NORM_V0(0), FP32_NORM_V0(1), FP32_RAND_V0(0), FP32_RAND_V0(1) } },16635 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },16636 /*mxcsr:in */ 0,16637 /*128:out */ 0,16638 /*256:out */ 0 },16639 /*16640 * Infinity.16641 */16642 /* 2*/{ { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } },16643 { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } },16644 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0) } },16645 /*mxcsr:in */ 0,16646 /*128:out */ 0,16647 /*256:out */ 0 },16648 { { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } },16649 { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(1) } },16650 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN(1), FP32_0(0), FP32_0(0), FP32_0(0) } },16651 /*mxcsr:in */ 0, /* oo + -oo = IE */16652 /*128:out */ 0,16653 /*256:out */ X86_MXCSR_IE },16654 { { /*src1 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(1), FP32_0(0) } },16655 { /*src2 */ { FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1) } },16656 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },16657 /*mxcsr:in */ 0, /* no IE: the oo * 0 dot-product is skipped */16658 /*128:out */ 0,16659 /*256:out */ 0 },16660 { { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },16661 { /*src2 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0) } },16662 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } },16663 /*mxcsr:in */ 0, /* big * big = oo (OE); big * -big = -oo (OE) */16664 /*128:out */ X86_MXCSR_OE | X86_MXCSR_PE,16665 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE },16666 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },16667 { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },16668 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) /* unused */ } },16669 /*mxcsr:in */ 0, /* big * big = oo (OE); big * -big = -oo (OE) */16670 /*128:out */ 0, /* OE hits in multiply step, before IE in addition step */16671 /*256:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED },16672 { { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1) } },16673 { /*src2 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0) } },16674 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } },16675 /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM, /* big * big = oo (OE) is skipped; big * -big = -oo (OE); -oo + -oo = -oo (!IE) */16676 /*128:out */ X86_MXCSR_OM | X86_MXCSR_PM,16677 /*256:out */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED | BS3_MXCSR_PM_FIXED },16678 /*16679 * Normals, Precision, Overflow.16680 */16681 /* 8*/{ { /*src1 */ { FP32_1(0), FP32_1(1), FP32_2(0), FP32_2(1), FP32_1(0), FP32_1(1), FP32_2(0), FP32_2(1) } },16682 { /*src2 */ { FP32_1(0), FP32_1(1), FP32_2(0), FP32_2(1), FP32_1(1), FP32_1(0), FP32_2(0), FP32_2(0) } },16683 { /* => */ { FP32_V(0,0x100000,0x82), FP32_0(0), FP32_0(0), FP32_0(0), FP32_1(1), FP32_0(0), FP32_0(0), FP32_0(0) } },16684 /*9.0*/16685 /*mxcsr:in */ 0,16686 /*128:out */ 0,16687 /*256:out */ 0 },16688 { { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(1) } },16689 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } },16690 { /* => */ { FP32_ROW_UNUSED } },16691 /*mxcsr:in */ 0,16692 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED,16693 /*256:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED },16694 { { /*src1 */ { FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(0), FP32_NORM_MAX(1), FP32_NORM_MAX(1), FP32_NORM_MAX(0), FP32_NORM_MAX(1) } },16695 { /*src2 */ { FP32_2(0), FP32_2(1), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(1), FP32_2(0) } },16696 { /* => */ { FP32_INF(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_INF(1), FP32_0(0), FP32_0(0), FP32_0(0) } },16697 /*mxcsr:in */ X86_MXCSR_OM,16698 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED,16699 /*256:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED },16700 /** @todo more normals; rounding controls affecting different steps of the calculation */16701 /*16702 * Denormals, Underflow.16703 */16704 { { /*src1 */ { FP32_DENORM_V0(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_V3(1), FP32_DENORM_V4(0), FP32_DENORM_V5(1), FP32_DENORM_V6(1), FP32_DENORM_V7(0) } },16705 { /*src2 */ { FP32_DENORM_V4(0), FP32_DENORM_V5(0), FP32_DENORM_V6(1), FP32_DENORM_V7(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_V1(0), FP32_DENORM_V0(0) } },16706 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },16707 /*mxcsr:in */ 0,16708 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED,16709 /*256:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE },16710 { { /*src1 */ { FP32_DENORM_V0(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_V3(1), FP32_DENORM_V4(0), FP32_DENORM_V5(1), FP32_DENORM_V6(1), FP32_DENORM_V7(0) } },16711 { /*src2 */ { FP32_DENORM_V4(0), FP32_DENORM_V5(0), FP32_DENORM_V6(1), FP32_DENORM_V7(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_V1(0), FP32_DENORM_V0(0) } },16712 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },16713 /*mxcsr:in */ X86_MXCSR_UM,16714 /*128:out */ X86_MXCSR_UM | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED,16715 /*256:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE },16716 { { /*src1 */ { FP32_DENORM_V0(0), FP32_DENORM_MIN(1), FP32_DENORM_MIN(0), FP32_DENORM_V3(1), FP32_DENORM_V4(0), FP32_DENORM_V5(1), FP32_DENORM_V6(1), FP32_DENORM_V7(0) } },16717 { /*src2 */ { FP32_DENORM_V4(0), FP32_DENORM_V5(0), FP32_DENORM_V6(1), FP32_DENORM_V7(1), FP32_DENORM_MAX(1), FP32_DENORM_MAX(0), FP32_DENORM_V1(0), FP32_DENORM_V0(0) } },16718 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },16719 /*mxcsr:in */ X86_MXCSR_DM,16720 /*128:out */ X86_MXCSR_DM | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED,16721 /*256:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE },16722 #define TINY_MAXx6 FP32_V(0,0x3ffffe,3) /* 6 * FP32_DENORM_MAX(0) */16723 #define TINY_MINx6 FP32_V(0,6,0) /* 6 * FP32_DENORM_MIN(0) */16724 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0) } },16725 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } },16726 { /* => */ { TINY_MAXx6, FP32_0(0), FP32_0(0), FP32_0(0) /* unused */ } },16727 /*mxcsr:in */ 0,16728 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE,16729 /*256:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED },16730 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0) } },16731 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } },16732 { /* => */ { TINY_MAXx6, FP32_0(0), FP32_0(0), FP32_0(0) /* unused */ } },16733 /*mxcsr:in */ 0,16734 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE,16735 /*256:out */ X86_MXCSR_DE | BS3_MXCSR_DM_FIXED },16736 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0) } },16737 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } },16738 { /* => */ { TINY_MAXx6, FP32_0(0), FP32_0(0), FP32_0(0), TINY_MINx6, FP32_0(0), FP32_0(0), FP32_0(0) } },16739 /*mxcsr:in */ X86_MXCSR_DM | X86_MXCSR_UM,16740 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE,16741 /*256:out */ X86_MXCSR_DM | X86_MXCSR_UM | X86_MXCSR_DE | X86_MXCSR_PE | BS3_MXCSR_DM_FIXED | BS3_MXCSR_UM_FIXED },16742 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0) } },16743 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } },16744 { /* => */ { TINY_MAXx6, FP32_0(0), FP32_0(0), FP32_0(0), TINY_MINx6, FP32_0(0), FP32_0(0), FP32_0(0) } },16745 /*mxcsr:in */ X86_MXCSR_FZ,16746 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_PE,16747 /*256:out */ X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED },16748 { { /*src1 */ { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0), FP32_DENORM_MIN(0) } },16749 { /*src2 */ { FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0), FP32_2(0) } },16750 { /* => */ { TINY_MAXx6, FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },16751 /*mxcsr:in */ X86_MXCSR_UM | X86_MXCSR_FZ,16752 /*128:out */ X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_PE,16753 /*256:out */ X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED },16754 #undef TINY_MAXx616755 #undef TINY_MINx616756 /*16757 * Invalids.16758 */16759 /*16|17*/{ { /*src1 */ { FP32_QNAN_V5(0), FP32_QNAN_V2(1), FP32_QNAN_V0(1), FP32_QNAN_V0(0), FP32_QNAN_V3(1), FP32_QNAN_V7(0), FP32_QNAN(0), FP32_QNAN_V4(1) } },16760 { /*src2 */ { FP32_QNAN(1), FP32_QNAN_V1(0), FP32_QNAN_MAX(0), FP32_QNAN_V6(0), FP32_QNAN_V5(1), FP32_QNAN_V7(1), FP32_QNAN_V6(1), FP32_QNAN_MAX(1) } },16761 { /* => */ { FP32_QNAN_V1(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN_V7(1), FP32_0(0), FP32_0(0), FP32_0(0) } },16762 /*mxcsr:in */ 0, /* output swaps src2 input pairs?!? -- result from i7-10700 */16763 /*128:out */ 0,16764 /*256:out */ 0 },16765 { { /*src1 */ { FP32_SNAN_V5(0), FP32_SNAN_V2(1), FP32_SNAN_V0(1), FP32_SNAN_V0(0), FP32_SNAN_V3(1), FP32_SNAN_V7(0), FP32_SNAN(0), FP32_SNAN_V4(1) } },16766 { /*src2 */ { FP32_SNAN(1), FP32_SNAN_V1(0), FP32_SNAN_MAX(0), FP32_SNAN_V6(0), FP32_SNAN_V5(1), FP32_SNAN_V7(1), FP32_SNAN_V6(1), FP32_SNAN_MAX(1) } },16767 { /* => */ { FP32_QNAN_V1(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN_V7(1), FP32_0(0), FP32_0(0), FP32_0(0) } },16768 /*mxcsr:in */ 0, /* output has swapped src2 input pairs?!? -- result from i7-10700 */16769 /*128:out */ X86_MXCSR_IE,16770 /*256:out */ X86_MXCSR_IE },16771 { { /*src1 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0) } },16772 { /*src2 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_QNAN_MAX(1) } },16773 { /* => */ { FP32_V(0,0x400000,0x80), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0) } },16774 /*3.0*/16775 /*mxcsr:in */ 0, /* output grabs the one NaN -- result from i7-10700 */16776 /*128:out */ 0,16777 /*256:out */ 0 },16778 { { /*src1 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0) } },16779 { /*src2 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_QNAN_MAX(1), FP32_1(0), FP32_1(0), FP32_1(0) } },16780 { /* => */ { FP32_V(0,0x400000,0x80), FP32_0(0), FP32_0(0), FP32_0(0), FP32_V(0,0x400000,0x80), FP32_0(0), FP32_0(0), FP32_0(0) } },16781 /*3.0*/ /*3.0*/16782 /*mxcsr:in */ 0, /* the NaN isn't in the specified set of calculations */16783 /*128:out */ 0,16784 /*256:out */ 0 },16785 { { /*src1 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_QNAN_MAX(1), FP32_1(0) } },16786 { /*src2 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0) } },16787 { /* => */ { FP32_V(0,0x400000,0x80), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0) } },16788 /*3.0*/16789 /*mxcsr:in */ 0, /* output grabs the one NaN -- result from i7-10700 */16790 /*128:out */ 0,16791 /*256:out */ 0 },16792 { { /*src1 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0) } },16793 { /*src2 */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_1(0), FP32_SNAN_MAX(1) } },16794 { /* => */ { FP32_V(0,0x400000,0x80), FP32_0(0), FP32_0(0), FP32_0(0), FP32_QNAN_MAX(1), FP32_0(0), FP32_0(0), FP32_0(0) } },16795 /*3.0*/16796 /*mxcsr:in */ 0, /* output grabs the one NaN -- result from i7-10700 */16797 /*128:out */ 0,16798 /*256:out */ X86_MXCSR_IE },16799 };16800 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesSR[] =16801 {16802 /*16803 * Zero.16804 */16805 /* 0*/{ { /*unused */ { FP32_ROW_UNUSED } },16806 { /*src1 */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_0(1) } },16807 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0), FP32_0(0) } },16808 16820 /*mxcsr:in */ 0, 16809 16821 /*128:out */ 0, … … 16941 16953 { bs3CpuInstr4_vdpps_YMM8_YMM8_YMM8_0E1h_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, YMM8, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 16942 16954 { bs3CpuInstr4_vdpps_YMM8_YMM8_FSxBX_0E1h_icebp_c64, 255, RM_MEM, T_AVX_256, YMM8, YMM8, FSxBX, PASS_ELEMENTS(s_aValuesE1) }, 16955 }; 16956 16957 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16,s_aTests32,s_aTests64); 16958 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 16959 return bs3CpuInstr4_WorkerTestType1(bMode,s_aTests[iTest].paTests,s_aTests[iTest].cTests, 16960 g_aXcptConfig4,RT_ELEMENTS(g_aXcptConfig4)); 16961 } 16962 16963 16964 /* 16965 * [V]DPPD. 16966 */ 16967 /** @todo this fails entirely under IEM, getting #GP faults and many differences in exceptions */ 16968 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_dppd(uint8_t bMode) 16969 { 16970 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues00[] = 16971 { 16972 /* 16973 * Zero. 16974 */ 16975 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 16976 { /*src2 */ { FP64_0(0), FP64_0(1) } }, 16977 { /* => */ { FP64_0(0), FP64_0(0) } }, 16978 /*mxcsr:in */ 0, 16979 /*128:out */ 0, 16980 /*256:out */ 0 }, 16981 { { /*src1 */ { FP64_0(0), FP64_0(0) } }, 16982 { /*src2 */ { FP64_1(0), FP64_1(1) } }, 16983 { /* => */ { FP64_0(0), FP64_0(0) } }, 16984 /*mxcsr:in */ 0, 16985 /*128:out */ 0, 16986 /*256:out */ 0 }, 16987 /* 16988 * Infinity. 16989 */ 16990 /* 2*/{ { /*src1 */ { FP64_INF(0), FP64_INF(1) } }, 16991 { /*src2 */ { FP64_INF(0), FP64_INF(1) } }, 16992 { /* => */ { FP64_0(0), FP64_0(0) } }, 16993 /*mxcsr:in */ 0, 16994 /*128:out */ 0, 16995 /*256:out */ 0 }, 16996 /* 16997 * Normals. 16998 */ 16999 /* 3*/{ { /*src1 */ { FP64_NORM_V0(0), FP64_NORM_V1(1) } }, 17000 { /*src2 */ { FP64_NORM_V2(0), FP64_NORM_V3(0) } }, 17001 { /* => */ { FP64_0(0), FP64_0(0) } }, 17002 /*mxcsr:in */ 0, 17003 /*128:out */ 0, 17004 /*256:out */ 0 }, 17005 /* 17006 * Denormals. 17007 */ 17008 /* 4*/{ { /*src1 */ { FP64_DENORM_MIN(1), FP64_DENORM_MAX(0) } }, 17009 { /*src2 */ { FP64_DENORM_MIN(0), FP64_DENORM_MAX(0) } }, 17010 { /* => */ { FP64_0(0), FP64_0(0) } }, 17011 /*mxcsr:in */ 0, 17012 /*128:out */ 0, 17013 /*256:out */ 0 }, 17014 /* 17015 * Invalids. 17016 */ 17017 /* 5*/{ { /*src1 */ { FP64_QNAN_V1(0), FP64_QNAN_V2(1) } }, 17018 { /*src2 */ { FP64_QNAN_MAX(0), FP64_QNAN_V0(0) } }, 17019 { /* => */ { FP64_0(0), FP64_0(0) } }, 17020 /*mxcsr:in */ 0, 17021 /*128:out */ 0, 17022 /*256:out */ 0 }, 17023 { { /*src1 */ { FP64_SNAN_V1(0), FP64_SNAN_V2(1) } }, 17024 { /*src2 */ { FP64_SNAN_MAX(0), FP64_SNAN_V0(0) } }, 17025 { /* => */ { FP64_0(0), FP64_0(0) } }, 17026 /*mxcsr:in */ 0, 17027 /*128:out */ 0, 17028 /*256:out */ 0 }, 17029 /* 17030 * Precision, Overflow, Underflow not possible in 'imm 0' case. 17031 */ 17032 }; 17033 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues22[] = 17034 { 17035 /* 17036 * Zero. 17037 */ 17038 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17039 { /*src2 */ { FP64_0(0), FP64_0(1) } }, 17040 { /* => */ { FP64_0(0), FP64_0(0) } }, 17041 /*mxcsr:in */ 0, 17042 /*128:out */ 0, 17043 /*256:out */ 0 }, 17044 { { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17045 { /*src2 */ { FP64_1(0), FP64_1(1) } }, 17046 { /* => */ { FP64_0(0), FP64_0(0) } }, 17047 /*mxcsr:in */ 0, 17048 /*128:out */ 0, 17049 /*256:out */ 0 }, 17050 /* 17051 * Infinity. 17052 */ 17053 /* 2*/{ { /*src1 */ { FP64_INF(0), FP64_INF(1) } }, 17054 { /*src2 */ { FP64_INF(0), FP64_INF(1) } }, 17055 { /* => */ { FP64_0(0), FP64_INF(0) } }, 17056 /*mxcsr:in */ 0, /* -oo * -oo = oo */ 17057 /*128:out */ 0, 17058 /*256:out */ 0 }, 17059 { { /*src1 */ { FP64_INF(0), FP64_INF(0) } }, 17060 { /*src2 */ { FP64_INF(0), FP64_INF(1) } }, 17061 { /* => */ { FP64_0(0), FP64_INF(1) } }, 17062 /*mxcsr:in */ 0, /* oo * -oo = -oo */ 17063 /*128:out */ 0, 17064 /*256:out */ -1 }, 17065 { { /*src1 */ { FP64_INF(0), FP64_0(0) } }, 17066 { /*src2 */ { FP64_0(0), FP64_0(0) } }, 17067 { /* => */ { FP64_0(0), FP64_0(0) } }, 17068 /*mxcsr:in */ 0, /* 0 * 0 = 0 */ 17069 /*128:out */ 0, 17070 /*256:out */ -1 }, 17071 { { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 17072 { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 17073 { /* => */ { FP64_0(0), FP64_INF(0) } }, 17074 /*mxcsr:in */ 0, /* big * big = oo (OE) */ 17075 /*128:out */ X86_MXCSR_OE | X86_MXCSR_PE, 17076 /*256:out */ -1 }, 17077 { { /*src1 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(0) } }, 17078 { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, 17079 { /* => */ { FP64_0(0), FP64_INF(1) } }, 17080 /*mxcsr:in */ 0, /* big * -big = -oo (OE) */ 17081 /*128:out */ X86_MXCSR_OE | X86_MXCSR_PE, 17082 /*256:out */ -1 }, 17083 /* 17084 * Normals, Precision, Overflow. 17085 */ 17086 /* 7*/{ { /*src1 */ { FP64_1(0), FP64_2(0) } }, 17087 { /*src2 */ { FP64_1(0), FP64_2(0) } }, 17088 { /* => */ { FP64_0(0), FP64_V(0,0,0x401)/*4.0*/ } }, 17089 /*mxcsr:in */ 0, 17090 /*128:out */ 0, 17091 /*256:out */ -1 }, 17092 { { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 17093 { /*src2 */ { FP64_2(0), FP64_2(0), } }, 17094 { /* => */ { FP64_ROW_UNUSED } }, 17095 /*mxcsr:in */ 0, /* big * 2 = inf (unmasked OE hits before PE) */ 17096 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 17097 /*256:out */ -1 }, 17098 { { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 17099 { /*src2 */ { FP64_2(0), FP64_2(0), } }, 17100 { /* => */ { FP64_0(0), FP64_INF(1) } }, 17101 /*mxcsr:in */ X86_MXCSR_OM, /* big * 2 = inf (OE | PE) */ 17102 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 17103 /*256:out */ -1 }, 17104 /** @todo more normals; rounding controls affecting different steps of the calculation */ 17105 /* 17106 * Denormals, Underflow. 17107 */ 17108 /*10*/{ { /*src1 */ { FP64_DENORM_V0(0), FP64_DENORM_MIN(1) } }, 17109 { /*src2 */ { FP64_DENORM_V1(0), FP64_DENORM_MAX(0) } }, 17110 { /* => */ { FP64_0(0), FP64_0(0) } }, 17111 /*mxcsr:in */ 0, 17112 /*128:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 17113 /*256:out */ -1 }, 17114 { { /*src1 */ { FP64_DENORM_V0(0), FP64_DENORM_MIN(1) } }, 17115 { /*src2 */ { FP64_DENORM_V1(0), FP64_DENORM_MAX(0) } }, 17116 { /* => */ { FP64_0(0), FP64_0(0) } }, 17117 /*mxcsr:in */ X86_MXCSR_UM, 17118 /*128:out */ X86_MXCSR_UM | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 17119 /*256:out */ -1 }, 17120 #define TINY_MAXx2 FP64_V(0,0xffffffffffffe,0x1) /* 2 * FP64_DENORM_MAX(0) */ 17121 #define TINY_MINx2 FP64_V(0,2,0) /* 2 * FP64_DENORM_MIN(0) */ 17122 { { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 17123 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17124 { /* => */ { FP64_0(0), TINY_MAXx2 } }, 17125 /*mxcsr:in */ 0, 17126 /*128:out */ X86_MXCSR_DE, 17127 /*256:out */ -1 }, 17128 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 17129 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17130 { /* => */ { FP64_ROW_UNUSED } }, 17131 /*mxcsr:in */ 0, 17132 /*128:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 17133 /*256:out */ -1 }, 17134 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 17135 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17136 { /* => */ { FP64_0(0), TINY_MINx2 } }, 17137 /*mxcsr:in */ X86_MXCSR_UM, 17138 /*128:out */ X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 17139 /*256:out */ -1 }, 17140 { { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 17141 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17142 { /* => */ { FP64_0(0), FP64_0(0) } }, 17143 /*mxcsr:in */ X86_MXCSR_DAZ, 17144 /*128:out */ X86_MXCSR_DAZ, 17145 /*256:out */ -1 }, 17146 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 17147 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17148 { /* => */ { FP64_ROW_UNUSED } }, 17149 /*mxcsr:in */ X86_MXCSR_FZ, 17150 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 17151 /*256:out */ -1 }, 17152 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 17153 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17154 { /* => */ { FP64_0(0), FP64_0(0) } }, 17155 /*mxcsr:in */ X86_MXCSR_UM | X86_MXCSR_FZ, 17156 /*128:out */ X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 17157 /*256:out */ -1 }, 17158 #undef TINY_MAXx2 17159 #undef TINY_MINx2 17160 /* 17161 * Invalids. 17162 */ 17163 /*18*/{ { /*src1 */ { FP64_QNAN_V0(0), FP64_QNAN_V2(1) } }, 17164 { /*src2 */ { FP64_QNAN(1), FP64_QNAN_V1(0) } }, 17165 { /* => */ { FP64_0(0), FP64_QNAN_V1(0) } }, 17166 /*mxcsr:in */ 0, /* output equals src2 input, same slot -- result from i7-10700 */ 17167 /*128:out */ 0, 17168 /*256:out */ 0 }, 17169 { { /*src1 */ { FP64_QNAN_V0(0), FP64_QNAN_V2(1) } }, 17170 { /*src2 */ { FP64_2(1), FP64_2(0) } }, 17171 { /* => */ { FP64_0(0), FP64_QNAN_V2(1) } }, 17172 /*mxcsr:in */ 0, /* output equals src1 input, same slot -- result from i7-10700 */ 17173 /*128:out */ 0, 17174 /*256:out */ 0 }, 17175 { { /*src1 */ { FP64_1(0), FP64_QNAN_V3(0) } }, 17176 { /*src2 */ { FP64_1(0), FP64_1(0) } }, 17177 { /* => */ { FP64_0(0), FP64_QNAN_V3(0) } }, 17178 /*mxcsr:in */ 0, /* output equals src1 input, same slot -- result from i7-10700 */ 17179 /*128:out */ 0, 17180 /*256:out */ 0 }, 17181 { { /*src1 */ { FP64_QNAN(0), FP64_1(0) } }, 17182 { /*src2 */ { FP64_1(0), FP64_1(0) } }, 17183 { /* => */ { FP64_0(0), FP64_1(0) } }, 17184 /*mxcsr:in */ 0, /* NaN not accessed */ 17185 /*128:out */ 0, 17186 /*256:out */ 0 }, 17187 { { /*src1 */ { FP64_1(0), FP64_1(0) } }, 17188 { /*src2 */ { FP64_1(0), FP64_QNAN_V1(0) } }, 17189 { /* => */ { FP64_0(0), FP64_QNAN_V1(0) } }, 17190 /*mxcsr:in */ 0, /* output equals src2 input, same slot -- result from i7-10700 */ 17191 /*128:out */ 0, 17192 /*256:out */ 0 }, 17193 { { /*src1 */ { FP64_1(0), FP64_1(0) } }, 17194 { /*src2 */ { FP64_QNAN(1), FP64_1(0) } }, 17195 { /* => */ { FP64_0(0), FP64_1(0) } }, 17196 /*mxcsr:in */ 0, /* NaN not accessed */ 17197 /*128:out */ 0, 17198 /*256:out */ 0 }, 17199 { { /*src1 */ { FP64_SNAN_V0(0), FP64_SNAN_V2(1) } }, 17200 { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V1(0) } }, 17201 { /* => */ { FP64_0(0), FP64_QNAN_V1(0) } }, 17202 /*mxcsr:in */ 0, /* output equals src2 input, same slot, quieted -- result from i7-10700 */ 17203 /*128:out */ X86_MXCSR_IE, 17204 /*256:out */ -1 }, 17205 { { /*src1 */ { FP64_SNAN_V0(0), FP64_SNAN_V2(1) } }, 17206 { /*src2 */ { FP64_2(1), FP64_2(0) } }, 17207 { /* => */ { FP64_0(0), FP64_QNAN_V2(1) } }, 17208 /*mxcsr:in */ 0, /* output equals src1 input, same slot, quieted -- result from i7-10700 */ 17209 /*128:out */ X86_MXCSR_IE, 17210 /*256:out */ -1 }, 17211 { { /*src1 */ { FP64_1(0), FP64_SNAN_V3(0) } }, 17212 { /*src2 */ { FP64_1(0), FP64_1(0) } }, 17213 { /* => */ { FP64_0(0), FP64_QNAN_V3(0) } }, 17214 /*mxcsr:in */ 0, /* output equals src1 input, same slot, quieted -- result from i7-10700 */ 17215 /*128:out */ X86_MXCSR_IE, 17216 /*256:out */ -1 }, 17217 { { /*src1 */ { FP64_SNAN(0), FP64_1(0) } }, 17218 { /*src2 */ { FP64_1(0), FP64_1(0) } }, 17219 { /* => */ { FP64_0(0), FP64_1(0) } }, 17220 /*mxcsr:in */ 0, /* NaN not accessed */ 17221 /*128:out */ 0, 17222 /*256:out */ -1 }, 17223 { { /*src1 */ { FP64_1(0), FP64_1(0) } }, 17224 { /*src2 */ { FP64_1(0), FP64_SNAN_V1(0) } }, 17225 { /* => */ { FP64_0(0), FP64_QNAN_V1(0) } }, 17226 /*mxcsr:in */ 0, /* output equals src2 NaN duplicated, quieted -- result from i7-10700 */ 17227 /*128:out */ X86_MXCSR_IE, 17228 /*256:out */ -1 }, 17229 { { /*src1 */ { FP64_1(0), FP64_1(0) } }, 17230 { /*src2 */ { FP64_SNAN(1), FP64_1(0) } }, 17231 { /* => */ { FP64_0(0), FP64_1(0) } }, 17232 /*mxcsr:in */ 0, /* NaN not accessed */ 17233 /*128:out */ 0, 17234 /*256:out */ -1 }, 17235 }; 17236 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesFF[] = 17237 { 17238 /* 17239 * Zero. 17240 */ 17241 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17242 { /*src2 */ { FP64_0(0), FP64_0(1) } }, 17243 { /* => */ { FP64_0(0), FP64_0(0) } }, 17244 /*mxcsr:in */ 0, 17245 /*128:out */ 0, 17246 /*256:out */ 0 }, 17247 { { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17248 { /*src2 */ { FP64_1(0), FP64_1(1) } }, 17249 { /* => */ { FP64_0(0), FP64_0(0) } }, 17250 /*mxcsr:in */ 0, 17251 /*128:out */ 0, 17252 /*256:out */ 0 }, 17253 /* 17254 * Infinity. 17255 */ 17256 /* 2*/{ { /*src1 */ { FP64_INF(0), FP64_INF(1) } }, 17257 { /*src2 */ { FP64_INF(0), FP64_INF(1) } }, 17258 { /* => */ { FP64_INF(0), FP64_INF(0) } }, 17259 /*mxcsr:in */ 0, /* oo + oo = oo */ 17260 /*128:out */ 0, 17261 /*256:out */ 0 }, 17262 { { /*src1 */ { FP64_INF(0), FP64_INF(0) } }, 17263 { /*src2 */ { FP64_INF(0), FP64_INF(1) } }, 17264 { /* => */ { FP64_QNAN(1), FP64_QNAN(1) } }, 17265 /*mxcsr:in */ 0, /* oo + -oo = IE */ 17266 /*128:out */ X86_MXCSR_IE, 17267 /*256:out */ -1 }, 17268 { { /*src1 */ { FP64_INF(0), FP64_0(0) } }, 17269 { /*src2 */ { FP64_0(0), FP64_0(0) } }, 17270 { /* => */ { FP64_QNAN(1), FP64_QNAN(1) } }, 17271 /*mxcsr:in */ 0, /* oo * 0 = IE */ 17272 /*128:out */ X86_MXCSR_IE, 17273 /*256:out */ -1 }, 17274 { { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 17275 { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 17276 { /* => */ { FP64_INF(0), FP64_INF(0) } }, 17277 /*mxcsr:in */ 0, /* big * big = oo (OE) */ 17278 /*128:out */ X86_MXCSR_OE | X86_MXCSR_PE, 17279 /*256:out */ -1 }, 17280 { { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 17281 { /*src2 */ { FP64_NORM_MAX(1), FP64_NORM_MAX(1) } }, 17282 { /* => */ { FP64_INF(1), FP64_INF(1) } }, 17283 /*mxcsr:in */ 0, /* big * -big = -oo (OE) */ 17284 /*128:out */ X86_MXCSR_OE | X86_MXCSR_PE, 17285 /*256:out */ -1 }, 17286 /** @todo the following three entries (including ifdef'd out one) are one test, with some corners unexplored due to tester issues. 17287 * The tester 'knows' that DE/IE/ZE are 'early' exceptions while OE/PE/UE are 'late'. This instruction can hit them in different 17288 * orders due to its internal sequence of operations. Possible fix: for all instructions, first run it unmasked; then, whatever 17289 * exception(s) hit, run it with those masked; repeat, adding more masks until the expected exceptions have all been delivered (or not). 17290 * Note this is a tester issue, the CPU is behaving correctly, we just aren't able to test it properly at the moment. 17291 */ 17292 { { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 17293 { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 17294 { /* => */ { FP64_ROW_UNUSED } }, 17295 /*mxcsr:in */ 0, /* big * big = oo (OE | PE); big * -big = -oo (OE | PE) */ 17296 /*128:out */ X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 17297 /*256:out */ -1 }, /* OE hits in multiply step, before IE in addition step */ 17298 { { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 17299 { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 17300 { /* => */ { FP64_QNAN(1), FP64_QNAN(1) } }, 17301 /*mxcsr:in */ X86_MXCSR_IM | X86_MXCSR_OM | X86_MXCSR_PM, /* big * big = oo (OE | PE); big * -big = -oo (OE | PE) */ 17302 /*128:out */ X86_MXCSR_IM | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_IE | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_IM_FIXED | BS3_MXCSR_OM_FIXED | BS3_MXCSR_PM_FIXED, 17303 /*256:out */ -1 }, /* big * big = oo (OE | PE); big * -big = -oo (OE | PE); oo + -oo = IE */ 17304 #ifdef TODO_MXCSR_ORDER /** @todo wrong order of exceptions, see above */ 17305 /*--| 9*/{ { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 17306 { /*src2 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 17307 { /* => */ { FP64_QNAN(1), FP64_QNAN(1) } }, 17308 /*mxcsr:in */ X86_MXCSR_OM, /* big * big = oo (OE | PE); big * -big = -oo (OE | PE); oo + -oo = IE */ 17309 /*128:out */ X86_MXCSR_OM | X86_MXCSR_IE | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 17310 /*256:out */ -1 }, 17311 #endif /* TODO_MXCSR_ORDER */ 17312 /* 17313 * Normals, Precision, Overflow. 17314 */ 17315 /* 9|10*/{ { /*src1 */ { FP64_1(0), FP64_2(0) } }, 17316 { /*src2 */ { FP64_1(0), FP64_2(0) } }, 17317 { /* => */ { FP64_V(0,0x4000000000000,0x401), FP64_V(0,0x4000000000000,0x401) } }, 17318 /*5.0*/ /*5.0*/ 17319 /*mxcsr:in */ 0, 17320 /*128:out */ 0, 17321 /*256:out */ -1 }, 17322 { { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(1) } }, 17323 { /*src2 */ { FP64_2(0), FP64_2(0), } }, 17324 { /* => */ { FP64_ROW_UNUSED } }, 17325 /*mxcsr:in */ 0, 17326 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 17327 /*256:out */ -1 }, 17328 { { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 17329 { /*src2 */ { FP64_1(0), FP64_1(0), } }, 17330 { /* => */ { FP64_ROW_UNUSED } }, 17331 /*mxcsr:in */ 0, /* big * 1 = big; big * 1 = big; big + big = oo (unmasked OE hits before PE) */ 17332 /*128:out */ X86_MXCSR_OE | BS3_MXCSR_OM_FIXED, 17333 /*256:out */ -1 }, 17334 { { /*src1 */ { FP64_NORM_MAX(0), FP64_NORM_MAX(0) } }, 17335 { /*src2 */ { FP64_2(0), FP64_2(0), } }, 17336 { /* => */ { FP64_INF(0), FP64_INF(0) } }, 17337 /*mxcsr:in */ X86_MXCSR_OM, /* big * 2 = oo (OE | PE); big * 2 = oo (OE | PE) */ 17338 /*128:out */ X86_MXCSR_OM | X86_MXCSR_OE | X86_MXCSR_PE | BS3_MXCSR_OM_FIXED, 17339 /*256:out */ -1 }, 17340 /** @todo more normals; rounding controls affecting different steps of the calculation */ 17341 /* 17342 * Denormals, Underflow. 17343 */ 17344 /*13|14*/{ { /*src1 */ { FP64_DENORM_V0(0), FP64_DENORM_MIN(1) } }, 17345 { /*src2 */ { FP64_DENORM_V1(0), FP64_DENORM_MAX(0) } }, 17346 { /* => */ { FP64_0(0), FP64_0(0) } }, 17347 /*mxcsr:in */ 0, 17348 /*128:out */ X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE, 17349 /*256:out */ -1 }, 17350 #define TINY_MAXx4 FP64_V(0,0xffffffffffffe,0x2) /* 4 * FP64_DENORM_MAX(0) */ 17351 #define TINY_MINx4 FP64_V(0,4,0) /* 4 * FP64_DENORM_MIN(0) */ 17352 { { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0) } }, 17353 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17354 { /* => */ { TINY_MAXx4, TINY_MAXx4 } }, 17355 /*mxcsr:in */ 0, 17356 /*128:out */ X86_MXCSR_DE, 17357 /*256:out */ -1 }, 17358 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 17359 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17360 { /* => */ { FP64_ROW_UNUSED } }, 17361 /*mxcsr:in */ 0, 17362 /*128:out */ X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 17363 /*256:out */ -1 }, 17364 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 17365 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17366 { /* => */ { TINY_MINx4, TINY_MINx4 } }, 17367 /*mxcsr:in */ X86_MXCSR_UM, 17368 /*128:out */ X86_MXCSR_UM | X86_MXCSR_DE | BS3_MXCSR_UM_FIXED, 17369 /*256:out */ -1 }, 17370 { { /*src1 */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(0) } }, 17371 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17372 { /* => */ { FP64_0(0), FP64_0(0) } }, 17373 /*mxcsr:in */ X86_MXCSR_DAZ, 17374 /*128:out */ X86_MXCSR_DAZ, 17375 /*256:out */ -1 }, 17376 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 17377 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17378 { /* => */ { FP64_ROW_UNUSED } }, 17379 /*mxcsr:in */ X86_MXCSR_FZ, 17380 /*128:out */ X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 17381 /*256:out */ -1 }, 17382 { { /*src1 */ { FP64_DENORM_MIN(0), FP64_DENORM_MIN(0) } }, 17383 { /*src2 */ { FP64_2(0), FP64_2(0) } }, 17384 { /* => */ { FP64_0(0), FP64_0(0) } }, 17385 /*mxcsr:in */ X86_MXCSR_UM | X86_MXCSR_FZ, 17386 /*128:out */ X86_MXCSR_UM | X86_MXCSR_FZ | X86_MXCSR_DE | X86_MXCSR_PE | X86_MXCSR_UE | BS3_MXCSR_UM_FIXED, 17387 /*256:out */ -1 }, 17388 #undef TINY_MAXx4 17389 #undef TINY_MINx4 17390 /* 17391 * Invalids. 17392 */ 17393 /*20|21*/{ { /*src1 */ { FP64_QNAN_V0(0), FP64_QNAN_V2(1) } }, 17394 { /*src2 */ { FP64_QNAN(1), FP64_QNAN_V1(0) } }, 17395 { /* => */ { FP64_QNAN(1), FP64_QNAN_V1(0) } }, 17396 /*mxcsr:in */ 0, /* output equals src2 input -- result from i7-10700 */ 17397 /*128:out */ 0, 17398 /*256:out */ 0 }, 17399 { { /*src1 */ { FP64_QNAN_V0(0), FP64_QNAN_V2(1) } }, 17400 { /*src2 */ { FP64_2(1), FP64_2(0) } }, 17401 { /* => */ { FP64_QNAN_V0(0), FP64_QNAN_V2(1) } }, 17402 /*mxcsr:in */ 0, /* output equals src1 input -- result from i7-10700 */ 17403 /*128:out */ 0, 17404 /*256:out */ 0 }, 17405 { { /*src1 */ { FP64_1(0), FP64_QNAN_V3(0) } }, 17406 { /*src2 */ { FP64_1(0), FP64_1(0) } }, 17407 { /* => */ { FP64_QNAN_V3(0), FP64_QNAN_V3(0) } }, 17408 /*mxcsr:in */ 0, /* output equals src1 NaN duplicated -- result from i7-10700 */ 17409 /*128:out */ 0, 17410 /*256:out */ 0 }, 17411 { { /*src1 */ { FP64_QNAN(0), FP64_1(0) } }, 17412 { /*src2 */ { FP64_1(0), FP64_1(0) } }, 17413 { /* => */ { FP64_QNAN(0), FP64_QNAN(0) } }, 17414 /*mxcsr:in */ 0, /* output equals src1 NaN duplicated -- result from i7-10700 */ 17415 /*128:out */ 0, 17416 /*256:out */ 0 }, 17417 { { /*src1 */ { FP64_1(0), FP64_1(0) } }, 17418 { /*src2 */ { FP64_1(0), FP64_QNAN_V1(0) } }, 17419 { /* => */ { FP64_QNAN_V1(0), FP64_QNAN_V1(0) } }, 17420 /*mxcsr:in */ 0, /* output equals src2 NaN duplicated -- result from i7-10700 */ 17421 /*128:out */ 0, 17422 /*256:out */ 0 }, 17423 { { /*src1 */ { FP64_1(0), FP64_1(0) } }, 17424 { /*src2 */ { FP64_QNAN(1), FP64_1(0) } }, 17425 { /* => */ { FP64_QNAN(1), FP64_QNAN(1) } }, 17426 /*mxcsr:in */ 0, /* output equals src2 NaN duplicated -- result from i7-10700 */ 17427 /*128:out */ 0, 17428 /*256:out */ 0 }, 17429 { { /*src1 */ { FP64_SNAN_V0(0), FP64_SNAN_V2(1) } }, 17430 { /*src2 */ { FP64_SNAN(1), FP64_SNAN_V1(0) } }, 17431 { /* => */ { FP64_QNAN_V(1,1), FP64_QNAN_V1(0) } }, 17432 /*mxcsr:in */ 0, /* output equals src2 input, quieted -- result from i7-10700 */ 17433 /*128:out */ X86_MXCSR_IE, 17434 /*256:out */ -1 }, 17435 { { /*src1 */ { FP64_SNAN_V0(0), FP64_SNAN_V2(1) } }, 17436 { /*src2 */ { FP64_2(1), FP64_2(0) } }, 17437 { /* => */ { FP64_QNAN_V0(0), FP64_QNAN_V2(1) } }, 17438 /*mxcsr:in */ 0, /* output equals src1 input, quieted -- result from i7-10700 */ 17439 /*128:out */ X86_MXCSR_IE, 17440 /*256:out */ -1 }, 17441 { { /*src1 */ { FP64_1(0), FP64_SNAN_V3(0) } }, 17442 { /*src2 */ { FP64_1(0), FP64_1(0) } }, 17443 { /* => */ { FP64_QNAN_V3(0), FP64_QNAN_V3(0) } }, 17444 /*mxcsr:in */ 0, /* output equals src1 NaN duplicated, quieted -- result from i7-10700 */ 17445 /*128:out */ X86_MXCSR_IE, 17446 /*256:out */ -1 }, 17447 { { /*src1 */ { FP64_SNAN(0), FP64_1(0) } }, 17448 { /*src2 */ { FP64_1(0), FP64_1(0) } }, 17449 { /* => */ { FP64_QNAN_V(0,1), FP64_QNAN_V(0,1) } }, 17450 /*mxcsr:in */ 0, /* output equals src1 NaN duplicated, quieted -- result from i7-10700 */ 17451 /*128:out */ X86_MXCSR_IE, 17452 /*256:out */ -1 }, 17453 { { /*src1 */ { FP64_1(0), FP64_1(0) } }, 17454 { /*src2 */ { FP64_1(0), FP64_SNAN_V1(0) } }, 17455 { /* => */ { FP64_QNAN_V1(0), FP64_QNAN_V1(0) } }, 17456 /*mxcsr:in */ 0, /* output equals src2 NaN duplicated, quieted -- result from i7-10700 */ 17457 /*128:out */ X86_MXCSR_IE, 17458 /*256:out */ -1 }, 17459 { { /*src1 */ { FP64_1(0), FP64_1(0) } }, 17460 { /*src2 */ { FP64_SNAN(1), FP64_1(0) } }, 17461 { /* => */ { FP64_QNAN_V(1,1), FP64_QNAN_V(1,1) } }, 17462 /*mxcsr:in */ 0, /* output equals src2 NaN duplicated, quieted -- result from i7-10700 */ 17463 /*128:out */ X86_MXCSR_IE, 17464 /*256:out */ -1 }, 17465 }; 17466 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesSR[] = 17467 { 17468 /* 17469 * Zero. 17470 */ 17471 /* 0*/{ { /*unused */ { FP64_ROW_UNUSED } }, 17472 { /*src1 */ { FP64_0(0), FP64_0(0) } }, 17473 { /* => */ { FP64_0(0), FP64_0(0) } }, 17474 /*mxcsr:in */ 0, 17475 /*128:out */ 0, 17476 /*256:out */ 0 }, 17477 /* 17478 * Infinity. 17479 */ 17480 /* 1*/{ { /*src1 */ { FP64_ROW_UNUSED } }, 17481 { /*unused */ { FP64_INF(0), FP64_INF(1) } }, 17482 { /* => */ { FP64_0(0), FP64_INF(0) } }, 17483 /*mxcsr:in */ 0, 17484 /*128:out */ 0, 17485 /*256:out */ 0 }, 17486 }; 17487 17488 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 17489 { 17490 { bs3CpuInstr4_dppd_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValues00) }, 17491 { bs3CpuInstr4_dppd_XMM1_XMM2_022h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValues22) }, 17492 { bs3CpuInstr4_dppd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesFF) }, 17493 { bs3CpuInstr4_dppd_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValues00) }, 17494 { bs3CpuInstr4_dppd_XMM1_FSxBX_022h_icebp_c16, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17495 { bs3CpuInstr4_dppd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesFF) }, 17496 17497 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValues00) }, 17498 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM3_022h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValues22) }, 17499 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesFF) }, 17500 { bs3CpuInstr4_vdppd_XMM1_XMM2_FSxBX_000h_icebp_c16, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValues00) }, 17501 { bs3CpuInstr4_vdppd_XMM1_XMM2_FSxBX_022h_icebp_c16, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17502 { bs3CpuInstr4_vdppd_XMM1_XMM2_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValuesFF) }, 17503 17504 { bs3CpuInstr4_dppd_XMM1_XMM1_022h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17505 17506 { bs3CpuInstr4_vdppd_XMM1_XMM1_XMM1_022h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17507 { bs3CpuInstr4_vdppd_XMM1_XMM1_XMM2_022h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValues22) }, 17508 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM1_022h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_ELEMENTS(s_aValues22) }, 17509 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM2_022h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17510 { bs3CpuInstr4_vdppd_XMM1_XMM1_FSxBX_022h_icebp_c16, 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17511 }; 17512 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 17513 { 17514 { bs3CpuInstr4_dppd_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValues00) }, 17515 { bs3CpuInstr4_dppd_XMM1_XMM2_022h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValues22) }, 17516 { bs3CpuInstr4_dppd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesFF) }, 17517 { bs3CpuInstr4_dppd_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValues00) }, 17518 { bs3CpuInstr4_dppd_XMM1_FSxBX_022h_icebp_c32, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17519 { bs3CpuInstr4_dppd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesFF) }, 17520 17521 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValues00) }, 17522 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM3_022h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValues22) }, 17523 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesFF) }, 17524 { bs3CpuInstr4_vdppd_XMM1_XMM2_FSxBX_000h_icebp_c32, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValues00) }, 17525 { bs3CpuInstr4_vdppd_XMM1_XMM2_FSxBX_022h_icebp_c32, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17526 { bs3CpuInstr4_vdppd_XMM1_XMM2_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValuesFF) }, 17527 17528 { bs3CpuInstr4_dppd_XMM1_XMM1_022h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17529 17530 { bs3CpuInstr4_vdppd_XMM1_XMM1_XMM1_022h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17531 { bs3CpuInstr4_vdppd_XMM1_XMM1_XMM2_022h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValues22) }, 17532 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM1_022h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_ELEMENTS(s_aValues22) }, 17533 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM2_022h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17534 { bs3CpuInstr4_vdppd_XMM1_XMM1_FSxBX_022h_icebp_c32, 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17535 }; 17536 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 17537 { 17538 { bs3CpuInstr4_dppd_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValues00) }, 17539 { bs3CpuInstr4_dppd_XMM1_XMM2_022h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValues22) }, 17540 { bs3CpuInstr4_dppd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesFF) }, 17541 { bs3CpuInstr4_dppd_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValues00) }, 17542 { bs3CpuInstr4_dppd_XMM1_FSxBX_022h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17543 { bs3CpuInstr4_dppd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesFF) }, 17544 { bs3CpuInstr4_dppd_XMM8_XMM9_022h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM8, XMM8, XMM9, PASS_ELEMENTS(s_aValues22) }, 17545 { bs3CpuInstr4_dppd_XMM8_FSxBX_022h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM8, XMM8, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17546 17547 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValues00) }, 17548 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM3_022h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValues22) }, 17549 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesFF) }, 17550 { bs3CpuInstr4_vdppd_XMM1_XMM2_FSxBX_000h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValues00) }, 17551 { bs3CpuInstr4_vdppd_XMM1_XMM2_FSxBX_022h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17552 { bs3CpuInstr4_vdppd_XMM1_XMM2_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValuesFF) }, 17553 { bs3CpuInstr4_vdppd_XMM8_XMM9_XMM10_022h_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM9, XMM10, PASS_ELEMENTS(s_aValues22) }, 17554 { bs3CpuInstr4_vdppd_XMM8_XMM9_FSxBX_022h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM8, XMM9, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17555 17556 { bs3CpuInstr4_dppd_XMM1_XMM1_022h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17557 { bs3CpuInstr4_dppd_XMM8_XMM8_022h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM8, XMM8, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17558 17559 { bs3CpuInstr4_vdppd_XMM1_XMM1_XMM1_022h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17560 { bs3CpuInstr4_vdppd_XMM1_XMM1_XMM2_022h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValues22) }, 17561 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM1_022h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_ELEMENTS(s_aValues22) }, 17562 { bs3CpuInstr4_vdppd_XMM1_XMM2_XMM2_022h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17563 { bs3CpuInstr4_vdppd_XMM1_XMM1_FSxBX_022h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValues22) }, 17564 { bs3CpuInstr4_vdppd_XMM8_XMM8_XMM8_022h_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM8, NOREG, PASS_ELEMENTS(s_aValuesSR) }, 17565 { bs3CpuInstr4_vdppd_XMM8_XMM8_FSxBX_022h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM8, XMM8, FSxBX, PASS_ELEMENTS(s_aValues22) }, 16943 17566 }; 16944 17567 … … 22284 22907 { "[v]rsqrtss", bs3CpuInstr4_v_rsqrtss, 0 }, 22285 22908 { "[v]dpps", bs3CpuInstr4_v_dpps, 0 }, 22909 { "[v]dppd", bs3CpuInstr4_v_dppd, 0 }, 22286 22910 { "cvtpi2ps", bs3CpuInstr4_cvtpi2ps, 0 }, 22287 22911 { "cvtps2pi", bs3CpuInstr4_cvtps2pi, 0 },
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