Changeset 106974 in vbox for trunk/src/VBox/ValidationKit
- Timestamp:
- Nov 13, 2024 3:41:56 AM (6 months ago)
- svn:sync-xref-src-repo-rev:
- 165904
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-4-template.mac (modified) (1 diff)
-
bs3-cpu-instr-4.c32 (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
r106947 r106974 951 951 EMIT_INSTR_PLUS_ICEBP_C64 vdppd, XMM8, XMM8, XMM8, 022h 952 952 EMIT_INSTR_PLUS_ICEBP_C64 vdppd, XMM8, XMM8, FSxBX, 022h 953 954 ; 955 ;; roundpd 956 ; 957 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM1, 008h 958 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM2, 000h 959 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM2, 008h 960 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM2, 009h 961 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM2, 00ah 962 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM2, 00bh 963 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM2, 00ch 964 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM2, 00dh 965 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM2, 00eh 966 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM2, 00fh 967 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, XMM2, 0ffh 968 EMIT_INSTR_PLUS_ICEBP roundpd, XMM1, FSxBX, 008h 969 EMIT_INSTR_PLUS_ICEBP_C64 roundpd, XMM8, XMM8, 008h 970 EMIT_INSTR_PLUS_ICEBP_C64 roundpd, XMM8, XMM9, 008h 971 EMIT_INSTR_PLUS_ICEBP_C64 roundpd, XMM8, FSxBX, 008h 972 973 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM1, 008h 974 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM2, 000h 975 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM2, 008h 976 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM2, 009h 977 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM2, 00ah 978 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM2, 00bh 979 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM2, 00ch 980 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM2, 00dh 981 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM2, 00eh 982 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM2, 00fh 983 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, XMM2, 0ffh 984 EMIT_INSTR_PLUS_ICEBP vroundpd, XMM1, FSxBX, 008h 985 EMIT_INSTR_PLUS_ICEBP_C64 vroundpd, XMM8, XMM8, 008h 986 EMIT_INSTR_PLUS_ICEBP_C64 vroundpd, XMM8, XMM9, 008h 987 EMIT_INSTR_PLUS_ICEBP_C64 vroundpd, XMM8, FSxBX, 008h 988 989 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM1, 008h 990 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM2, 000h 991 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM2, 008h 992 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM2, 009h 993 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM2, 00ah 994 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM2, 00bh 995 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM2, 00ch 996 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM2, 00dh 997 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM2, 00eh 998 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM2, 00fh 999 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, YMM2, 0ffh 1000 EMIT_INSTR_PLUS_ICEBP vroundpd, YMM1, FSxBX, 008h 1001 EMIT_INSTR_PLUS_ICEBP_C64 vroundpd, YMM8, YMM8, 008h 1002 EMIT_INSTR_PLUS_ICEBP_C64 vroundpd, YMM8, YMM9, 008h 1003 EMIT_INSTR_PLUS_ICEBP_C64 vroundpd, YMM8, FSxBX, 008h 1004 1005 ; 1006 ;; roundps 1007 ; 1008 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM1, 008h 1009 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM2, 000h 1010 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM2, 008h 1011 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM2, 009h 1012 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM2, 00ah 1013 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM2, 00bh 1014 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM2, 00ch 1015 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM2, 00dh 1016 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM2, 00eh 1017 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM2, 00fh 1018 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, XMM2, 0ffh 1019 EMIT_INSTR_PLUS_ICEBP roundps, XMM1, FSxBX, 008h 1020 EMIT_INSTR_PLUS_ICEBP_C64 roundps, XMM8, XMM8, 008h 1021 EMIT_INSTR_PLUS_ICEBP_C64 roundps, XMM8, XMM9, 008h 1022 EMIT_INSTR_PLUS_ICEBP_C64 roundps, XMM8, FSxBX, 008h 1023 1024 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM1, 008h 1025 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM2, 000h 1026 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM2, 008h 1027 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM2, 009h 1028 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM2, 00ah 1029 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM2, 00bh 1030 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM2, 00ch 1031 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM2, 00dh 1032 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM2, 00eh 1033 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM2, 00fh 1034 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, XMM2, 0ffh 1035 EMIT_INSTR_PLUS_ICEBP vroundps, XMM1, FSxBX, 008h 1036 EMIT_INSTR_PLUS_ICEBP_C64 vroundps, XMM8, XMM8, 008h 1037 EMIT_INSTR_PLUS_ICEBP_C64 vroundps, XMM8, XMM9, 008h 1038 EMIT_INSTR_PLUS_ICEBP_C64 vroundps, XMM8, FSxBX, 008h 1039 1040 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM1, 008h 1041 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM2, 000h 1042 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM2, 008h 1043 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM2, 009h 1044 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM2, 00ah 1045 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM2, 00bh 1046 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM2, 00ch 1047 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM2, 00dh 1048 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM2, 00eh 1049 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM2, 00fh 1050 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, YMM2, 0ffh 1051 EMIT_INSTR_PLUS_ICEBP vroundps, YMM1, FSxBX, 008h 1052 EMIT_INSTR_PLUS_ICEBP_C64 vroundps, YMM8, YMM8, 008h 1053 EMIT_INSTR_PLUS_ICEBP_C64 vroundps, YMM8, YMM9, 008h 1054 EMIT_INSTR_PLUS_ICEBP_C64 vroundps, YMM8, FSxBX, 008h 1055 1056 ; 1057 ;; roundsd 1058 ; 1059 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM2, 000h 1060 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM2, 008h 1061 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM2, 009h 1062 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM2, 00ah 1063 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM2, 00bh 1064 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM2, 00ch 1065 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM2, 00dh 1066 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM2, 00eh 1067 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM2, 00fh 1068 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM2, 0ffh 1069 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, FSxBX, 008h 1070 EMIT_INSTR_PLUS_ICEBP_C64 roundsd, XMM8, XMM9, 008h 1071 EMIT_INSTR_PLUS_ICEBP_C64 roundsd, XMM8, FSxBX, 008h 1072 1073 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM1, XMM2, 008h 1074 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM1, FSxBX, 008h 1075 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM1, 008h 1076 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM3, 000h 1077 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM3, 008h 1078 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM3, 009h 1079 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM3, 00ah 1080 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM3, 00bh 1081 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM3, 00ch 1082 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM3, 00dh 1083 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM3, 00eh 1084 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM3, 00fh 1085 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM3, 0ffh 1086 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, FSxBX, 008h 1087 EMIT_INSTR_PLUS_ICEBP_C64 vroundsd, XMM8, XMM8, FSxBX, 008h 1088 EMIT_INSTR_PLUS_ICEBP_C64 vroundsd, XMM8, XMM9, XMM10, 008h 1089 EMIT_INSTR_PLUS_ICEBP_C64 vroundsd, XMM8, XMM9, FSxBX, 008h 1090 1091 EMIT_INSTR_PLUS_ICEBP roundsd, XMM1, XMM1, 008h 1092 EMIT_INSTR_PLUS_ICEBP_C64 roundsd, XMM8, XMM8, 008h 1093 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM1, XMM1, 008h 1094 EMIT_INSTR_PLUS_ICEBP vroundsd, XMM1, XMM2, XMM2, 008h 1095 EMIT_INSTR_PLUS_ICEBP_C64 vroundsd, XMM8, XMM8, XMM8, 008h 1096 1097 ; 1098 ;; roundss 1099 ; 1100 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM2, 000h 1101 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM2, 008h 1102 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM2, 009h 1103 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM2, 00ah 1104 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM2, 00bh 1105 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM2, 00ch 1106 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM2, 00dh 1107 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM2, 00eh 1108 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM2, 00fh 1109 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM2, 0ffh 1110 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, FSxBX, 008h 1111 EMIT_INSTR_PLUS_ICEBP_C64 roundss, XMM8, XMM9, 008h 1112 EMIT_INSTR_PLUS_ICEBP_C64 roundss, XMM8, FSxBX, 008h 1113 1114 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM1, XMM2, 008h 1115 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM1, FSxBX, 008h 1116 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM1, 008h 1117 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM3, 000h 1118 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM3, 008h 1119 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM3, 009h 1120 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM3, 00ah 1121 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM3, 00bh 1122 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM3, 00ch 1123 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM3, 00dh 1124 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM3, 00eh 1125 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM3, 00fh 1126 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM3, 0ffh 1127 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, FSxBX, 008h 1128 EMIT_INSTR_PLUS_ICEBP_C64 vroundss, XMM8, XMM8, FSxBX, 008h 1129 EMIT_INSTR_PLUS_ICEBP_C64 vroundss, XMM8, XMM9, XMM10, 008h 1130 EMIT_INSTR_PLUS_ICEBP_C64 vroundss, XMM8, XMM9, FSxBX, 008h 1131 1132 EMIT_INSTR_PLUS_ICEBP roundss, XMM1, XMM1, 008h 1133 EMIT_INSTR_PLUS_ICEBP_C64 roundss, XMM8, XMM8, 008h 1134 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM1, XMM1, 008h 1135 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM2, 008h 1136 EMIT_INSTR_PLUS_ICEBP_C64 vroundss, XMM8, XMM8, XMM8, 008h 953 1137 954 1138 ; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r106947 r106974 17574 17574 17575 17575 /* 17576 * [V]ROUNDPS. 17577 */ 17578 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_roundps(uint8_t bMode) 17579 { 17580 /** quiet PE + round toward nearest even */ 17581 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNE[] = 17582 { 17583 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17584 { /*unused */ { FP32_ROW_UNUSED } }, 17585 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17586 /*mxcsr:in */ 0, 17587 /*128:out */ 0, 17588 /*256:out */ 0 }, 17589 }; 17590 /** quiet PE + rounding controlled by MXCSR */ 17591 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesMX[] = 17592 { 17593 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17594 { /*unused */ { FP32_ROW_UNUSED } }, 17595 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17596 /*mxcsr:in */ 0, 17597 /*128:out */ 0, 17598 /*256:out */ 0 }, 17599 }; 17600 /** quiet PE + round toward negative infinity */ 17601 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNI[] = 17602 { 17603 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17604 { /*unused */ { FP32_ROW_UNUSED } }, 17605 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17606 /*mxcsr:in */ 0, 17607 /*128:out */ 0, 17608 /*256:out */ 0 }, 17609 }; 17610 /** quiet PE + round toward positive infinity */ 17611 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesPI[] = 17612 { 17613 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17614 { /*unused */ { FP32_ROW_UNUSED } }, 17615 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17616 /*mxcsr:in */ 0, 17617 /*128:out */ 0, 17618 /*256:out */ 0 }, 17619 }; 17620 /** raise PE + round toward nearest even */ 17621 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesPE[] = 17622 { 17623 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17624 { /*unused */ { FP32_ROW_UNUSED } }, 17625 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17626 /*mxcsr:in */ 0, 17627 /*128:out */ 0, 17628 /*256:out */ 0 }, 17629 }; 17630 /** quiet PE + round toward zero */ 17631 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesZR[] = 17632 { 17633 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17634 { /*unused */ { FP32_ROW_UNUSED } }, 17635 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17636 /*mxcsr:in */ 0, 17637 /*128:out */ 0, 17638 /*256:out */ 0 }, 17639 }; 17640 /** quiet PE + rounding controlled by MXCSR (invalid encoding) */ 17641 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNV[] = 17642 { 17643 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17644 { /*unused */ { FP32_ROW_UNUSED } }, 17645 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 17646 /*mxcsr:in */ 0, 17647 /*128:out */ 0, 17648 /*256:out */ 0 }, 17649 }; 17650 17651 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 17652 { 17653 { bs3CpuInstr4_roundps_XMM1_XMM1_008h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17654 { bs3CpuInstr4_roundps_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17655 { bs3CpuInstr4_roundps_XMM1_XMM2_008h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17656 { bs3CpuInstr4_roundps_XMM1_XMM2_009h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17657 { bs3CpuInstr4_roundps_XMM1_XMM2_00ah_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17658 { bs3CpuInstr4_roundps_XMM1_XMM2_00bh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17659 { bs3CpuInstr4_roundps_XMM1_XMM2_00ch_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17660 { bs3CpuInstr4_roundps_XMM1_XMM2_00dh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17661 { bs3CpuInstr4_roundps_XMM1_XMM2_00eh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17662 { bs3CpuInstr4_roundps_XMM1_XMM2_00fh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17663 { bs3CpuInstr4_roundps_XMM1_XMM2_0ffh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17664 { bs3CpuInstr4_roundps_XMM1_FSxBX_008h_icebp_c16, 255, RM_MEM, T_SSE4_1, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17665 17666 { bs3CpuInstr4_vroundps_XMM1_XMM1_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17667 { bs3CpuInstr4_vroundps_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17668 { bs3CpuInstr4_vroundps_XMM1_XMM2_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17669 { bs3CpuInstr4_vroundps_XMM1_XMM2_009h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17670 { bs3CpuInstr4_vroundps_XMM1_XMM2_00ah_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17671 { bs3CpuInstr4_vroundps_XMM1_XMM2_00bh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17672 { bs3CpuInstr4_vroundps_XMM1_XMM2_00ch_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17673 { bs3CpuInstr4_vroundps_XMM1_XMM2_00dh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17674 { bs3CpuInstr4_vroundps_XMM1_XMM2_00eh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17675 { bs3CpuInstr4_vroundps_XMM1_XMM2_00fh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17676 { bs3CpuInstr4_vroundps_XMM1_XMM2_0ffh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17677 { bs3CpuInstr4_vroundps_XMM1_FSxBX_008h_icebp_c16, 255, RM_MEM, T_AVX_128, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17678 17679 { bs3CpuInstr4_vroundps_YMM1_YMM1_008h_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM1, PASS_ELEMENTS(s_aValuesNE) }, 17680 { bs3CpuInstr4_vroundps_YMM1_YMM2_000h_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPE) }, 17681 { bs3CpuInstr4_vroundps_YMM1_YMM2_008h_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNE) }, 17682 { bs3CpuInstr4_vroundps_YMM1_YMM2_009h_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNI) }, 17683 { bs3CpuInstr4_vroundps_YMM1_YMM2_00ah_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPI) }, 17684 { bs3CpuInstr4_vroundps_YMM1_YMM2_00bh_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesZR) }, 17685 { bs3CpuInstr4_vroundps_YMM1_YMM2_00ch_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17686 { bs3CpuInstr4_vroundps_YMM1_YMM2_00dh_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17687 { bs3CpuInstr4_vroundps_YMM1_YMM2_00eh_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17688 { bs3CpuInstr4_vroundps_YMM1_YMM2_00fh_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17689 { bs3CpuInstr4_vroundps_YMM1_YMM2_0ffh_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNV) }, 17690 { bs3CpuInstr4_vroundps_YMM1_FSxBX_008h_icebp_c16, 255, RM_MEM, T_AVX_256, YMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17691 }; 17692 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 17693 { 17694 { bs3CpuInstr4_roundps_XMM1_XMM1_008h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17695 { bs3CpuInstr4_roundps_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17696 { bs3CpuInstr4_roundps_XMM1_XMM2_008h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17697 { bs3CpuInstr4_roundps_XMM1_XMM2_009h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17698 { bs3CpuInstr4_roundps_XMM1_XMM2_00ah_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17699 { bs3CpuInstr4_roundps_XMM1_XMM2_00bh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17700 { bs3CpuInstr4_roundps_XMM1_XMM2_00ch_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17701 { bs3CpuInstr4_roundps_XMM1_XMM2_00dh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17702 { bs3CpuInstr4_roundps_XMM1_XMM2_00eh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17703 { bs3CpuInstr4_roundps_XMM1_XMM2_00fh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17704 { bs3CpuInstr4_roundps_XMM1_XMM2_0ffh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17705 { bs3CpuInstr4_roundps_XMM1_FSxBX_008h_icebp_c32, 255, RM_MEM, T_SSE4_1, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17706 17707 { bs3CpuInstr4_vroundps_XMM1_XMM1_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17708 { bs3CpuInstr4_vroundps_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17709 { bs3CpuInstr4_vroundps_XMM1_XMM2_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17710 { bs3CpuInstr4_vroundps_XMM1_XMM2_009h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17711 { bs3CpuInstr4_vroundps_XMM1_XMM2_00ah_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17712 { bs3CpuInstr4_vroundps_XMM1_XMM2_00bh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17713 { bs3CpuInstr4_vroundps_XMM1_XMM2_00ch_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17714 { bs3CpuInstr4_vroundps_XMM1_XMM2_00dh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17715 { bs3CpuInstr4_vroundps_XMM1_XMM2_00eh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17716 { bs3CpuInstr4_vroundps_XMM1_XMM2_00fh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17717 { bs3CpuInstr4_vroundps_XMM1_XMM2_0ffh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17718 { bs3CpuInstr4_vroundps_XMM1_FSxBX_008h_icebp_c32, 255, RM_MEM, T_AVX_128, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17719 17720 { bs3CpuInstr4_vroundps_YMM1_YMM1_008h_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM1, PASS_ELEMENTS(s_aValuesNE) }, 17721 { bs3CpuInstr4_vroundps_YMM1_YMM2_000h_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPE) }, 17722 { bs3CpuInstr4_vroundps_YMM1_YMM2_008h_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNE) }, 17723 { bs3CpuInstr4_vroundps_YMM1_YMM2_009h_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNI) }, 17724 { bs3CpuInstr4_vroundps_YMM1_YMM2_00ah_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPI) }, 17725 { bs3CpuInstr4_vroundps_YMM1_YMM2_00bh_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesZR) }, 17726 { bs3CpuInstr4_vroundps_YMM1_YMM2_00ch_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17727 { bs3CpuInstr4_vroundps_YMM1_YMM2_00dh_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17728 { bs3CpuInstr4_vroundps_YMM1_YMM2_00eh_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17729 { bs3CpuInstr4_vroundps_YMM1_YMM2_00fh_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17730 { bs3CpuInstr4_vroundps_YMM1_YMM2_0ffh_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNV) }, 17731 { bs3CpuInstr4_vroundps_YMM1_FSxBX_008h_icebp_c32, 255, RM_MEM, T_AVX_256, YMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17732 }; 17733 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 17734 { 17735 { bs3CpuInstr4_roundps_XMM1_XMM1_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17736 { bs3CpuInstr4_roundps_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17737 { bs3CpuInstr4_roundps_XMM1_XMM2_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17738 { bs3CpuInstr4_roundps_XMM1_XMM2_009h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17739 { bs3CpuInstr4_roundps_XMM1_XMM2_00ah_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17740 { bs3CpuInstr4_roundps_XMM1_XMM2_00bh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17741 { bs3CpuInstr4_roundps_XMM1_XMM2_00ch_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17742 { bs3CpuInstr4_roundps_XMM1_XMM2_00dh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17743 { bs3CpuInstr4_roundps_XMM1_XMM2_00eh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17744 { bs3CpuInstr4_roundps_XMM1_XMM2_00fh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17745 { bs3CpuInstr4_roundps_XMM1_XMM2_0ffh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17746 { bs3CpuInstr4_roundps_XMM1_FSxBX_008h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17747 { bs3CpuInstr4_roundps_XMM8_XMM8_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM8, NOREG, XMM8, PASS_ELEMENTS(s_aValuesNE) }, 17748 { bs3CpuInstr4_roundps_XMM8_XMM9_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM8, NOREG, XMM9, PASS_ELEMENTS(s_aValuesNE) }, 17749 { bs3CpuInstr4_roundps_XMM8_FSxBX_008h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM8, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17750 17751 { bs3CpuInstr4_vroundps_XMM1_XMM1_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17752 { bs3CpuInstr4_vroundps_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17753 { bs3CpuInstr4_vroundps_XMM1_XMM2_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17754 { bs3CpuInstr4_vroundps_XMM1_XMM2_009h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17755 { bs3CpuInstr4_vroundps_XMM1_XMM2_00ah_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17756 { bs3CpuInstr4_vroundps_XMM1_XMM2_00bh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17757 { bs3CpuInstr4_vroundps_XMM1_XMM2_00ch_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17758 { bs3CpuInstr4_vroundps_XMM1_XMM2_00dh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17759 { bs3CpuInstr4_vroundps_XMM1_XMM2_00eh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17760 { bs3CpuInstr4_vroundps_XMM1_XMM2_00fh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17761 { bs3CpuInstr4_vroundps_XMM1_XMM2_0ffh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17762 { bs3CpuInstr4_vroundps_XMM1_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17763 { bs3CpuInstr4_vroundps_XMM8_XMM8_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, NOREG, XMM8, PASS_ELEMENTS(s_aValuesNE) }, 17764 { bs3CpuInstr4_vroundps_XMM8_XMM9_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, NOREG, XMM9, PASS_ELEMENTS(s_aValuesNE) }, 17765 { bs3CpuInstr4_vroundps_XMM8_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM8, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17766 17767 { bs3CpuInstr4_vroundps_YMM1_YMM1_008h_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM1, PASS_ELEMENTS(s_aValuesNE) }, 17768 { bs3CpuInstr4_vroundps_YMM1_YMM2_000h_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPE) }, 17769 { bs3CpuInstr4_vroundps_YMM1_YMM2_008h_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNE) }, 17770 { bs3CpuInstr4_vroundps_YMM1_YMM2_009h_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNI) }, 17771 { bs3CpuInstr4_vroundps_YMM1_YMM2_00ah_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPI) }, 17772 { bs3CpuInstr4_vroundps_YMM1_YMM2_00bh_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesZR) }, 17773 { bs3CpuInstr4_vroundps_YMM1_YMM2_00ch_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17774 { bs3CpuInstr4_vroundps_YMM1_YMM2_00dh_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17775 { bs3CpuInstr4_vroundps_YMM1_YMM2_00eh_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17776 { bs3CpuInstr4_vroundps_YMM1_YMM2_00fh_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17777 { bs3CpuInstr4_vroundps_YMM1_YMM2_0ffh_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNV) }, 17778 { bs3CpuInstr4_vroundps_YMM1_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_256, YMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17779 { bs3CpuInstr4_vroundps_YMM8_YMM8_008h_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, NOREG, YMM8, PASS_ELEMENTS(s_aValuesNE) }, 17780 { bs3CpuInstr4_vroundps_YMM8_YMM9_008h_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, NOREG, YMM9, PASS_ELEMENTS(s_aValuesNE) }, 17781 { bs3CpuInstr4_vroundps_YMM8_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_256, YMM8, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17782 }; 17783 17784 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16,s_aTests32,s_aTests64); 17785 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 17786 return bs3CpuInstr4_WorkerTestType1(bMode,s_aTests[iTest].paTests,s_aTests[iTest].cTests, 17787 g_aXcptConfig2,RT_ELEMENTS(g_aXcptConfig2)); 17788 } 17789 17790 17791 /* 17792 * [V]ROUNDPD. 17793 */ 17794 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_roundpd(uint8_t bMode) 17795 { 17796 /** quiet PE + round toward nearest even */ 17797 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNE[] = 17798 { 17799 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17800 { /*unused */ { FP64_ROW_UNUSED } }, 17801 { /* => */ { FP64_0(0), FP64_0(1) } }, 17802 /*mxcsr:in */ 0, 17803 /*128:out */ 0, 17804 /*256:out */ 0 }, 17805 }; 17806 /** quiet PE + rounding controlled by MXCSR */ 17807 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesMX[] = 17808 { 17809 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17810 { /*unused */ { FP64_ROW_UNUSED } }, 17811 { /* => */ { FP64_0(0), FP64_0(1) } }, 17812 /*mxcsr:in */ 0, 17813 /*128:out */ 0, 17814 /*256:out */ 0 }, 17815 }; 17816 /** quiet PE + round toward negative infinity */ 17817 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNI[] = 17818 { 17819 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17820 { /*unused */ { FP64_ROW_UNUSED } }, 17821 { /* => */ { FP64_0(0), FP64_0(1) } }, 17822 /*mxcsr:in */ 0, 17823 /*128:out */ 0, 17824 /*256:out */ 0 }, 17825 }; 17826 /** quiet PE + round toward positive infinity */ 17827 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesPI[] = 17828 { 17829 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17830 { /*unused */ { FP64_ROW_UNUSED } }, 17831 { /* => */ { FP64_0(0), FP64_0(1) } }, 17832 /*mxcsr:in */ 0, 17833 /*128:out */ 0, 17834 /*256:out */ 0 }, 17835 }; 17836 /** raise PE + round toward nearest even */ 17837 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesPE[] = 17838 { 17839 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17840 { /*unused */ { FP64_ROW_UNUSED } }, 17841 { /* => */ { FP64_0(0), FP64_0(1) } }, 17842 /*mxcsr:in */ 0, 17843 /*128:out */ 0, 17844 /*256:out */ 0 }, 17845 }; 17846 /** quiet PE + round toward zero */ 17847 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesZR[] = 17848 { 17849 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17850 { /*unused */ { FP64_ROW_UNUSED } }, 17851 { /* => */ { FP64_0(0), FP64_0(1) } }, 17852 /*mxcsr:in */ 0, 17853 /*128:out */ 0, 17854 /*256:out */ 0 }, 17855 }; 17856 /** quiet PE + rounding controlled by MXCSR (invalid encoding) */ 17857 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNV[] = 17858 { 17859 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17860 { /*unused */ { FP64_ROW_UNUSED } }, 17861 { /* => */ { FP64_0(0), FP64_0(1) } }, 17862 /*mxcsr:in */ 0, 17863 /*128:out */ 0, 17864 /*256:out */ 0 }, 17865 }; 17866 17867 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 17868 { 17869 { bs3CpuInstr4_roundpd_XMM1_XMM1_008h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17870 { bs3CpuInstr4_roundpd_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17871 { bs3CpuInstr4_roundpd_XMM1_XMM2_008h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17872 { bs3CpuInstr4_roundpd_XMM1_XMM2_009h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17873 { bs3CpuInstr4_roundpd_XMM1_XMM2_00ah_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17874 { bs3CpuInstr4_roundpd_XMM1_XMM2_00bh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17875 { bs3CpuInstr4_roundpd_XMM1_XMM2_00ch_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17876 { bs3CpuInstr4_roundpd_XMM1_XMM2_00dh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17877 { bs3CpuInstr4_roundpd_XMM1_XMM2_00eh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17878 { bs3CpuInstr4_roundpd_XMM1_XMM2_00fh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17879 { bs3CpuInstr4_roundpd_XMM1_XMM2_0ffh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17880 { bs3CpuInstr4_roundpd_XMM1_FSxBX_008h_icebp_c16, 255, RM_MEM, T_SSE4_1, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17881 17882 { bs3CpuInstr4_vroundpd_XMM1_XMM1_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17883 { bs3CpuInstr4_vroundpd_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17884 { bs3CpuInstr4_vroundpd_XMM1_XMM2_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17885 { bs3CpuInstr4_vroundpd_XMM1_XMM2_009h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17886 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00ah_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17887 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00bh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17888 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00ch_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17889 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00dh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17890 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00eh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17891 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00fh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17892 { bs3CpuInstr4_vroundpd_XMM1_XMM2_0ffh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17893 { bs3CpuInstr4_vroundpd_XMM1_FSxBX_008h_icebp_c16, 255, RM_MEM, T_AVX_128, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17894 17895 { bs3CpuInstr4_vroundpd_YMM1_YMM1_008h_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM1, PASS_ELEMENTS(s_aValuesNE) }, 17896 { bs3CpuInstr4_vroundpd_YMM1_YMM2_000h_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPE) }, 17897 { bs3CpuInstr4_vroundpd_YMM1_YMM2_008h_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNE) }, 17898 { bs3CpuInstr4_vroundpd_YMM1_YMM2_009h_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNI) }, 17899 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00ah_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPI) }, 17900 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00bh_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesZR) }, 17901 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00ch_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17902 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00dh_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17903 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00eh_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17904 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00fh_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17905 { bs3CpuInstr4_vroundpd_YMM1_YMM2_0ffh_icebp_c16, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNV) }, 17906 { bs3CpuInstr4_vroundpd_YMM1_FSxBX_008h_icebp_c16, 255, RM_MEM, T_AVX_256, YMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17907 }; 17908 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 17909 { 17910 { bs3CpuInstr4_roundpd_XMM1_XMM1_008h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17911 { bs3CpuInstr4_roundpd_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17912 { bs3CpuInstr4_roundpd_XMM1_XMM2_008h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17913 { bs3CpuInstr4_roundpd_XMM1_XMM2_009h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17914 { bs3CpuInstr4_roundpd_XMM1_XMM2_00ah_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17915 { bs3CpuInstr4_roundpd_XMM1_XMM2_00bh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17916 { bs3CpuInstr4_roundpd_XMM1_XMM2_00ch_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17917 { bs3CpuInstr4_roundpd_XMM1_XMM2_00dh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17918 { bs3CpuInstr4_roundpd_XMM1_XMM2_00eh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17919 { bs3CpuInstr4_roundpd_XMM1_XMM2_00fh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17920 { bs3CpuInstr4_roundpd_XMM1_XMM2_0ffh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17921 { bs3CpuInstr4_roundpd_XMM1_FSxBX_008h_icebp_c32, 255, RM_MEM, T_SSE4_1, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17922 17923 { bs3CpuInstr4_vroundpd_XMM1_XMM1_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17924 { bs3CpuInstr4_vroundpd_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17925 { bs3CpuInstr4_vroundpd_XMM1_XMM2_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17926 { bs3CpuInstr4_vroundpd_XMM1_XMM2_009h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17927 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00ah_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17928 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00bh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17929 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00ch_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17930 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00dh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17931 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00eh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17932 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00fh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17933 { bs3CpuInstr4_vroundpd_XMM1_XMM2_0ffh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17934 { bs3CpuInstr4_vroundpd_XMM1_FSxBX_008h_icebp_c32, 255, RM_MEM, T_AVX_128, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17935 17936 { bs3CpuInstr4_vroundpd_YMM1_YMM1_008h_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM1, PASS_ELEMENTS(s_aValuesNE) }, 17937 { bs3CpuInstr4_vroundpd_YMM1_YMM2_000h_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPE) }, 17938 { bs3CpuInstr4_vroundpd_YMM1_YMM2_008h_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNE) }, 17939 { bs3CpuInstr4_vroundpd_YMM1_YMM2_009h_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNI) }, 17940 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00ah_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPI) }, 17941 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00bh_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesZR) }, 17942 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00ch_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17943 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00dh_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17944 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00eh_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17945 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00fh_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17946 { bs3CpuInstr4_vroundpd_YMM1_YMM2_0ffh_icebp_c32, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNV) }, 17947 { bs3CpuInstr4_vroundpd_YMM1_FSxBX_008h_icebp_c32, 255, RM_MEM, T_AVX_256, YMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17948 }; 17949 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 17950 { 17951 { bs3CpuInstr4_roundpd_XMM1_XMM1_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17952 { bs3CpuInstr4_roundpd_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17953 { bs3CpuInstr4_roundpd_XMM1_XMM2_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17954 { bs3CpuInstr4_roundpd_XMM1_XMM2_009h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17955 { bs3CpuInstr4_roundpd_XMM1_XMM2_00ah_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17956 { bs3CpuInstr4_roundpd_XMM1_XMM2_00bh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17957 { bs3CpuInstr4_roundpd_XMM1_XMM2_00ch_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17958 { bs3CpuInstr4_roundpd_XMM1_XMM2_00dh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17959 { bs3CpuInstr4_roundpd_XMM1_XMM2_00eh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17960 { bs3CpuInstr4_roundpd_XMM1_XMM2_00fh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17961 { bs3CpuInstr4_roundpd_XMM1_XMM2_0ffh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17962 { bs3CpuInstr4_roundpd_XMM1_FSxBX_008h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17963 { bs3CpuInstr4_roundpd_XMM8_XMM8_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM8, NOREG, XMM8, PASS_ELEMENTS(s_aValuesNE) }, 17964 { bs3CpuInstr4_roundpd_XMM8_XMM9_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM8, NOREG, XMM9, PASS_ELEMENTS(s_aValuesNE) }, 17965 { bs3CpuInstr4_roundpd_XMM8_FSxBX_008h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM8, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17966 17967 { bs3CpuInstr4_vroundpd_XMM1_XMM1_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 17968 { bs3CpuInstr4_vroundpd_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 17969 { bs3CpuInstr4_vroundpd_XMM1_XMM2_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 17970 { bs3CpuInstr4_vroundpd_XMM1_XMM2_009h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 17971 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00ah_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 17972 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00bh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 17973 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00ch_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17974 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00dh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17975 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00eh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17976 { bs3CpuInstr4_vroundpd_XMM1_XMM2_00fh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 17977 { bs3CpuInstr4_vroundpd_XMM1_XMM2_0ffh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 17978 { bs3CpuInstr4_vroundpd_XMM1_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17979 { bs3CpuInstr4_vroundpd_XMM8_XMM8_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, NOREG, XMM8, PASS_ELEMENTS(s_aValuesNE) }, 17980 { bs3CpuInstr4_vroundpd_XMM8_XMM9_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, NOREG, XMM9, PASS_ELEMENTS(s_aValuesNE) }, 17981 { bs3CpuInstr4_vroundpd_XMM8_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM8, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17982 17983 { bs3CpuInstr4_vroundpd_YMM1_YMM1_008h_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM1, PASS_ELEMENTS(s_aValuesNE) }, 17984 { bs3CpuInstr4_vroundpd_YMM1_YMM2_000h_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPE) }, 17985 { bs3CpuInstr4_vroundpd_YMM1_YMM2_008h_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNE) }, 17986 { bs3CpuInstr4_vroundpd_YMM1_YMM2_009h_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNI) }, 17987 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00ah_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesPI) }, 17988 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00bh_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesZR) }, 17989 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00ch_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17990 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00dh_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17991 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00eh_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17992 { bs3CpuInstr4_vroundpd_YMM1_YMM2_00fh_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesMX) }, 17993 { bs3CpuInstr4_vroundpd_YMM1_YMM2_0ffh_icebp_c64, 255, RM_REG, T_AVX_256, YMM1, NOREG, YMM2, PASS_ELEMENTS(s_aValuesNV) }, 17994 { bs3CpuInstr4_vroundpd_YMM1_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_256, YMM1, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17995 { bs3CpuInstr4_vroundpd_YMM8_YMM8_008h_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, NOREG, YMM8, PASS_ELEMENTS(s_aValuesNE) }, 17996 { bs3CpuInstr4_vroundpd_YMM8_YMM9_008h_icebp_c64, 255, RM_REG, T_AVX_256, YMM8, NOREG, YMM9, PASS_ELEMENTS(s_aValuesNE) }, 17997 { bs3CpuInstr4_vroundpd_YMM8_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_256, YMM8, NOREG, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 17998 }; 17999 18000 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16,s_aTests32,s_aTests64); 18001 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 18002 return bs3CpuInstr4_WorkerTestType1(bMode,s_aTests[iTest].paTests,s_aTests[iTest].cTests, 18003 g_aXcptConfig2,RT_ELEMENTS(g_aXcptConfig2)); 18004 } 18005 18006 18007 /* 18008 * [V]ROUNDSS. 18009 */ 18010 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_roundss(uint8_t bMode) 18011 { 18012 /** quiet PE + round toward nearest even */ 18013 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNE[] = 18014 { 18015 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 18016 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 18017 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 18018 /*mxcsr:in */ 0, 18019 /*128:out */ 0, 18020 /*256:out */ 0 }, 18021 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V2 } }, 18022 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 18023 { /* => */ { FP32_0(1), FP32_RAND_x7_V3 } }, 18024 /*mxcsr:in */ 0, 18025 /*128:out */ 0, 18026 /*256:out */ 0 }, 18027 }; 18028 /** quiet PE + rounding controlled by MXCSR */ 18029 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesMX[] = 18030 { 18031 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 18032 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 18033 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 18034 /*mxcsr:in */ 0, 18035 /*128:out */ 0, 18036 /*256:out */ 0 }, 18037 }; 18038 /** quiet PE + round toward negative infinity */ 18039 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNI[] = 18040 { 18041 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 18042 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 18043 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 18044 /*mxcsr:in */ 0, 18045 /*128:out */ 0, 18046 /*256:out */ 0 }, 18047 }; 18048 /** quiet PE + round toward positive infinity */ 18049 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesPI[] = 18050 { 18051 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 18052 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 18053 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 18054 /*mxcsr:in */ 0, 18055 /*128:out */ 0, 18056 /*256:out */ 0 }, 18057 }; 18058 /** raise PE + round toward nearest even */ 18059 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesPE[] = 18060 { 18061 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 18062 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 18063 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 18064 /*mxcsr:in */ 0, 18065 /*128:out */ 0, 18066 /*256:out */ 0 }, 18067 }; 18068 /** quiet PE + round toward zero */ 18069 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesZR[] = 18070 { 18071 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 18072 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 18073 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 18074 /*mxcsr:in */ 0, 18075 /*128:out */ 0, 18076 /*256:out */ 0 }, 18077 }; 18078 /** quiet PE + rounding controlled by MXCSR (invalid encoding) */ 18079 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNV[] = 18080 { 18081 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 18082 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 18083 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 18084 /*mxcsr:in */ 0, 18085 /*128:out */ 0, 18086 /*256:out */ 0 }, 18087 }; 18088 /** quiet PE + round toward nearest even + same-register */ 18089 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesSR[] = 18090 { 18091 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 18092 { /*src2 */ { FP32_ROW_UNUSED } }, 18093 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 18094 /*mxcsr:in */ 0, 18095 /*128:out */ 0, 18096 /*256:out */ 0 }, 18097 }; 18098 18099 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 18100 { 18101 { bs3CpuInstr4_roundss_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 18102 { bs3CpuInstr4_roundss_XMM1_XMM2_008h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18103 { bs3CpuInstr4_roundss_XMM1_XMM2_009h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 18104 { bs3CpuInstr4_roundss_XMM1_XMM2_00ah_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 18105 { bs3CpuInstr4_roundss_XMM1_XMM2_00bh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 18106 { bs3CpuInstr4_roundss_XMM1_XMM2_00ch_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18107 { bs3CpuInstr4_roundss_XMM1_XMM2_00dh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18108 { bs3CpuInstr4_roundss_XMM1_XMM2_00eh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18109 { bs3CpuInstr4_roundss_XMM1_XMM2_00fh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18110 { bs3CpuInstr4_roundss_XMM1_XMM2_0ffh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 18111 { bs3CpuInstr4_roundss_XMM1_FSxBX_008h_icebp_c16, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18112 18113 { bs3CpuInstr4_vroundss_XMM1_XMM1_XMM2_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18114 { bs3CpuInstr4_vroundss_XMM1_XMM1_FSxBX_008h_icebp_c16, 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18115 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM1_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 18116 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPE) }, 18117 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNE) }, 18118 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_009h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNI) }, 18119 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00ah_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPI) }, 18120 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00bh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesZR) }, 18121 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00ch_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18122 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00dh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18123 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00eh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18124 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00fh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18125 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_0ffh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNV) }, 18126 { bs3CpuInstr4_vroundss_XMM1_XMM2_FSxBX_008h_icebp_c16, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18127 18128 { bs3CpuInstr4_roundss_XMM1_XMM1_008h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18129 { bs3CpuInstr4_vroundss_XMM1_XMM1_XMM1_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18130 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM2_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesSR) }, 18131 }; 18132 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 18133 { 18134 { bs3CpuInstr4_roundss_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 18135 { bs3CpuInstr4_roundss_XMM1_XMM2_008h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18136 { bs3CpuInstr4_roundss_XMM1_XMM2_009h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 18137 { bs3CpuInstr4_roundss_XMM1_XMM2_00ah_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 18138 { bs3CpuInstr4_roundss_XMM1_XMM2_00bh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 18139 { bs3CpuInstr4_roundss_XMM1_XMM2_00ch_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18140 { bs3CpuInstr4_roundss_XMM1_XMM2_00dh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18141 { bs3CpuInstr4_roundss_XMM1_XMM2_00eh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18142 { bs3CpuInstr4_roundss_XMM1_XMM2_00fh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18143 { bs3CpuInstr4_roundss_XMM1_XMM2_0ffh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 18144 { bs3CpuInstr4_roundss_XMM1_FSxBX_008h_icebp_c32, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18145 18146 { bs3CpuInstr4_vroundss_XMM1_XMM1_XMM2_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18147 { bs3CpuInstr4_vroundss_XMM1_XMM1_FSxBX_008h_icebp_c32, 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18148 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM1_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 18149 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPE) }, 18150 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNE) }, 18151 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_009h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNI) }, 18152 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00ah_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPI) }, 18153 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00bh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesZR) }, 18154 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00ch_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18155 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00dh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18156 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00eh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18157 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00fh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18158 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_0ffh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNV) }, 18159 { bs3CpuInstr4_vroundss_XMM1_XMM2_FSxBX_008h_icebp_c32, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18160 18161 { bs3CpuInstr4_roundss_XMM1_XMM1_008h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18162 { bs3CpuInstr4_vroundss_XMM1_XMM1_XMM1_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18163 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM2_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesSR) }, 18164 }; 18165 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 18166 { 18167 { bs3CpuInstr4_roundss_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 18168 { bs3CpuInstr4_roundss_XMM1_XMM2_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18169 { bs3CpuInstr4_roundss_XMM1_XMM2_009h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 18170 { bs3CpuInstr4_roundss_XMM1_XMM2_00ah_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 18171 { bs3CpuInstr4_roundss_XMM1_XMM2_00bh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 18172 { bs3CpuInstr4_roundss_XMM1_XMM2_00ch_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18173 { bs3CpuInstr4_roundss_XMM1_XMM2_00dh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18174 { bs3CpuInstr4_roundss_XMM1_XMM2_00eh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18175 { bs3CpuInstr4_roundss_XMM1_XMM2_00fh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18176 { bs3CpuInstr4_roundss_XMM1_XMM2_0ffh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 18177 { bs3CpuInstr4_roundss_XMM1_FSxBX_008h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18178 { bs3CpuInstr4_roundss_XMM8_XMM9_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM8, XMM8, XMM9, PASS_ELEMENTS(s_aValuesNE) }, 18179 { bs3CpuInstr4_roundss_XMM8_FSxBX_008h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM8, XMM8, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18180 18181 { bs3CpuInstr4_vroundss_XMM1_XMM1_XMM2_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18182 { bs3CpuInstr4_vroundss_XMM1_XMM1_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18183 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM1_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 18184 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPE) }, 18185 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNE) }, 18186 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_009h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNI) }, 18187 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00ah_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPI) }, 18188 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00bh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesZR) }, 18189 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00ch_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18190 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00dh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18191 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00eh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18192 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_00fh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18193 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM3_0ffh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNV) }, 18194 { bs3CpuInstr4_vroundss_XMM1_XMM2_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18195 { bs3CpuInstr4_vroundss_XMM8_XMM8_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM8, XMM8, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18196 { bs3CpuInstr4_vroundss_XMM8_XMM9_XMM10_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM9, XMM10, PASS_ELEMENTS(s_aValuesNE) }, 18197 { bs3CpuInstr4_vroundss_XMM8_XMM9_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM8, XMM9, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18198 18199 { bs3CpuInstr4_roundss_XMM1_XMM1_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18200 { bs3CpuInstr4_roundss_XMM8_XMM8_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM8, NOREG, XMM8, PASS_ELEMENTS(s_aValuesSR) }, 18201 { bs3CpuInstr4_vroundss_XMM1_XMM1_XMM1_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18202 { bs3CpuInstr4_vroundss_XMM1_XMM2_XMM2_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesSR) }, 18203 { bs3CpuInstr4_vroundss_XMM8_XMM8_XMM8_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, NOREG, XMM8, PASS_ELEMENTS(s_aValuesSR) }, 18204 }; 18205 18206 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16,s_aTests32,s_aTests64); 18207 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 18208 return bs3CpuInstr4_WorkerTestType1(bMode,s_aTests[iTest].paTests,s_aTests[iTest].cTests, 18209 g_aXcptConfig3,RT_ELEMENTS(g_aXcptConfig3)); 18210 } 18211 18212 18213 /* 18214 * [V]ROUNDSD. 18215 */ 18216 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_roundsd(uint8_t bMode) 18217 { 18218 /** quiet PE + round toward nearest even */ 18219 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNE[] = 18220 { 18221 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 18222 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 18223 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 18224 /*mxcsr:in */ 0, 18225 /*128:out */ 0, 18226 /*256:out */ 0 }, 18227 { { /*src1 */ { FP64_0(1), FP64_RAND_V1(0) } }, 18228 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 18229 { /* => */ { FP64_0(1), FP64_RAND_V2(0) } }, 18230 /*mxcsr:in */ 0, 18231 /*128:out */ 0, 18232 /*256:out */ 0 }, 18233 }; 18234 /** quiet PE + rounding controlled by MXCSR */ 18235 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesMX[] = 18236 { 18237 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 18238 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 18239 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 18240 /*mxcsr:in */ 0, 18241 /*128:out */ 0, 18242 /*256:out */ 0 }, 18243 }; 18244 /** quiet PE + round toward negative infinity */ 18245 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNI[] = 18246 { 18247 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 18248 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 18249 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 18250 /*mxcsr:in */ 0, 18251 /*128:out */ 0, 18252 /*256:out */ 0 }, 18253 }; 18254 /** quiet PE + round toward positive infinity */ 18255 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesPI[] = 18256 { 18257 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 18258 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 18259 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 18260 /*mxcsr:in */ 0, 18261 /*128:out */ 0, 18262 /*256:out */ 0 }, 18263 }; 18264 /** raise PE + round toward nearest even */ 18265 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesPE[] = 18266 { 18267 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 18268 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 18269 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 18270 /*mxcsr:in */ 0, 18271 /*128:out */ 0, 18272 /*256:out */ 0 }, 18273 }; 18274 /** quiet PE + round toward zero */ 18275 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesZR[] = 18276 { 18277 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 18278 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 18279 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 18280 /*mxcsr:in */ 0, 18281 /*128:out */ 0, 18282 /*256:out */ 0 }, 18283 }; 18284 /** quiet PE + rounding controlled by MXCSR (invalid encoding) */ 18285 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNV[] = 18286 { 18287 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 18288 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 18289 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 18290 /*mxcsr:in */ 0, 18291 /*128:out */ 0, 18292 /*256:out */ 0 }, 18293 }; 18294 /** quiet PE + round toward nearest even + same-register */ 18295 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesSR[] = 18296 { 18297 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V2(0) } }, 18298 { /*src2 */ { FP64_ROW_UNUSED } }, 18299 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 18300 /*mxcsr:in */ 0, 18301 /*128:out */ 0, 18302 /*256:out */ 0 }, 18303 }; 18304 18305 static BS3CPUINSTR4_TEST1_T const s_aTests16[] = 18306 { 18307 { bs3CpuInstr4_roundsd_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 18308 { bs3CpuInstr4_roundsd_XMM1_XMM2_008h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18309 { bs3CpuInstr4_roundsd_XMM1_XMM2_009h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 18310 { bs3CpuInstr4_roundsd_XMM1_XMM2_00ah_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 18311 { bs3CpuInstr4_roundsd_XMM1_XMM2_00bh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 18312 { bs3CpuInstr4_roundsd_XMM1_XMM2_00ch_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18313 { bs3CpuInstr4_roundsd_XMM1_XMM2_00dh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18314 { bs3CpuInstr4_roundsd_XMM1_XMM2_00eh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18315 { bs3CpuInstr4_roundsd_XMM1_XMM2_00fh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18316 { bs3CpuInstr4_roundsd_XMM1_XMM2_0ffh_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 18317 { bs3CpuInstr4_roundsd_XMM1_FSxBX_008h_icebp_c16, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18318 18319 { bs3CpuInstr4_vroundsd_XMM1_XMM1_XMM2_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18320 { bs3CpuInstr4_vroundsd_XMM1_XMM1_FSxBX_008h_icebp_c16, 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18321 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM1_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 18322 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPE) }, 18323 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNE) }, 18324 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_009h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNI) }, 18325 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00ah_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPI) }, 18326 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00bh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesZR) }, 18327 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00ch_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18328 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00dh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18329 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00eh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18330 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00fh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18331 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_0ffh_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNV) }, 18332 { bs3CpuInstr4_vroundsd_XMM1_XMM2_FSxBX_008h_icebp_c16, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18333 18334 { bs3CpuInstr4_roundsd_XMM1_XMM1_008h_icebp_c16, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18335 { bs3CpuInstr4_vroundsd_XMM1_XMM1_XMM1_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18336 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM2_008h_icebp_c16, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesSR) }, 18337 }; 18338 static BS3CPUINSTR4_TEST1_T const s_aTests32[] = 18339 { 18340 { bs3CpuInstr4_roundsd_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 18341 { bs3CpuInstr4_roundsd_XMM1_XMM2_008h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18342 { bs3CpuInstr4_roundsd_XMM1_XMM2_009h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 18343 { bs3CpuInstr4_roundsd_XMM1_XMM2_00ah_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 18344 { bs3CpuInstr4_roundsd_XMM1_XMM2_00bh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 18345 { bs3CpuInstr4_roundsd_XMM1_XMM2_00ch_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18346 { bs3CpuInstr4_roundsd_XMM1_XMM2_00dh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18347 { bs3CpuInstr4_roundsd_XMM1_XMM2_00eh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18348 { bs3CpuInstr4_roundsd_XMM1_XMM2_00fh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18349 { bs3CpuInstr4_roundsd_XMM1_XMM2_0ffh_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 18350 { bs3CpuInstr4_roundsd_XMM1_FSxBX_008h_icebp_c32, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18351 18352 { bs3CpuInstr4_vroundsd_XMM1_XMM1_XMM2_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18353 { bs3CpuInstr4_vroundsd_XMM1_XMM1_FSxBX_008h_icebp_c32, 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18354 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM1_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 18355 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPE) }, 18356 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNE) }, 18357 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_009h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNI) }, 18358 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00ah_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPI) }, 18359 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00bh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesZR) }, 18360 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00ch_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18361 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00dh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18362 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00eh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18363 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00fh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18364 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_0ffh_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNV) }, 18365 { bs3CpuInstr4_vroundsd_XMM1_XMM2_FSxBX_008h_icebp_c32, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18366 18367 { bs3CpuInstr4_roundsd_XMM1_XMM1_008h_icebp_c32, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18368 { bs3CpuInstr4_vroundsd_XMM1_XMM1_XMM1_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18369 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM2_008h_icebp_c32, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesSR) }, 18370 }; 18371 static BS3CPUINSTR4_TEST1_T const s_aTests64[] = 18372 { 18373 { bs3CpuInstr4_roundsd_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPE) }, 18374 { bs3CpuInstr4_roundsd_XMM1_XMM2_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18375 { bs3CpuInstr4_roundsd_XMM1_XMM2_009h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNI) }, 18376 { bs3CpuInstr4_roundsd_XMM1_XMM2_00ah_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesPI) }, 18377 { bs3CpuInstr4_roundsd_XMM1_XMM2_00bh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesZR) }, 18378 { bs3CpuInstr4_roundsd_XMM1_XMM2_00ch_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18379 { bs3CpuInstr4_roundsd_XMM1_XMM2_00dh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18380 { bs3CpuInstr4_roundsd_XMM1_XMM2_00eh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18381 { bs3CpuInstr4_roundsd_XMM1_XMM2_00fh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesMX) }, 18382 { bs3CpuInstr4_roundsd_XMM1_XMM2_0ffh_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNV) }, 18383 { bs3CpuInstr4_roundsd_XMM1_FSxBX_008h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18384 { bs3CpuInstr4_roundsd_XMM8_XMM9_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM8, XMM8, XMM9, PASS_ELEMENTS(s_aValuesNE) }, 18385 { bs3CpuInstr4_roundsd_XMM8_FSxBX_008h_icebp_c64, 255, RM_MEM, T_SSE4_1, XMM8, XMM8, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18386 18387 { bs3CpuInstr4_vroundsd_XMM1_XMM1_XMM2_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_ELEMENTS(s_aValuesNE) }, 18388 { bs3CpuInstr4_vroundsd_XMM1_XMM1_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18389 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM1_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_ELEMENTS(s_aValuesNE) }, 18390 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPE) }, 18391 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNE) }, 18392 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_009h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNI) }, 18393 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00ah_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesPI) }, 18394 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00bh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesZR) }, 18395 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00ch_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18396 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00dh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18397 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00eh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18398 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_00fh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesMX) }, 18399 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM3_0ffh_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_ELEMENTS(s_aValuesNV) }, 18400 { bs3CpuInstr4_vroundsd_XMM1_XMM2_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18401 { bs3CpuInstr4_vroundsd_XMM8_XMM8_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM8, XMM8, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18402 { bs3CpuInstr4_vroundsd_XMM8_XMM9_XMM10_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, XMM9, XMM10, PASS_ELEMENTS(s_aValuesNE) }, 18403 { bs3CpuInstr4_vroundsd_XMM8_XMM9_FSxBX_008h_icebp_c64, 255, RM_MEM, T_AVX_128, XMM8, XMM9, FSxBX, PASS_ELEMENTS(s_aValuesNE) }, 18404 18405 { bs3CpuInstr4_roundsd_XMM1_XMM1_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18406 { bs3CpuInstr4_roundsd_XMM8_XMM8_008h_icebp_c64, 255, RM_REG, T_SSE4_1, XMM8, NOREG, XMM8, PASS_ELEMENTS(s_aValuesSR) }, 18407 { bs3CpuInstr4_vroundsd_XMM1_XMM1_XMM1_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_ELEMENTS(s_aValuesSR) }, 18408 { bs3CpuInstr4_vroundsd_XMM1_XMM2_XMM2_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_ELEMENTS(s_aValuesSR) }, 18409 { bs3CpuInstr4_vroundsd_XMM8_XMM8_XMM8_008h_icebp_c64, 255, RM_REG, T_AVX_128, XMM8, NOREG, XMM8, PASS_ELEMENTS(s_aValuesSR) }, 18410 }; 18411 18412 static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16,s_aTests32,s_aTests64); 18413 unsigned const iTest = BS3CPUINSTR4_TEST_MODES_INDEX(bMode); 18414 return bs3CpuInstr4_WorkerTestType1(bMode,s_aTests[iTest].paTests,s_aTests[iTest].cTests, 18415 g_aXcptConfig3,RT_ELEMENTS(g_aXcptConfig3)); 18416 } 18417 18418 18419 /* 17576 18420 * CVTPI2PS. 17577 18421 */ … … 22908 23752 { "[v]dpps", bs3CpuInstr4_v_dpps, 0 }, 22909 23753 { "[v]dppd", bs3CpuInstr4_v_dppd, 0 }, 23754 { "[v]roundps", bs3CpuInstr4_v_roundps, 0 }, 23755 { "[v]roundpd", bs3CpuInstr4_v_roundpd, 0 }, 23756 { "[v]roundss", bs3CpuInstr4_v_roundss, 0 }, 23757 { "[v]roundsd", bs3CpuInstr4_v_roundsd, 0 }, 22910 23758 { "cvtpi2ps", bs3CpuInstr4_cvtpi2ps, 0 }, 22911 23759 { "cvtps2pi", bs3CpuInstr4_cvtps2pi, 0 },
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