Changeset 107046 in vbox for trunk/src/VBox/ValidationKit
- Timestamp:
- Nov 20, 2024 2:40:16 AM (2 months ago)
- File:
-
- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r107021 r107046 2465 2465 uint8_t afPadding[2]; /**< Alignment padding. */ 2466 2466 } BS3CPUINSTR4_TEST1_VALUES_T; 2467 typedef BS3CPUINSTR4_TEST1_VALUES_T BS3_FAR *PBS3CPUINSTR4_TEST1_VALUES_T; 2467 2468 2468 2469 /* … … 2610 2611 uint8_t iRegSrc2; /**< Identity of second source register. */ 2611 2612 uint8_t cValues; /**< Number of test values in @c paValues. */ 2612 BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *paValues; /**< Test values. */2613 PBS3CPUINSTR4_TEST1_VALUES_T const paValues; /**< Test values. */ 2613 2614 } BS3CPUINSTR4_TEST1_T; 2614 2615 … … 2630 2631 BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest; /**< The instruction being tested. */ 2631 2632 unsigned iVal; /**< Which iteration of the test value is this. */ 2633 PBS3CPUINSTR4_TEST1_VALUES_T pValues; /**< The test values for this iteration. */ 2632 2634 const char BS3_FAR *pszMode; /**< The testing mode (e.g. real, protected, paged and permutations). */ 2633 2635 PBS3TRAPFRAME pTrapFrame; /**< The exception (trap) frame. */ … … 2688 2690 { 2689 2691 BS3CPUINSTR4_TEST1_T const BS3_FAR *pTest = pTestCtx->pTest; 2690 BS3CPUINSTR4_TEST1_VALUES_T const BS3_FAR *pValues = &pTestCtx->pTest->paValues[pTestCtx->iVal];2692 PBS3CPUINSTR4_TEST1_VALUES_T const pValues = pTestCtx->pValues; 2691 2693 PBS3TRAPFRAME pTrapFrame = pTestCtx->pTrapFrame; 2692 2694 PBS3REGCTX pCtx = pTestCtx->pCtx; … … 3038 3040 3039 3041 /** 3040 * Test type #1 worker. 3042 * A values provider function decodes test values from an instruction-specific 3043 * format into the generic BS3CPUINSTR4_TEST1_VALUES_T structure. 3041 3044 */ 3042 static uint8_t bs3CpuInstr4_WorkerTestType1(uint8_t bMode, unsigned cTests, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, 3043 unsigned cConfigs, PCBS3CPUINSTR4_CONFIG_T paConfigs) 3045 typedef DECLCALLBACKTYPE(PBS3CPUINSTR4_TEST1_VALUES_T, BS3CPUINSTR4_TEST1_VALUES_PROVIDER,(void *paValues, const unsigned cValues, const unsigned iVal)); 3046 typedef BS3CPUINSTR4_TEST1_VALUES_PROVIDER *PBS3CPUINSTR4_TEST1_VALUES_PROVIDER; 3047 3048 static DECLCALLBACK(PBS3CPUINSTR4_TEST1_VALUES_T) bs3CpuInstr4_WorkerTestType1_Provider_Default(void *paValues, const unsigned cValues, const unsigned iVal) 3049 { 3050 return &((PBS3CPUINSTR4_TEST1_VALUES_T)paValues)[iVal]; 3051 } 3052 3053 /** 3054 * Test type #1 worker with optional test-unique test value provider. 3055 */ 3056 static uint8_t bs3CpuInstr4_WorkerTestType1_P(uint8_t bMode, unsigned cTests, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, 3057 unsigned cConfigs, PCBS3CPUINSTR4_CONFIG_T paConfigs, PBS3CPUINSTR4_TEST1_VALUES_PROVIDER pfnProvider) 3044 3058 { 3045 3059 BS3REGCTX Ctx; … … 3173 3187 TestCtx.pConfig = &paConfigs[iCfg]; 3174 3188 TestCtx.pTest = pTest; 3189 TestCtx.pValues = pfnProvider((void *)pTest->paValues, cValues, iVal); 3175 3190 TestCtx.iVal = iVal; 3176 3191 TestCtx.pszMode = pszMode; … … 3213 3228 bs3CpuInstrXFreeExtCtxs(pExtCtx, pExtCtxOut); 3214 3229 return 0; 3230 } 3231 3232 /** 3233 * Test type #1 worker using generic test values table. 3234 */ 3235 static uint8_t bs3CpuInstr4_WorkerTestType1(uint8_t bMode, unsigned cTests, BS3CPUINSTR4_TEST1_T const BS3_FAR *paTests, 3236 unsigned cConfigs, PCBS3CPUINSTR4_CONFIG_T paConfigs) 3237 { 3238 return bs3CpuInstr4_WorkerTestType1_P(bMode, cTests, paTests, cConfigs, paConfigs, bs3CpuInstr4_WorkerTestType1_Provider_Default); 3215 3239 } 3216 3240 … … 16468 16492 16469 16493 16494 /* Constants for testing rounding: 0.1, 0.5, slightly below and above 0.5, 0.9; 16495 * a moderately large value well within the range where the FP format can still 16496 * represent every integer exactly + .1, .5, .9; and an integer which is beyond 16497 * the safe integer range. 16498 */ 16499 16500 #define FP32_0_1(a_Sign) FP32_V(a_Sign,0x4ccccd,0x7b) /* 0.1 */ 16501 #define FP32_0_5_DN(a_Sign) FP32_V(a_Sign,0x7fffff,0x7d) /* 0.5[DN] */ 16502 #define FP32_0_5(a_Sign) FP32_V(a_Sign,0,0x7e) /* 0.5 */ 16503 #define FP32_0_5_UP(a_Sign) FP32_V(a_Sign,1,0x7e) /* 0.5[UP] */ 16504 #define FP32_0_9(a_Sign) FP32_V(a_Sign,0x666666,0x7e) /* 0.9 */ 16505 #define FP32_12_67_0(a_Sign) FP32_V(a_Sign,0x16b438,0x93) /* 1234567.0 */ 16506 #define FP32_12_67_1(a_Sign) FP32_V(a_Sign,0x16b439,0x93) /* 1234567.1 */ 16507 #define FP32_12_67_5(a_Sign) FP32_V(a_Sign,0x16b43c,0x93) /* 1234567.5 */ 16508 #define FP32_12_67_9(a_Sign) FP32_V(a_Sign,0x16b43f,0x93) /* 1234567.9 */ 16509 #define FP32_12_68_0(a_Sign) FP32_V(a_Sign,0x16b440,0x93) /* 1234568.0 */ 16510 #define FP32_BIG_INT(a_Sign) FP32_V(a_Sign,2,0x97) /* 16777220.0*/ 16511 16512 #define FP64_0_1(a_Sign) FP64_V(a_Sign,0x999999999999a,0x3fb) /* 0.1 */ 16513 #define FP64_0_5_DN(a_Sign) FP64_V(a_Sign,0xfffffffffffff,0x3fd) /* 0.5[DN] */ 16514 #define FP64_0_5(a_Sign) FP64_V(a_Sign,0,0x3fe) /* 0.5 */ 16515 #define FP64_0_5_UP(a_Sign) FP64_V(a_Sign,1,0x3fe) /* 0.5[UP] */ 16516 #define FP64_0_9(a_Sign) FP64_V(a_Sign,0xccccccccccccd,0x3fe) /* 0.9 */ 16517 #define FP64_12_89_0(a_Sign) FP64_V(a_Sign,0xd6f3454000000,0x419) /* 123456789.0 */ 16518 #define FP64_12_89_1(a_Sign) FP64_V(a_Sign,0xd6f3454666666,0x419) /* 123456789.1 */ 16519 #define FP64_12_89_5(a_Sign) FP64_V(a_Sign,0xd6f3456000000,0x419) /* 123456789.5 */ 16520 #define FP64_12_89_9(a_Sign) FP64_V(a_Sign,0xd6f345799999a,0x419) /* 123456789.9 */ 16521 #define FP64_12_90_0(a_Sign) FP64_V(a_Sign,0xd6f3458000000,0x419) /* 123456790.0 */ 16522 #define FP64_BIG_INT(a_Sign) FP64_V(a_Sign,2,0x434) /* 9007199254740996.0 */ 16523 16470 16524 /* 16471 16525 * [V]ROUNDPS. … … 16473 16527 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_roundps(uint8_t bMode) 16474 16528 { 16475 /** quiet PE + round toward nearest even*/16529 /** quiet PE + round toward nearest (even) */ 16476 16530 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNE[] = 16477 16531 { 16532 /* 16533 * Zero. 16534 */ 16478 16535 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16479 16536 { /*unused */ { FP32_ROW_UNUSED } }, … … 16482 16539 /*128:out */ 0, 16483 16540 /*256:out */ 0 }, 16541 /* 16542 * Infinity. 16543 */ 16544 /* 1*/{ { /*src1 */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 16545 { /*unused */ { FP32_ROW_UNUSED } }, 16546 { /* => */ { FP32_INF(0), FP32_INF(1), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0), FP32_INF(1), FP32_INF(0) } }, 16547 /*mxcsr:in */ 0, 16548 /*128:out */ 0, 16549 /*256:out */ 0 }, 16550 /* 16551 * Normals. 16552 */ 16553 /* 2*/{ { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16554 { /*unused */ { FP32_ROW_UNUSED } }, 16555 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_1(1), FP32_BIG_INT(1) } }, 16556 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 16557 /*128:out */ X86_MXCSR_RC_NEAREST, 16558 /*256:out */ X86_MXCSR_RC_NEAREST }, 16559 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16560 { /*unused */ { FP32_ROW_UNUSED } }, 16561 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_1(1), FP32_BIG_INT(1) } }, 16562 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 16563 /*128:out */ X86_MXCSR_RC_DOWN, 16564 /*256:out */ X86_MXCSR_RC_DOWN }, 16565 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16566 { /*unused */ { FP32_ROW_UNUSED } }, 16567 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_1(1), FP32_BIG_INT(1) } }, 16568 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 16569 /*128:out */ X86_MXCSR_RC_UP, 16570 /*256:out */ X86_MXCSR_RC_UP }, 16571 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16572 { /*unused */ { FP32_ROW_UNUSED } }, 16573 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_1(1), FP32_BIG_INT(1) } }, 16574 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 16575 /*128:out */ X86_MXCSR_RC_ZERO, 16576 /*256:out */ X86_MXCSR_RC_ZERO }, 16577 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16578 { /*unused */ { FP32_ROW_UNUSED } }, 16579 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_2(1), FP32_0(1), FP32_0(1), FP32_1(1), FP32_2(0) } }, 16580 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 16581 /*128:out */ X86_MXCSR_RC_NEAREST, 16582 /*256:out */ X86_MXCSR_RC_NEAREST }, 16583 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16584 { /*unused */ { FP32_ROW_UNUSED } }, 16585 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_2(1), FP32_0(1), FP32_0(1), FP32_1(1), FP32_2(0) } }, 16586 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 16587 /*128:out */ X86_MXCSR_RC_DOWN, 16588 /*256:out */ X86_MXCSR_RC_DOWN }, 16589 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16590 { /*unused */ { FP32_ROW_UNUSED } }, 16591 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_2(1), FP32_0(1), FP32_0(1), FP32_1(1), FP32_2(0) } }, 16592 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 16593 /*128:out */ X86_MXCSR_RC_UP, 16594 /*256:out */ X86_MXCSR_RC_UP }, 16595 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16596 { /*unused */ { FP32_ROW_UNUSED } }, 16597 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_2(1), FP32_0(1), FP32_0(1), FP32_1(1), FP32_2(0) } }, 16598 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 16599 /*128:out */ X86_MXCSR_RC_ZERO, 16600 /*256:out */ X86_MXCSR_RC_ZERO }, 16601 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16602 { /*unused */ { FP32_ROW_UNUSED } }, 16603 { /* => */ { FP32_12_67_0(0), FP32_12_68_0(0), FP32_12_68_0(0), FP32_1(1), FP32_12_67_0(1), FP32_12_68_0(1), FP32_12_68_0(1), FP32_1(0) } }, 16604 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 16605 /*128:out */ X86_MXCSR_RC_NEAREST, 16606 /*256:out */ X86_MXCSR_RC_NEAREST }, 16607 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16608 { /*unused */ { FP32_ROW_UNUSED } }, 16609 { /* => */ { FP32_12_67_0(0), FP32_12_68_0(0), FP32_12_68_0(0), FP32_1(1), FP32_12_67_0(1), FP32_12_68_0(1), FP32_12_68_0(1), FP32_1(0) } }, 16610 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 16611 /*128:out */ X86_MXCSR_RC_DOWN, 16612 /*256:out */ X86_MXCSR_RC_DOWN }, 16613 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16614 { /*unused */ { FP32_ROW_UNUSED } }, 16615 { /* => */ { FP32_12_67_0(0), FP32_12_68_0(0), FP32_12_68_0(0), FP32_1(1), FP32_12_67_0(1), FP32_12_68_0(1), FP32_12_68_0(1), FP32_1(0) } }, 16616 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 16617 /*128:out */ X86_MXCSR_RC_UP, 16618 /*256:out */ X86_MXCSR_RC_UP }, 16619 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16620 { /*unused */ { FP32_ROW_UNUSED } }, 16621 { /* => */ { FP32_12_67_0(0), FP32_12_68_0(0), FP32_12_68_0(0), FP32_1(1), FP32_12_67_0(1), FP32_12_68_0(1), FP32_12_68_0(1), FP32_1(0) } }, 16622 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 16623 /*128:out */ X86_MXCSR_RC_ZERO, 16624 /*256:out */ X86_MXCSR_RC_ZERO }, 16625 }; 16626 /** quiet PE + round toward negative infinity */ 16627 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNI[] = 16628 { 16629 /* 16630 * Zero. 16631 */ 16632 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16633 { /*unused */ { FP32_ROW_UNUSED } }, 16634 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16635 /*mxcsr:in */ 0, 16636 /*128:out */ 0, 16637 /*256:out */ 0 }, 16638 /* 16639 * Normals. 16640 */ 16641 /* 1*/{ { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16642 { /*unused */ { FP32_ROW_UNUSED } }, 16643 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_1(1), FP32_1(1), FP32_1(1), FP32_BIG_INT(1) } }, 16644 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 16645 /*128:out */ X86_MXCSR_RC_NEAREST, 16646 /*256:out */ X86_MXCSR_RC_NEAREST }, 16647 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16648 { /*unused */ { FP32_ROW_UNUSED } }, 16649 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_1(1), FP32_1(1), FP32_1(1), FP32_BIG_INT(1) } }, 16650 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* rounding mode affirmed by instruction */ 16651 /*128:out */ X86_MXCSR_RC_DOWN, 16652 /*256:out */ X86_MXCSR_RC_DOWN }, 16653 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16654 { /*unused */ { FP32_ROW_UNUSED } }, 16655 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_1(1), FP32_1(1), FP32_1(1), FP32_BIG_INT(1) } }, 16656 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 16657 /*128:out */ X86_MXCSR_RC_UP, 16658 /*256:out */ X86_MXCSR_RC_UP }, 16659 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16660 { /*unused */ { FP32_ROW_UNUSED } }, 16661 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_1(1), FP32_1(1), FP32_1(1), FP32_BIG_INT(1) } }, 16662 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 16663 /*128:out */ X86_MXCSR_RC_ZERO, 16664 /*256:out */ X86_MXCSR_RC_ZERO }, 16665 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16666 { /*unused */ { FP32_ROW_UNUSED } }, 16667 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_2(1), FP32_1(1), FP32_1(1), FP32_1(1), FP32_2(0) } }, 16668 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 16669 /*128:out */ X86_MXCSR_RC_NEAREST, 16670 /*256:out */ X86_MXCSR_RC_NEAREST }, 16671 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16672 { /*unused */ { FP32_ROW_UNUSED } }, 16673 { /* => */ { FP32_12_67_0(0), FP32_12_67_0(0), FP32_12_67_0(0), FP32_1(1), FP32_12_68_0(1), FP32_12_68_0(1), FP32_12_68_0(1), FP32_1(0) } }, 16674 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 16675 /*128:out */ X86_MXCSR_RC_ZERO, 16676 /*256:out */ X86_MXCSR_RC_ZERO }, 16677 }; 16678 /** quiet PE + round toward positive infinity */ 16679 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesPI[] = 16680 { 16681 /* 16682 * Zero. 16683 */ 16684 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16685 { /*unused */ { FP32_ROW_UNUSED } }, 16686 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16687 /*mxcsr:in */ 0, 16688 /*128:out */ 0, 16689 /*256:out */ 0 }, 16690 /* 16691 * Normals. 16692 */ 16693 /* 1*/{ { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16694 { /*unused */ { FP32_ROW_UNUSED } }, 16695 { /* => */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_BIG_INT(1) } }, 16696 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 16697 /*128:out */ X86_MXCSR_RC_NEAREST, 16698 /*256:out */ X86_MXCSR_RC_NEAREST }, 16699 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16700 { /*unused */ { FP32_ROW_UNUSED } }, 16701 { /* => */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_BIG_INT(1) } }, 16702 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 16703 /*128:out */ X86_MXCSR_RC_DOWN, 16704 /*256:out */ X86_MXCSR_RC_DOWN }, 16705 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16706 { /*unused */ { FP32_ROW_UNUSED } }, 16707 { /* => */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_BIG_INT(1) } }, 16708 /*mxcsr:in */ X86_MXCSR_RC_UP, /* rounding mode affirmed by instruction */ 16709 /*128:out */ X86_MXCSR_RC_UP, 16710 /*256:out */ X86_MXCSR_RC_UP }, 16711 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16712 { /*unused */ { FP32_ROW_UNUSED } }, 16713 { /* => */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_BIG_INT(1) } }, 16714 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 16715 /*128:out */ X86_MXCSR_RC_ZERO, 16716 /*256:out */ X86_MXCSR_RC_ZERO }, 16717 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16718 { /*unused */ { FP32_ROW_UNUSED } }, 16719 { /* => */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_2(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_2(0) } }, 16720 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 16721 /*128:out */ X86_MXCSR_RC_DOWN, 16722 /*256:out */ X86_MXCSR_RC_DOWN }, 16723 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16724 { /*unused */ { FP32_ROW_UNUSED } }, 16725 { /* => */ { FP32_12_68_0(0), FP32_12_68_0(0), FP32_12_68_0(0), FP32_1(1), FP32_12_67_0(1), FP32_12_67_0(1), FP32_12_67_0(1), FP32_1(0) } }, 16726 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 16727 /*128:out */ X86_MXCSR_RC_ZERO, 16728 /*256:out */ X86_MXCSR_RC_ZERO }, 16729 }; 16730 /** quiet PE + round toward zero */ 16731 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesZR[] = 16732 { 16733 /* 16734 * Zero. 16735 */ 16736 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16737 { /*unused */ { FP32_ROW_UNUSED } }, 16738 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16739 /*mxcsr:in */ 0, 16740 /*128:out */ 0, 16741 /*256:out */ 0 }, 16742 /* 16743 * Normals. 16744 */ 16745 /* 1*/{ { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16746 { /*unused */ { FP32_ROW_UNUSED } }, 16747 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_BIG_INT(1) } }, 16748 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 16749 /*128:out */ X86_MXCSR_RC_NEAREST, 16750 /*256:out */ X86_MXCSR_RC_NEAREST }, 16751 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16752 { /*unused */ { FP32_ROW_UNUSED } }, 16753 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_BIG_INT(1) } }, 16754 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 16755 /*128:out */ X86_MXCSR_RC_DOWN, 16756 /*256:out */ X86_MXCSR_RC_DOWN }, 16757 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16758 { /*unused */ { FP32_ROW_UNUSED } }, 16759 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_BIG_INT(1) } }, 16760 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 16761 /*128:out */ X86_MXCSR_RC_UP, 16762 /*256:out */ X86_MXCSR_RC_UP }, 16763 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16764 { /*unused */ { FP32_ROW_UNUSED } }, 16765 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_BIG_INT(1) } }, 16766 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* rounding mode affirmed by instruction */ 16767 /*128:out */ X86_MXCSR_RC_ZERO, 16768 /*256:out */ X86_MXCSR_RC_ZERO }, 16769 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16770 { /*unused */ { FP32_ROW_UNUSED } }, 16771 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_2(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_2(0) } }, 16772 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 16773 /*128:out */ X86_MXCSR_RC_NEAREST, 16774 /*256:out */ X86_MXCSR_RC_NEAREST }, 16775 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16776 { /*unused */ { FP32_ROW_UNUSED } }, 16777 { /* => */ { FP32_12_67_0(0), FP32_12_67_0(0), FP32_12_67_0(0), FP32_1(1), FP32_12_67_0(1), FP32_12_67_0(1), FP32_12_67_0(1), FP32_1(0) } }, 16778 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 16779 /*128:out */ X86_MXCSR_RC_UP, 16780 /*256:out */ X86_MXCSR_RC_UP }, 16484 16781 }; 16485 16782 /** quiet PE + rounding controlled by MXCSR */ 16486 16783 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesMX[] = 16487 16784 { 16785 /* 16786 * Zero. 16787 */ 16488 16788 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16489 16789 { /*unused */ { FP32_ROW_UNUSED } }, … … 16492 16792 /*128:out */ 0, 16493 16793 /*256:out */ 0 }, 16794 /* 16795 * Normals. 16796 */ 16797 /* 1*/{ { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16798 { /*unused */ { FP32_ROW_UNUSED } }, 16799 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_1(1), FP32_BIG_INT(1) } }, 16800 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 16801 /*128:out */ X86_MXCSR_RC_NEAREST, 16802 /*256:out */ X86_MXCSR_RC_NEAREST }, 16803 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16804 { /*unused */ { FP32_ROW_UNUSED } }, 16805 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_1(1), FP32_1(1), FP32_1(1), FP32_BIG_INT(1) } }, 16806 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 16807 /*128:out */ X86_MXCSR_RC_DOWN, 16808 /*256:out */ X86_MXCSR_RC_DOWN }, 16809 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16810 { /*unused */ { FP32_ROW_UNUSED } }, 16811 { /* => */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_BIG_INT(1) } }, 16812 /*mxcsr:in */ X86_MXCSR_RC_UP, 16813 /*128:out */ X86_MXCSR_RC_UP, 16814 /*256:out */ X86_MXCSR_RC_UP }, 16815 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16816 { /*unused */ { FP32_ROW_UNUSED } }, 16817 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_0(1), FP32_BIG_INT(1) } }, 16818 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 16819 /*128:out */ X86_MXCSR_RC_ZERO, 16820 /*256:out */ X86_MXCSR_RC_ZERO }, 16821 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16822 { /*unused */ { FP32_ROW_UNUSED } }, 16823 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_2(1), FP32_0(1), FP32_0(1), FP32_1(1), FP32_2(0) } }, 16824 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 16825 /*128:out */ X86_MXCSR_RC_NEAREST, 16826 /*256:out */ X86_MXCSR_RC_NEAREST }, 16827 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16828 { /*unused */ { FP32_ROW_UNUSED } }, 16829 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_2(1), FP32_1(1), FP32_1(1), FP32_1(1), FP32_2(0) } }, 16830 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 16831 /*128:out */ X86_MXCSR_RC_DOWN, 16832 /*256:out */ X86_MXCSR_RC_DOWN }, 16833 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16834 { /*unused */ { FP32_ROW_UNUSED } }, 16835 { /* => */ { FP32_1(0), FP32_1(0), FP32_1(0), FP32_2(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_2(0) } }, 16836 /*mxcsr:in */ X86_MXCSR_RC_UP, 16837 /*128:out */ X86_MXCSR_RC_UP, 16838 /*256:out */ X86_MXCSR_RC_UP }, 16839 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16840 { /*unused */ { FP32_ROW_UNUSED } }, 16841 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_2(1), FP32_0(1), FP32_0(1), FP32_0(1), FP32_2(0) } }, 16842 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 16843 /*128:out */ X86_MXCSR_RC_ZERO, 16844 /*256:out */ X86_MXCSR_RC_ZERO }, 16845 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16846 { /*unused */ { FP32_ROW_UNUSED } }, 16847 { /* => */ { FP32_12_67_0(0), FP32_12_68_0(0), FP32_12_68_0(0), FP32_1(1), FP32_12_67_0(1), FP32_12_68_0(1), FP32_12_68_0(1), FP32_1(0) } }, 16848 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 16849 /*128:out */ X86_MXCSR_RC_NEAREST, 16850 /*256:out */ X86_MXCSR_RC_NEAREST }, 16851 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16852 { /*unused */ { FP32_ROW_UNUSED } }, 16853 { /* => */ { FP32_12_67_0(0), FP32_12_67_0(0), FP32_12_67_0(0), FP32_1(1), FP32_12_68_0(1), FP32_12_68_0(1), FP32_12_68_0(1), FP32_1(0) } }, 16854 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 16855 /*128:out */ X86_MXCSR_RC_DOWN, 16856 /*256:out */ X86_MXCSR_RC_DOWN }, 16857 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16858 { /*unused */ { FP32_ROW_UNUSED } }, 16859 { /* => */ { FP32_12_68_0(0), FP32_12_68_0(0), FP32_12_68_0(0), FP32_1(1), FP32_12_67_0(1), FP32_12_67_0(1), FP32_12_67_0(1), FP32_1(0) } }, 16860 /*mxcsr:in */ X86_MXCSR_RC_UP, 16861 /*128:out */ X86_MXCSR_RC_UP, 16862 /*256:out */ X86_MXCSR_RC_UP }, 16863 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16864 { /*unused */ { FP32_ROW_UNUSED } }, 16865 { /* => */ { FP32_12_67_0(0), FP32_12_67_0(0), FP32_12_67_0(0), FP32_1(1), FP32_12_67_0(1), FP32_12_67_0(1), FP32_12_67_0(1), FP32_1(0) } }, 16866 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 16867 /*128:out */ X86_MXCSR_RC_ZERO, 16868 /*256:out */ X86_MXCSR_RC_ZERO }, 16494 16869 }; 16495 /** quiet PE + round toward negative infinity*/16496 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues NI[] =16870 /** raise PE + round toward nearest (even) */ 16871 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesPE[] = 16497 16872 { 16873 /* 16874 * Zero. 16875 */ 16498 16876 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16499 16877 { /*unused */ { FP32_ROW_UNUSED } }, … … 16502 16880 /*128:out */ 0, 16503 16881 /*256:out */ 0 }, 16882 /* 16883 * Normals & Precision. 16884 */ 16885 /* 1*/{ { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16886 { /*unused */ { FP32_ROW_UNUSED } }, 16887 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_1(1), FP32_BIG_INT(1) } }, 16888 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 16889 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 16890 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN }, 16891 { { /*src1 */ { FP32_0_5_DN(0), FP32_0_5(0), FP32_0_5_UP(0), FP32_2(1), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_2(0) } }, 16892 { /*unused */ { FP32_ROW_UNUSED } }, 16893 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_2(1), FP32_0(1), FP32_0(1), FP32_1(1), FP32_2(0) } }, 16894 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 16895 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP, 16896 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP }, 16897 { { /*src1 */ { FP32_12_67_1(0), FP32_12_67_5(0), FP32_12_67_9(0), FP32_1(1), FP32_12_67_1(1), FP32_12_67_5(1), FP32_12_67_9(1), FP32_1(0) } }, 16898 { /*unused */ { FP32_ROW_UNUSED } }, 16899 { /* => */ { FP32_12_67_0(0), FP32_12_68_0(0), FP32_12_68_0(0), FP32_1(1), FP32_12_67_0(1), FP32_12_68_0(1), FP32_12_68_0(1), FP32_1(0) } }, 16900 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 16901 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 16902 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO }, 16903 { { /*src1 */ { FP32_12_67_0(0), FP32_12_68_0(0), FP32_2(0), FP32_BIG_INT(1), FP32_12_67_0(1), FP32_12_68_0(1), FP32_2(1), FP32_BIG_INT(0) } }, 16904 { /*unused */ { FP32_ROW_UNUSED } }, 16905 { /* => */ { FP32_12_67_0(0), FP32_12_68_0(0), FP32_2(0), FP32_BIG_INT(1), FP32_12_67_0(1), FP32_12_68_0(1), FP32_2(1), FP32_BIG_INT(0) } }, 16906 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 16907 /*128:out */ X86_MXCSR_RC_NEAREST, 16908 /*256:out */ X86_MXCSR_RC_NEAREST }, 16504 16909 }; 16505 /** quiet PE + round toward positive infinity*/16506 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValues PI[] =16910 /** quiet PE + rounding controlled by MXCSR (reserved encoding) */ 16911 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNV[] = 16507 16912 { 16913 /* 16914 * Zero. 16915 */ 16508 16916 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16509 16917 { /*unused */ { FP32_ROW_UNUSED } }, … … 16512 16920 /*128:out */ 0, 16513 16921 /*256:out */ 0 }, 16514 }; 16515 /** raise PE + round toward nearest even */ 16516 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesPE[] = 16517 { 16518 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16922 /* 16923 * Normals. 16924 */ 16925 /* 1*/{ { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16519 16926 { /*unused */ { FP32_ROW_UNUSED } }, 16520 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16521 /*mxcsr:in */ 0, 16522 /*128:out */ 0, 16523 /*256:out */ 0 }, 16524 }; 16525 /** quiet PE + round toward zero */ 16526 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesZR[] = 16527 { 16528 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16927 { /* => */ { FP32_0(0), FP32_0(0), FP32_1(0), FP32_BIG_INT(0), FP32_0(1), FP32_0(1), FP32_1(1), FP32_BIG_INT(1) } }, 16928 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 16929 /*128:out */ X86_MXCSR_RC_NEAREST, 16930 /*256:out */ X86_MXCSR_RC_NEAREST }, 16931 { { /*src1 */ { FP32_0_1(0), FP32_0_5(0), FP32_0_9(0), FP32_BIG_INT(0), FP32_0_1(1), FP32_0_5(1), FP32_0_9(1), FP32_BIG_INT(1) } }, 16529 16932 { /*unused */ { FP32_ROW_UNUSED } }, 16530 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16531 /*mxcsr:in */ 0, 16532 /*128:out */ 0, 16533 /*256:out */ 0 }, 16534 }; 16535 /** quiet PE + rounding controlled by MXCSR (invalid encoding) */ 16536 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNV[] = 16537 { 16538 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16539 { /*unused */ { FP32_ROW_UNUSED } }, 16540 { /* => */ { FP32_0(0), FP32_0(1), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0), FP32_0(1), FP32_0(0) } }, 16541 /*mxcsr:in */ 0, 16542 /*128:out */ 0, 16543 /*256:out */ 0 }, 16933 { /* => */ { FP32_0(0), FP32_0(0), FP32_0(0), FP32_BIG_INT(0), FP32_1(1), FP32_1(1), FP32_1(1), FP32_BIG_INT(1) } }, 16934 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 16935 /*128:out */ X86_MXCSR_RC_DOWN, 16936 /*256:out */ X86_MXCSR_RC_DOWN }, 16544 16937 }; 16545 16938 … … 16604 16997 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_roundpd(uint8_t bMode) 16605 16998 { 16606 /** quiet PE + round toward nearest even*/16999 /** quiet PE + round toward nearest (even) */ 16607 17000 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNE[] = 16608 17001 { 16609 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17002 /* 17003 * Zero. 17004 */ 17005 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 16610 17006 { /*unused */ { FP64_ROW_UNUSED } }, 16611 { /* => */ { FP64_0(0), FP64_0(1) } },17007 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 16612 17008 /*mxcsr:in */ 0, 16613 17009 /*128:out */ 0, 16614 17010 /*256:out */ 0 }, 17011 /* 17012 * Infinity. 17013 */ 17014 /* 1*/{ { /*src1 */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } }, 17015 { /*unused */ { FP64_ROW_UNUSED } }, 17016 { /* => */ { FP64_INF(0), FP64_INF(1), FP64_INF(1), FP64_INF(0) } }, 17017 /*mxcsr:in */ 0, 17018 /*128:out */ 0, 17019 /*256:out */ 0 }, 17020 /* 17021 * Normals. 17022 */ 17023 /* 2*/{ { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17024 { /*unused */ { FP64_ROW_UNUSED } }, 17025 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_BIG_INT(0) } }, 17026 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 17027 /*128:out */ X86_MXCSR_RC_NEAREST, 17028 /*256:out */ X86_MXCSR_RC_NEAREST }, 17029 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17030 { /*unused */ { FP64_ROW_UNUSED } }, 17031 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_BIG_INT(1) } }, 17032 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 17033 /*128:out */ X86_MXCSR_RC_NEAREST, 17034 /*256:out */ X86_MXCSR_RC_NEAREST }, 17035 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17036 { /*unused */ { FP64_ROW_UNUSED } }, 17037 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_BIG_INT(0) } }, 17038 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17039 /*128:out */ X86_MXCSR_RC_DOWN, 17040 /*256:out */ X86_MXCSR_RC_DOWN }, 17041 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17042 { /*unused */ { FP64_ROW_UNUSED } }, 17043 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_BIG_INT(1) } }, 17044 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17045 /*128:out */ X86_MXCSR_RC_DOWN, 17046 /*256:out */ X86_MXCSR_RC_DOWN }, 17047 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17048 { /*unused */ { FP64_ROW_UNUSED } }, 17049 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_BIG_INT(0) } }, 17050 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17051 /*128:out */ X86_MXCSR_RC_UP, 17052 /*256:out */ X86_MXCSR_RC_UP }, 17053 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17054 { /*unused */ { FP64_ROW_UNUSED } }, 17055 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_BIG_INT(1) } }, 17056 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17057 /*128:out */ X86_MXCSR_RC_UP, 17058 /*256:out */ X86_MXCSR_RC_UP }, 17059 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17060 { /*unused */ { FP64_ROW_UNUSED } }, 17061 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_BIG_INT(0) } }, 17062 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17063 /*128:out */ X86_MXCSR_RC_ZERO, 17064 /*256:out */ X86_MXCSR_RC_ZERO }, 17065 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17066 { /*unused */ { FP64_ROW_UNUSED } }, 17067 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_BIG_INT(1) } }, 17068 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17069 /*128:out */ X86_MXCSR_RC_ZERO, 17070 /*256:out */ X86_MXCSR_RC_ZERO }, 17071 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17072 { /*unused */ { FP64_ROW_UNUSED } }, 17073 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_2(1) } }, 17074 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 17075 /*128:out */ X86_MXCSR_RC_NEAREST, 17076 /*256:out */ X86_MXCSR_RC_NEAREST }, 17077 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17078 { /*unused */ { FP64_ROW_UNUSED } }, 17079 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_2(0) } }, 17080 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 17081 /*128:out */ X86_MXCSR_RC_NEAREST, 17082 /*256:out */ X86_MXCSR_RC_NEAREST }, 17083 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17084 { /*unused */ { FP64_ROW_UNUSED } }, 17085 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_2(1) } }, 17086 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17087 /*128:out */ X86_MXCSR_RC_DOWN, 17088 /*256:out */ X86_MXCSR_RC_DOWN }, 17089 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17090 { /*unused */ { FP64_ROW_UNUSED } }, 17091 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_2(0) } }, 17092 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17093 /*128:out */ X86_MXCSR_RC_DOWN, 17094 /*256:out */ X86_MXCSR_RC_DOWN }, 17095 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17096 { /*unused */ { FP64_ROW_UNUSED } }, 17097 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_2(1) } }, 17098 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17099 /*128:out */ X86_MXCSR_RC_UP, 17100 /*256:out */ X86_MXCSR_RC_UP }, 17101 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17102 { /*unused */ { FP64_ROW_UNUSED } }, 17103 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_2(0) } }, 17104 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17105 /*128:out */ X86_MXCSR_RC_UP, 17106 /*256:out */ X86_MXCSR_RC_UP }, 17107 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17108 { /*unused */ { FP64_ROW_UNUSED } }, 17109 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_2(1) } }, 17110 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17111 /*128:out */ X86_MXCSR_RC_ZERO, 17112 /*256:out */ X86_MXCSR_RC_ZERO }, 17113 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17114 { /*unused */ { FP64_ROW_UNUSED } }, 17115 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_2(0) } }, 17116 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17117 /*128:out */ X86_MXCSR_RC_ZERO, 17118 /*256:out */ X86_MXCSR_RC_ZERO }, 17119 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17120 { /*unused */ { FP64_ROW_UNUSED } }, 17121 { /* => */ { FP64_12_89_0(0), FP64_12_90_0(0), FP64_12_90_0(0), FP64_1(1) } }, 17122 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 17123 /*128:out */ X86_MXCSR_RC_NEAREST, 17124 /*256:out */ X86_MXCSR_RC_NEAREST }, 17125 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17126 { /*unused */ { FP64_ROW_UNUSED } }, 17127 { /* => */ { FP64_12_89_0(1), FP64_12_90_0(1), FP64_12_90_0(1), FP64_1(0) } }, 17128 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 17129 /*128:out */ X86_MXCSR_RC_NEAREST, 17130 /*256:out */ X86_MXCSR_RC_NEAREST }, 17131 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17132 { /*unused */ { FP64_ROW_UNUSED } }, 17133 { /* => */ { FP64_12_89_0(0), FP64_12_90_0(0), FP64_12_90_0(0), FP64_1(1) } }, 17134 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17135 /*128:out */ X86_MXCSR_RC_DOWN, 17136 /*256:out */ X86_MXCSR_RC_DOWN }, 17137 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17138 { /*unused */ { FP64_ROW_UNUSED } }, 17139 { /* => */ { FP64_12_89_0(1), FP64_12_90_0(1), FP64_12_90_0(1), FP64_1(0) } }, 17140 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17141 /*128:out */ X86_MXCSR_RC_DOWN, 17142 /*256:out */ X86_MXCSR_RC_DOWN }, 17143 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17144 { /*unused */ { FP64_ROW_UNUSED } }, 17145 { /* => */ { FP64_12_89_0(0), FP64_12_90_0(0), FP64_12_90_0(0), FP64_1(1) } }, 17146 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17147 /*128:out */ X86_MXCSR_RC_UP, 17148 /*256:out */ X86_MXCSR_RC_UP }, 17149 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17150 { /*unused */ { FP64_ROW_UNUSED } }, 17151 { /* => */ { FP64_12_89_0(1), FP64_12_90_0(1), FP64_12_90_0(1), FP64_1(0) } }, 17152 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17153 /*128:out */ X86_MXCSR_RC_UP, 17154 /*256:out */ X86_MXCSR_RC_UP }, 17155 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17156 { /*unused */ { FP64_ROW_UNUSED } }, 17157 { /* => */ { FP64_12_89_0(0), FP64_12_90_0(0), FP64_12_90_0(0), FP64_1(1) } }, 17158 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17159 /*128:out */ X86_MXCSR_RC_ZERO, 17160 /*256:out */ X86_MXCSR_RC_ZERO }, 17161 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17162 { /*unused */ { FP64_ROW_UNUSED } }, 17163 { /* => */ { FP64_12_89_0(1), FP64_12_90_0(1), FP64_12_90_0(1), FP64_1(0) } }, 17164 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17165 /*128:out */ X86_MXCSR_RC_ZERO, 17166 /*256:out */ X86_MXCSR_RC_ZERO }, 17167 }; 17168 /** quiet PE + round toward negative infinity */ 17169 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNI[] = 17170 { 17171 /* 17172 * Zero. 17173 */ 17174 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 17175 { /*unused */ { FP64_ROW_UNUSED } }, 17176 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 17177 /*mxcsr:in */ 0, 17178 /*128:out */ 0, 17179 /*256:out */ 0 }, 17180 /* 17181 * Normals. 17182 */ 17183 /* 1*/{ { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17184 { /*unused */ { FP64_ROW_UNUSED } }, 17185 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17186 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 17187 /*128:out */ X86_MXCSR_RC_NEAREST, 17188 /*256:out */ X86_MXCSR_RC_NEAREST }, 17189 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17190 { /*unused */ { FP64_ROW_UNUSED } }, 17191 { /* => */ { FP64_1(1), FP64_1(1), FP64_1(1), FP64_BIG_INT(1) } }, 17192 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 17193 /*128:out */ X86_MXCSR_RC_NEAREST, 17194 /*256:out */ X86_MXCSR_RC_NEAREST }, 17195 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17196 { /*unused */ { FP64_ROW_UNUSED } }, 17197 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17198 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* rounding mode affirmed by instruction */ 17199 /*128:out */ X86_MXCSR_RC_DOWN, 17200 /*256:out */ X86_MXCSR_RC_DOWN }, 17201 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17202 { /*unused */ { FP64_ROW_UNUSED } }, 17203 { /* => */ { FP64_1(1), FP64_1(1), FP64_1(1), FP64_BIG_INT(1) } }, 17204 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* rounding mode affirmed by instruction */ 17205 /*128:out */ X86_MXCSR_RC_DOWN, 17206 /*256:out */ X86_MXCSR_RC_DOWN }, 17207 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17208 { /*unused */ { FP64_ROW_UNUSED } }, 17209 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17210 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17211 /*128:out */ X86_MXCSR_RC_UP, 17212 /*256:out */ X86_MXCSR_RC_UP }, 17213 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17214 { /*unused */ { FP64_ROW_UNUSED } }, 17215 { /* => */ { FP64_1(1), FP64_1(1), FP64_1(1), FP64_BIG_INT(1) } }, 17216 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17217 /*128:out */ X86_MXCSR_RC_UP, 17218 /*256:out */ X86_MXCSR_RC_UP }, 17219 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17220 { /*unused */ { FP64_ROW_UNUSED } }, 17221 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17222 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17223 /*128:out */ X86_MXCSR_RC_ZERO, 17224 /*256:out */ X86_MXCSR_RC_ZERO }, 17225 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17226 { /*unused */ { FP64_ROW_UNUSED } }, 17227 { /* => */ { FP64_1(1), FP64_1(1), FP64_1(1), FP64_BIG_INT(1) } }, 17228 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17229 /*128:out */ X86_MXCSR_RC_ZERO, 17230 /*256:out */ X86_MXCSR_RC_ZERO }, 17231 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17232 { /*unused */ { FP64_ROW_UNUSED } }, 17233 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_2(1) } }, 17234 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 17235 /*128:out */ X86_MXCSR_RC_NEAREST, 17236 /*256:out */ X86_MXCSR_RC_NEAREST }, 17237 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17238 { /*unused */ { FP64_ROW_UNUSED } }, 17239 { /* => */ { FP64_1(1), FP64_1(1), FP64_1(1), FP64_2(0) } }, 17240 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 17241 /*128:out */ X86_MXCSR_RC_NEAREST, 17242 /*256:out */ X86_MXCSR_RC_NEAREST }, 17243 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17244 { /*unused */ { FP64_ROW_UNUSED } }, 17245 { /* => */ { FP64_12_89_0(0), FP64_12_89_0(0), FP64_12_89_0(0), FP64_1(1) } }, 17246 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17247 /*128:out */ X86_MXCSR_RC_ZERO, 17248 /*256:out */ X86_MXCSR_RC_ZERO }, 17249 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17250 { /*unused */ { FP64_ROW_UNUSED } }, 17251 { /* => */ { FP64_12_90_0(1), FP64_12_90_0(1), FP64_12_90_0(1), FP64_1(0) } }, 17252 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17253 /*128:out */ X86_MXCSR_RC_ZERO, 17254 /*256:out */ X86_MXCSR_RC_ZERO }, 17255 }; 17256 /** quiet PE + round toward positive infinity */ 17257 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesPI[] = 17258 { 17259 /* 17260 * Zero. 17261 */ 17262 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 17263 { /*unused */ { FP64_ROW_UNUSED } }, 17264 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 17265 /*mxcsr:in */ 0, 17266 /*128:out */ 0, 17267 /*256:out */ 0 }, 17268 /* 17269 * Normals. 17270 */ 17271 /* 1*/{ { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17272 { /*unused */ { FP64_ROW_UNUSED } }, 17273 { /* => */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_BIG_INT(0) } }, 17274 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 17275 /*128:out */ X86_MXCSR_RC_NEAREST, 17276 /*256:out */ X86_MXCSR_RC_NEAREST }, 17277 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17278 { /*unused */ { FP64_ROW_UNUSED } }, 17279 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_BIG_INT(1) } }, 17280 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 17281 /*128:out */ X86_MXCSR_RC_NEAREST, 17282 /*256:out */ X86_MXCSR_RC_NEAREST }, 17283 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17284 { /*unused */ { FP64_ROW_UNUSED } }, 17285 { /* => */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_BIG_INT(0) } }, 17286 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17287 /*128:out */ X86_MXCSR_RC_DOWN, 17288 /*256:out */ X86_MXCSR_RC_DOWN }, 17289 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17290 { /*unused */ { FP64_ROW_UNUSED } }, 17291 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_BIG_INT(1) } }, 17292 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17293 /*128:out */ X86_MXCSR_RC_DOWN, 17294 /*256:out */ X86_MXCSR_RC_DOWN }, 17295 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17296 { /*unused */ { FP64_ROW_UNUSED } }, 17297 { /* => */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_BIG_INT(0) } }, 17298 /*mxcsr:in */ X86_MXCSR_RC_UP, /* rounding mode affirmed by instruction */ 17299 /*128:out */ X86_MXCSR_RC_UP, 17300 /*256:out */ X86_MXCSR_RC_UP }, 17301 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17302 { /*unused */ { FP64_ROW_UNUSED } }, 17303 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_BIG_INT(1) } }, 17304 /*mxcsr:in */ X86_MXCSR_RC_UP, /* rounding mode affirmed by instruction */ 17305 /*128:out */ X86_MXCSR_RC_UP, 17306 /*256:out */ X86_MXCSR_RC_UP }, 17307 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17308 { /*unused */ { FP64_ROW_UNUSED } }, 17309 { /* => */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_BIG_INT(0) } }, 17310 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17311 /*128:out */ X86_MXCSR_RC_ZERO, 17312 /*256:out */ X86_MXCSR_RC_ZERO }, 17313 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17314 { /*unused */ { FP64_ROW_UNUSED } }, 17315 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_BIG_INT(1) } }, 17316 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17317 /*128:out */ X86_MXCSR_RC_ZERO, 17318 /*256:out */ X86_MXCSR_RC_ZERO }, 17319 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17320 { /*unused */ { FP64_ROW_UNUSED } }, 17321 { /* => */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_2(1) } }, 17322 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17323 /*128:out */ X86_MXCSR_RC_DOWN, 17324 /*256:out */ X86_MXCSR_RC_DOWN }, 17325 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17326 { /*unused */ { FP64_ROW_UNUSED } }, 17327 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_2(0) } }, 17328 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17329 /*128:out */ X86_MXCSR_RC_DOWN, 17330 /*256:out */ X86_MXCSR_RC_DOWN }, 17331 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17332 { /*unused */ { FP64_ROW_UNUSED } }, 17333 { /* => */ { FP64_12_90_0(0), FP64_12_90_0(0), FP64_12_90_0(0), FP64_1(1) } }, 17334 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17335 /*128:out */ X86_MXCSR_RC_ZERO, 17336 /*256:out */ X86_MXCSR_RC_ZERO }, 17337 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17338 { /*unused */ { FP64_ROW_UNUSED } }, 17339 { /* => */ { FP64_12_89_0(1), FP64_12_89_0(1), FP64_12_89_0(1), FP64_1(0) } }, 17340 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17341 /*128:out */ X86_MXCSR_RC_ZERO, 17342 /*256:out */ X86_MXCSR_RC_ZERO }, 17343 }; 17344 /** quiet PE + round toward zero */ 17345 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesZR[] = 17346 { 17347 /* 17348 * Zero. 17349 */ 17350 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 17351 { /*unused */ { FP64_ROW_UNUSED } }, 17352 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 17353 /*mxcsr:in */ 0, 17354 /*128:out */ 0, 17355 /*256:out */ 0 }, 17356 /* 17357 * Normals. 17358 */ 17359 /* 1*/{ { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17360 { /*unused */ { FP64_ROW_UNUSED } }, 17361 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17362 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 17363 /*128:out */ X86_MXCSR_RC_NEAREST, 17364 /*256:out */ X86_MXCSR_RC_NEAREST }, 17365 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17366 { /*unused */ { FP64_ROW_UNUSED } }, 17367 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_BIG_INT(1) } }, 17368 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 17369 /*128:out */ X86_MXCSR_RC_NEAREST, 17370 /*256:out */ X86_MXCSR_RC_NEAREST }, 17371 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17372 { /*unused */ { FP64_ROW_UNUSED } }, 17373 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17374 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17375 /*128:out */ X86_MXCSR_RC_DOWN, 17376 /*256:out */ X86_MXCSR_RC_DOWN }, 17377 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17378 { /*unused */ { FP64_ROW_UNUSED } }, 17379 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_BIG_INT(1) } }, 17380 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17381 /*128:out */ X86_MXCSR_RC_DOWN, 17382 /*256:out */ X86_MXCSR_RC_DOWN }, 17383 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17384 { /*unused */ { FP64_ROW_UNUSED } }, 17385 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17386 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17387 /*128:out */ X86_MXCSR_RC_UP, 17388 /*256:out */ X86_MXCSR_RC_UP }, 17389 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17390 { /*unused */ { FP64_ROW_UNUSED } }, 17391 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_BIG_INT(1) } }, 17392 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17393 /*128:out */ X86_MXCSR_RC_UP, 17394 /*256:out */ X86_MXCSR_RC_UP }, 17395 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17396 { /*unused */ { FP64_ROW_UNUSED } }, 17397 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17398 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* rounding mode affirmed by instruction */ 17399 /*128:out */ X86_MXCSR_RC_ZERO, 17400 /*256:out */ X86_MXCSR_RC_ZERO }, 17401 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17402 { /*unused */ { FP64_ROW_UNUSED } }, 17403 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_BIG_INT(1) } }, 17404 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* rounding mode affirmed by instruction */ 17405 /*128:out */ X86_MXCSR_RC_ZERO, 17406 /*256:out */ X86_MXCSR_RC_ZERO }, 17407 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17408 { /*unused */ { FP64_ROW_UNUSED } }, 17409 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_2(1) } }, 17410 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 17411 /*128:out */ X86_MXCSR_RC_NEAREST, 17412 /*256:out */ X86_MXCSR_RC_NEAREST }, 17413 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17414 { /*unused */ { FP64_ROW_UNUSED } }, 17415 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_2(0) } }, 17416 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* MXCSR overridden by instruction */ 17417 /*128:out */ X86_MXCSR_RC_NEAREST, 17418 /*256:out */ X86_MXCSR_RC_NEAREST }, 17419 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17420 { /*unused */ { FP64_ROW_UNUSED } }, 17421 { /* => */ { FP64_12_89_0(0), FP64_12_89_0(0), FP64_12_89_0(0), FP64_1(1) } }, 17422 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17423 /*128:out */ X86_MXCSR_RC_UP, 17424 /*256:out */ X86_MXCSR_RC_UP }, 17425 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17426 { /*unused */ { FP64_ROW_UNUSED } }, 17427 { /* => */ { FP64_12_89_0(1), FP64_12_89_0(1), FP64_12_89_0(1), FP64_1(0) } }, 17428 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17429 /*128:out */ X86_MXCSR_RC_UP, 17430 /*256:out */ X86_MXCSR_RC_UP }, 16615 17431 }; 16616 17432 /** quiet PE + rounding controlled by MXCSR */ 16617 17433 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesMX[] = 16618 17434 { 16619 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17435 /* 17436 * Zero. 17437 */ 17438 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 16620 17439 { /*unused */ { FP64_ROW_UNUSED } }, 16621 { /* => */ { FP64_0(0), FP64_0(1) } },17440 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 16622 17441 /*mxcsr:in */ 0, 16623 17442 /*128:out */ 0, 16624 17443 /*256:out */ 0 }, 17444 /* 17445 * Normals. 17446 */ 17447 /* 1*/{ { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17448 { /*unused */ { FP64_ROW_UNUSED } }, 17449 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_BIG_INT(0) } }, 17450 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 17451 /*128:out */ X86_MXCSR_RC_NEAREST, 17452 /*256:out */ X86_MXCSR_RC_NEAREST }, 17453 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17454 { /*unused */ { FP64_ROW_UNUSED } }, 17455 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_BIG_INT(1) } }, 17456 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 17457 /*128:out */ X86_MXCSR_RC_NEAREST, 17458 /*256:out */ X86_MXCSR_RC_NEAREST }, 17459 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17460 { /*unused */ { FP64_ROW_UNUSED } }, 17461 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17462 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 17463 /*128:out */ X86_MXCSR_RC_DOWN, 17464 /*256:out */ X86_MXCSR_RC_DOWN }, 17465 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17466 { /*unused */ { FP64_ROW_UNUSED } }, 17467 { /* => */ { FP64_1(1), FP64_1(1), FP64_1(1), FP64_BIG_INT(1) } }, 17468 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 17469 /*128:out */ X86_MXCSR_RC_DOWN, 17470 /*256:out */ X86_MXCSR_RC_DOWN }, 17471 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17472 { /*unused */ { FP64_ROW_UNUSED } }, 17473 { /* => */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_BIG_INT(0) } }, 17474 /*mxcsr:in */ X86_MXCSR_RC_UP, 17475 /*128:out */ X86_MXCSR_RC_UP, 17476 /*256:out */ X86_MXCSR_RC_UP }, 17477 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17478 { /*unused */ { FP64_ROW_UNUSED } }, 17479 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_BIG_INT(1) } }, 17480 /*mxcsr:in */ X86_MXCSR_RC_UP, 17481 /*128:out */ X86_MXCSR_RC_UP, 17482 /*256:out */ X86_MXCSR_RC_UP }, 17483 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17484 { /*unused */ { FP64_ROW_UNUSED } }, 17485 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17486 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 17487 /*128:out */ X86_MXCSR_RC_ZERO, 17488 /*256:out */ X86_MXCSR_RC_ZERO }, 17489 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17490 { /*unused */ { FP64_ROW_UNUSED } }, 17491 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_BIG_INT(1) } }, 17492 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 17493 /*128:out */ X86_MXCSR_RC_ZERO, 17494 /*256:out */ X86_MXCSR_RC_ZERO }, 17495 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17496 { /*unused */ { FP64_ROW_UNUSED } }, 17497 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_2(1) } }, 17498 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 17499 /*128:out */ X86_MXCSR_RC_NEAREST, 17500 /*256:out */ X86_MXCSR_RC_NEAREST }, 17501 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17502 { /*unused */ { FP64_ROW_UNUSED } }, 17503 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_2(0) } }, 17504 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 17505 /*128:out */ X86_MXCSR_RC_NEAREST, 17506 /*256:out */ X86_MXCSR_RC_NEAREST }, 17507 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17508 { /*unused */ { FP64_ROW_UNUSED } }, 17509 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_2(1) } }, 17510 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 17511 /*128:out */ X86_MXCSR_RC_DOWN, 17512 /*256:out */ X86_MXCSR_RC_DOWN }, 17513 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17514 { /*unused */ { FP64_ROW_UNUSED } }, 17515 { /* => */ { FP64_1(1), FP64_1(1), FP64_1(1), FP64_2(0) } }, 17516 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 17517 /*128:out */ X86_MXCSR_RC_DOWN, 17518 /*256:out */ X86_MXCSR_RC_DOWN }, 17519 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17520 { /*unused */ { FP64_ROW_UNUSED } }, 17521 { /* => */ { FP64_1(0), FP64_1(0), FP64_1(0), FP64_2(1) } }, 17522 /*mxcsr:in */ X86_MXCSR_RC_UP, 17523 /*128:out */ X86_MXCSR_RC_UP, 17524 /*256:out */ X86_MXCSR_RC_UP }, 17525 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17526 { /*unused */ { FP64_ROW_UNUSED } }, 17527 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_2(0) } }, 17528 /*mxcsr:in */ X86_MXCSR_RC_UP, 17529 /*128:out */ X86_MXCSR_RC_UP, 17530 /*256:out */ X86_MXCSR_RC_UP }, 17531 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17532 { /*unused */ { FP64_ROW_UNUSED } }, 17533 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_2(1) } }, 17534 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 17535 /*128:out */ X86_MXCSR_RC_ZERO, 17536 /*256:out */ X86_MXCSR_RC_ZERO }, 17537 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17538 { /*unused */ { FP64_ROW_UNUSED } }, 17539 { /* => */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_2(0) } }, 17540 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 17541 /*128:out */ X86_MXCSR_RC_ZERO, 17542 /*256:out */ X86_MXCSR_RC_ZERO }, 17543 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17544 { /*unused */ { FP64_ROW_UNUSED } }, 17545 { /* => */ { FP64_12_89_0(0), FP64_12_90_0(0), FP64_12_90_0(0), FP64_1(1) } }, 17546 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 17547 /*128:out */ X86_MXCSR_RC_NEAREST, 17548 /*256:out */ X86_MXCSR_RC_NEAREST }, 17549 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17550 { /*unused */ { FP64_ROW_UNUSED } }, 17551 { /* => */ { FP64_12_89_0(1), FP64_12_90_0(1), FP64_12_90_0(1), FP64_1(0) } }, 17552 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 17553 /*128:out */ X86_MXCSR_RC_NEAREST, 17554 /*256:out */ X86_MXCSR_RC_NEAREST }, 17555 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17556 { /*unused */ { FP64_ROW_UNUSED } }, 17557 { /* => */ { FP64_12_89_0(0), FP64_12_89_0(0), FP64_12_89_0(0), FP64_1(1) } }, 17558 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 17559 /*128:out */ X86_MXCSR_RC_DOWN, 17560 /*256:out */ X86_MXCSR_RC_DOWN }, 17561 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17562 { /*unused */ { FP64_ROW_UNUSED } }, 17563 { /* => */ { FP64_12_90_0(1), FP64_12_90_0(1), FP64_12_90_0(1), FP64_1(0) } }, 17564 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 17565 /*128:out */ X86_MXCSR_RC_DOWN, 17566 /*256:out */ X86_MXCSR_RC_DOWN }, 17567 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17568 { /*unused */ { FP64_ROW_UNUSED } }, 17569 { /* => */ { FP64_12_90_0(0), FP64_12_90_0(0), FP64_12_90_0(0), FP64_1(1) } }, 17570 /*mxcsr:in */ X86_MXCSR_RC_UP, 17571 /*128:out */ X86_MXCSR_RC_UP, 17572 /*256:out */ X86_MXCSR_RC_UP }, 17573 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17574 { /*unused */ { FP64_ROW_UNUSED } }, 17575 { /* => */ { FP64_12_89_0(1), FP64_12_89_0(1), FP64_12_89_0(1), FP64_1(0) } }, 17576 /*mxcsr:in */ X86_MXCSR_RC_UP, 17577 /*128:out */ X86_MXCSR_RC_UP, 17578 /*256:out */ X86_MXCSR_RC_UP }, 17579 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17580 { /*unused */ { FP64_ROW_UNUSED } }, 17581 { /* => */ { FP64_12_89_0(0), FP64_12_89_0(0), FP64_12_89_0(0), FP64_1(1) } }, 17582 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 17583 /*128:out */ X86_MXCSR_RC_ZERO, 17584 /*256:out */ X86_MXCSR_RC_ZERO }, 17585 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17586 { /*unused */ { FP64_ROW_UNUSED } }, 17587 { /* => */ { FP64_12_89_0(1), FP64_12_89_0(1), FP64_12_89_0(1), FP64_1(0) } }, 17588 /*mxcsr:in */ X86_MXCSR_RC_ZERO, 17589 /*128:out */ X86_MXCSR_RC_ZERO, 17590 /*256:out */ X86_MXCSR_RC_ZERO }, 16625 17591 }; 16626 /** quiet PE + round toward negative infinity */ 16627 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNI[] = 16628 { 16629 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 16630 { /*unused */ { FP64_ROW_UNUSED } }, 16631 { /* => */ { FP64_0(0), FP64_0(1) } }, 16632 /*mxcsr:in */ 0, 16633 /*128:out */ 0, 16634 /*256:out */ 0 }, 16635 }; 16636 /** quiet PE + round toward positive infinity */ 16637 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesPI[] = 16638 { 16639 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 16640 { /*unused */ { FP64_ROW_UNUSED } }, 16641 { /* => */ { FP64_0(0), FP64_0(1) } }, 16642 /*mxcsr:in */ 0, 16643 /*128:out */ 0, 16644 /*256:out */ 0 }, 16645 }; 16646 /** raise PE + round toward nearest even */ 17592 /** raise PE + round toward nearest (even) */ 16647 17593 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesPE[] = 16648 17594 { 16649 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17595 /* 17596 * Zero. 17597 */ 17598 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 16650 17599 { /*unused */ { FP64_ROW_UNUSED } }, 16651 { /* => */ { FP64_0(0), FP64_0(1) } },17600 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 16652 17601 /*mxcsr:in */ 0, 16653 17602 /*128:out */ 0, 16654 17603 /*256:out */ 0 }, 17604 /* 17605 * Normals & Precision. 17606 */ 17607 /* 1*/{ { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17608 { /*unused */ { FP64_ROW_UNUSED } }, 17609 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_BIG_INT(0) } }, 17610 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17611 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 17612 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN }, 17613 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17614 { /*unused */ { FP64_ROW_UNUSED } }, 17615 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_BIG_INT(1) } }, 17616 /*mxcsr:in */ X86_MXCSR_RC_DOWN, /* MXCSR overridden by instruction */ 17617 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN, 17618 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_DOWN }, 17619 { { /*src1 */ { FP64_0_5_DN(0), FP64_0_5(0), FP64_0_5_UP(0), FP64_2(1) } }, 17620 { /*unused */ { FP64_ROW_UNUSED } }, 17621 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_2(1) } }, 17622 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17623 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP, 17624 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP }, 17625 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_2(0) } }, 17626 { /*unused */ { FP64_ROW_UNUSED } }, 17627 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_2(0) } }, 17628 /*mxcsr:in */ X86_MXCSR_RC_UP, /* MXCSR overridden by instruction */ 17629 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP, 17630 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_UP }, 17631 { { /*src1 */ { FP64_12_89_1(0), FP64_12_89_5(0), FP64_12_89_9(0), FP64_1(1) } }, 17632 { /*unused */ { FP64_ROW_UNUSED } }, 17633 { /* => */ { FP64_12_89_0(0), FP64_12_90_0(0), FP64_12_90_0(0), FP64_1(1) } }, 17634 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17635 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 17636 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO }, 17637 { { /*src1 */ { FP64_12_89_1(1), FP64_12_89_5(1), FP64_12_89_9(1), FP64_1(0) } }, 17638 { /*unused */ { FP64_ROW_UNUSED } }, 17639 { /* => */ { FP64_12_89_0(1), FP64_12_90_0(1), FP64_12_90_0(1), FP64_1(0) } }, 17640 /*mxcsr:in */ X86_MXCSR_RC_ZERO, /* MXCSR overridden by instruction */ 17641 /*128:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO, 17642 /*256:out */ X86_MXCSR_PE | X86_MXCSR_RC_ZERO }, 17643 { { /*src1 */ { FP64_12_89_0(0), FP64_12_90_0(0), FP64_2(0), FP64_BIG_INT(1) } }, 17644 { /*unused */ { FP64_ROW_UNUSED } }, 17645 { /* => */ { FP64_12_89_0(0), FP64_12_90_0(0), FP64_2(0), FP64_BIG_INT(1) } }, 17646 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 17647 /*128:out */ X86_MXCSR_RC_NEAREST, 17648 /*256:out */ X86_MXCSR_RC_NEAREST }, 17649 { { /*src1 */ { FP64_12_89_0(1), FP64_12_90_0(1), FP64_2(1), FP64_BIG_INT(0) } }, 17650 { /*unused */ { FP64_ROW_UNUSED } }, 17651 { /* => */ { FP64_12_89_0(1), FP64_12_90_0(1), FP64_2(1), FP64_BIG_INT(0) } }, 17652 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, /* rounding mode affirmed by instruction */ 17653 /*128:out */ X86_MXCSR_RC_NEAREST, 17654 /*256:out */ X86_MXCSR_RC_NEAREST }, 16655 17655 }; 16656 /** quiet PE + round toward zero */ 16657 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesZR[] = 16658 { 16659 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 16660 { /*unused */ { FP64_ROW_UNUSED } }, 16661 { /* => */ { FP64_0(0), FP64_0(1) } }, 16662 /*mxcsr:in */ 0, 16663 /*128:out */ 0, 16664 /*256:out */ 0 }, 16665 }; 16666 /** quiet PE + rounding controlled by MXCSR (invalid encoding) */ 17656 /** quiet PE + rounding controlled by MXCSR (reserved encoding) */ 16667 17657 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNV[] = 16668 17658 { 16669 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1) } }, 17659 /* 17660 * Zero. 17661 */ 17662 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 16670 17663 { /*unused */ { FP64_ROW_UNUSED } }, 16671 { /* => */ { FP64_0(0), FP64_0(1) } },17664 { /* => */ { FP64_0(0), FP64_0(1), FP64_0(1), FP64_0(0) } }, 16672 17665 /*mxcsr:in */ 0, 16673 17666 /*128:out */ 0, 16674 17667 /*256:out */ 0 }, 17668 /* 17669 * Normals. 17670 */ 17671 /* 1*/{ { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17672 { /*unused */ { FP64_ROW_UNUSED } }, 17673 { /* => */ { FP64_0(0), FP64_0(0), FP64_1(0), FP64_BIG_INT(0) } }, 17674 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 17675 /*128:out */ X86_MXCSR_RC_NEAREST, 17676 /*256:out */ X86_MXCSR_RC_NEAREST }, 17677 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17678 { /*unused */ { FP64_ROW_UNUSED } }, 17679 { /* => */ { FP64_0(1), FP64_0(1), FP64_1(1), FP64_BIG_INT(1) } }, 17680 /*mxcsr:in */ X86_MXCSR_RC_NEAREST, 17681 /*128:out */ X86_MXCSR_RC_NEAREST, 17682 /*256:out */ X86_MXCSR_RC_NEAREST }, 17683 { { /*src1 */ { FP64_0_1(0), FP64_0_5(0), FP64_0_9(0), FP64_BIG_INT(0) } }, 17684 { /*unused */ { FP64_ROW_UNUSED } }, 17685 { /* => */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_BIG_INT(0) } }, 17686 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 17687 /*128:out */ X86_MXCSR_RC_DOWN, 17688 /*256:out */ X86_MXCSR_RC_DOWN }, 17689 { { /*src1 */ { FP64_0_1(1), FP64_0_5(1), FP64_0_9(1), FP64_BIG_INT(1) } }, 17690 { /*unused */ { FP64_ROW_UNUSED } }, 17691 { /* => */ { FP64_1(1), FP64_1(1), FP64_1(1), FP64_BIG_INT(1) } }, 17692 /*mxcsr:in */ X86_MXCSR_RC_DOWN, 17693 /*128:out */ X86_MXCSR_RC_DOWN, 17694 /*256:out */ X86_MXCSR_RC_DOWN }, 16675 17695 }; 16676 17696 … … 16730 17750 16731 17751 17752 typedef struct BS3CPUINSTR4_ROUNDSS_VALUES_T 17753 { 17754 RTFLOAT32U uSrc; 17755 RTFLOAT32U uDst; 17756 uint16_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ 17757 uint16_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 17758 } BS3CPUINSTR4_ROUNDSS_VALUES_T; 17759 17760 static DECLCALLBACK(PBS3CPUINSTR4_TEST1_VALUES_T) bs3CpuInstr4_WorkerTestType1_Provider_roundss(void *paValues, const unsigned cValues, const unsigned iVal) 17761 { 17762 static BS3CPUINSTR4_TEST1_VALUES_PS_T sValues; 17763 BS3CPUINSTR4_ROUNDSS_VALUES_T *psValuesIn = &((BS3CPUINSTR4_ROUNDSS_VALUES_T *)paValues)[iVal]; 17764 unsigned iCnt; 17765 17766 sValues.uSrc1.ar32[0] = psValuesIn->uSrc; 17767 sValues.uSrc2.ar32[0] = psValuesIn->uSrc; 17768 sValues.uDstOut.ar32[0] = psValuesIn->uDst; 17769 for (iCnt = 1; iCnt < RT_ELEMENTS(sValues.uSrc1.ymm.au32); iCnt++) 17770 { 17771 sValues.uSrc1.ymm.au32[iCnt] = bs3CpuInstrX_SimpleRand(); 17772 sValues.uSrc2.ymm.au32[iCnt] = bs3CpuInstrX_SimpleRand(); 17773 sValues.uDstOut.ymm.au32[iCnt] = sValues.uSrc1.ymm.au32[iCnt]; 17774 } 17775 sValues.uMxCsr = psValuesIn->uMxCsr; 17776 sValues.u128ExpectedMxCsr = psValuesIn->u128ExpectedMxCsr; 17777 return (PBS3CPUINSTR4_TEST1_VALUES_T)&sValues; 17778 } 17779 16732 17780 /* 16733 17781 * [V]ROUNDSS. … … 16735 17783 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_roundss(uint8_t bMode) 16736 17784 { 16737 /** quiet PE + round toward nearest even*/16738 static BS3CPUINSTR4_ TEST1_VALUES_PS_T const s_aValuesNE[] =17785 /** quiet PE + round toward nearest (even) + main testing + plenty of testing instruction-overrides-MXCSR */ 17786 static BS3CPUINSTR4_ROUNDSS_VALUES_T const s_aValuesNE[] = 16739 17787 { 16740 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 16741 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 16742 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 16743 /*mxcsr:in */ 0, 16744 /*128:out */ 0, 16745 /*256:out */ 0 }, 16746 { { /*src1 */ { FP32_0(1), FP32_RAND_x7_V2 } }, 16747 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 16748 { /* => */ { FP32_0(1), FP32_RAND_x7_V3 } }, 16749 /*mxcsr:in */ 0, 16750 /*128:out */ 0, 16751 /*256:out */ 0 }, 17788 /*src*/ /* => */ /*mxcsr:in*/ /*128:out*/ 17789 /* 17790 * Zero. 17791 */ 17792 /* 0*/{ FP32_0(0), FP32_0(0), 0, 0 }, 17793 { FP32_0(1), FP32_0(1), 0, 0 }, 17794 /* 17795 * Infinity. 17796 */ 17797 /* 2*/{ FP32_INF(0), FP32_INF(0), 0, 0 }, 17798 { FP32_INF(1), FP32_INF(1), 0, 0 }, 17799 /* 17800 * Normals. 17801 */ 17802 /* 4*/{ FP32_0_1(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17803 { FP32_0_1(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17804 { FP32_0_1(1), FP32_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17805 { FP32_0_1(1), FP32_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17806 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17807 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17808 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17809 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17810 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17811 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17812 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17813 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17814 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17815 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17816 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17817 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17818 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17819 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17820 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17821 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17822 { FP32_0_9(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17823 { FP32_0_9(0), FP32_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17824 { FP32_0_9(1), FP32_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17825 { FP32_0_9(1), FP32_1(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17826 { FP32_1(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17827 { FP32_1(1), FP32_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17828 { FP32_12_67_1(0), FP32_12_67_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17829 { FP32_12_67_1(0), FP32_12_67_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17830 { FP32_12_67_1(1), FP32_12_67_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17831 { FP32_12_67_1(1), FP32_12_67_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17832 { FP32_12_67_5(0), FP32_12_68_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17833 { FP32_12_67_5(0), FP32_12_68_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17834 { FP32_12_67_5(1), FP32_12_68_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17835 { FP32_12_67_5(1), FP32_12_68_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17836 { FP32_12_67_9(0), FP32_12_68_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17837 { FP32_12_67_9(0), FP32_12_68_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17838 { FP32_12_67_9(1), FP32_12_68_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17839 { FP32_12_67_9(1), FP32_12_68_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17840 { FP32_2(0), FP32_2(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17841 { FP32_2(0), FP32_2(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17842 { FP32_2(1), FP32_2(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17843 { FP32_2(1), FP32_2(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17844 { FP32_BIG_INT(0), FP32_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17845 { FP32_BIG_INT(1), FP32_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17846 }; 17847 /** quiet PE + round toward negative infinity */ 17848 static BS3CPUINSTR4_ROUNDSS_VALUES_T const s_aValuesNI[] = 17849 { 17850 /* 17851 * Normals. 17852 */ 17853 /* 0*/{ FP32_0_1(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17854 { FP32_0_1(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17855 { FP32_0_1(1), FP32_1(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17856 { FP32_0_1(1), FP32_1(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17857 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17858 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17859 { FP32_0_5(1), FP32_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17860 { FP32_0_5(1), FP32_1(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17861 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17862 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17863 { FP32_0_5_UP(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17864 { FP32_0_5_UP(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17865 { FP32_0_9(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17866 { FP32_0_9(1), FP32_1(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17867 { FP32_1(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17868 { FP32_1(1), FP32_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17869 { FP32_12_67_1(0), FP32_12_67_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17870 { FP32_12_67_1(1), FP32_12_68_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17871 { FP32_12_67_5(0), FP32_12_67_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17872 { FP32_12_67_5(1), FP32_12_68_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17873 { FP32_12_67_9(0), FP32_12_67_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17874 { FP32_12_67_9(1), FP32_12_68_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP, }, /* MXCSR overridden by instruction */ 17875 { FP32_2(0), FP32_2(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17876 { FP32_2(1), FP32_2(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17877 { FP32_BIG_INT(0), FP32_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17878 { FP32_BIG_INT(1), FP32_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17879 }; 17880 /** quiet PE + round toward positive infinity */ 17881 static BS3CPUINSTR4_ROUNDSS_VALUES_T const s_aValuesPI[] = 17882 { 17883 /* 17884 * Normals. 17885 */ 17886 /* 0*/{ FP32_0_1(0), FP32_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17887 { FP32_0_1(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17888 { FP32_0_1(1), FP32_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17889 { FP32_0_1(1), FP32_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17890 { FP32_0_5(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17891 { FP32_0_5(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17892 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17893 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17894 { FP32_0_5_DN(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17895 { FP32_0_5_DN(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17896 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17897 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17898 { FP32_0_9(0), FP32_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17899 { FP32_0_9(1), FP32_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17900 { FP32_1(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17901 { FP32_1(1), FP32_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17902 { FP32_12_67_1(0), FP32_12_68_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17903 { FP32_12_67_1(1), FP32_12_67_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17904 { FP32_12_67_5(0), FP32_12_68_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17905 { FP32_12_67_5(1), FP32_12_67_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 17906 { FP32_12_67_9(0), FP32_12_68_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17907 { FP32_12_67_9(1), FP32_12_67_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17908 { FP32_2(0), FP32_2(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17909 { FP32_2(1), FP32_2(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17910 { FP32_BIG_INT(0), FP32_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17911 { FP32_BIG_INT(1), FP32_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17912 }; 17913 /** quiet PE + round toward zero */ 17914 static BS3CPUINSTR4_ROUNDSS_VALUES_T const s_aValuesZR[] = 17915 { 17916 /* 17917 * Normals. 17918 */ 17919 /* 0*/{ FP32_0_1(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17920 { FP32_0_1(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17921 { FP32_0_1(1), FP32_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17922 { FP32_0_1(1), FP32_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17923 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17924 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17925 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17926 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17927 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17928 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17929 { FP32_0_5_UP(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17930 { FP32_0_5_UP(0), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17931 { FP32_0_9(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17932 { FP32_0_9(1), FP32_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17933 { FP32_1(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17934 { FP32_1(1), FP32_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17935 { FP32_12_67_1(0), FP32_12_67_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17936 { FP32_12_67_1(1), FP32_12_67_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17937 { FP32_12_67_5(0), FP32_12_67_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17938 { FP32_12_67_5(1), FP32_12_67_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17939 { FP32_12_67_9(0), FP32_12_67_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17940 { FP32_12_67_9(1), FP32_12_67_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 17941 { FP32_2(0), FP32_2(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 17942 { FP32_2(1), FP32_2(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17943 { FP32_BIG_INT(0), FP32_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 17944 { FP32_BIG_INT(1), FP32_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 16752 17945 }; 16753 17946 /** quiet PE + rounding controlled by MXCSR */ 16754 static BS3CPUINSTR4_ TEST1_VALUES_PS_T const s_aValuesMX[] =17947 static BS3CPUINSTR4_ROUNDSS_VALUES_T const s_aValuesMX[] = 16755 17948 { 16756 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 16757 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 16758 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 16759 /*mxcsr:in */ 0, 16760 /*128:out */ 0, 16761 /*256:out */ 0 }, 17949 /* 17950 * Normals. 17951 */ 17952 /* 0*/{ FP32_0_1(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17953 { FP32_0_1(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17954 { FP32_0_1(1), FP32_1(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17955 { FP32_0_1(1), FP32_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17956 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17957 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17958 { FP32_0_5(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17959 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17960 { FP32_0_5(1), FP32_1(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17961 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17962 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17963 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17964 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17965 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17966 { FP32_0_5_DN(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17967 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17968 { FP32_0_5_UP(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17969 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17970 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17971 { FP32_0_5_UP(0), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17972 { FP32_0_9(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17973 { FP32_0_9(0), FP32_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17974 { FP32_0_9(1), FP32_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17975 { FP32_0_9(1), FP32_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17976 { FP32_1(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17977 { FP32_1(1), FP32_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17978 { FP32_12_67_1(0), FP32_12_67_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17979 { FP32_12_67_1(0), FP32_12_68_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17980 { FP32_12_67_1(1), FP32_12_68_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17981 { FP32_12_67_1(1), FP32_12_67_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17982 { FP32_12_67_5(0), FP32_12_68_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17983 { FP32_12_67_5(0), FP32_12_67_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17984 { FP32_12_67_5(1), FP32_12_68_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17985 { FP32_12_67_5(1), FP32_12_67_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17986 { FP32_12_67_9(0), FP32_12_67_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17987 { FP32_12_67_9(0), FP32_12_68_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17988 { FP32_12_67_9(1), FP32_12_68_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 17989 { FP32_12_67_9(1), FP32_12_68_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17990 { FP32_2(0), FP32_2(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17991 { FP32_2(0), FP32_2(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 17992 { FP32_2(1), FP32_2(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17993 { FP32_2(1), FP32_2(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 17994 { FP32_BIG_INT(0), FP32_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 17995 { FP32_BIG_INT(1), FP32_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 16762 17996 }; 16763 /** quiet PE + round toward negative infinity*/16764 static BS3CPUINSTR4_ TEST1_VALUES_PS_T const s_aValuesNI[] =17997 /** raise PE + round toward nearest (even) */ 17998 static BS3CPUINSTR4_ROUNDSS_VALUES_T const s_aValuesPE[] = 16765 17999 { 16766 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 16767 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 16768 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 16769 /*mxcsr:in */ 0, 16770 /*128:out */ 0, 16771 /*256:out */ 0 }, 18000 /* 18001 * Normals. 18002 */ 18003 /* 0*/{ FP32_0_1(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18004 { FP32_0_1(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18005 { FP32_0_1(1), FP32_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18006 { FP32_0_1(1), FP32_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18007 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18008 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18009 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18010 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18011 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18012 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18013 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18014 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18015 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18016 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18017 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18018 { FP32_0_5_DN(0), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18019 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18020 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18021 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18022 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18023 { FP32_0_9(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18024 { FP32_0_9(0), FP32_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18025 { FP32_0_9(1), FP32_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18026 { FP32_0_9(1), FP32_1(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18027 { FP32_1(0), FP32_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18028 { FP32_1(1), FP32_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18029 { FP32_12_67_1(0), FP32_12_67_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18030 { FP32_12_67_1(0), FP32_12_67_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18031 { FP32_12_67_1(1), FP32_12_67_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18032 { FP32_12_67_1(1), FP32_12_67_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18033 { FP32_12_67_5(0), FP32_12_68_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18034 { FP32_12_67_5(0), FP32_12_68_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18035 { FP32_12_67_5(1), FP32_12_68_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18036 { FP32_12_67_5(1), FP32_12_68_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18037 { FP32_12_67_9(0), FP32_12_68_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18038 { FP32_12_67_9(0), FP32_12_68_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18039 { FP32_12_67_9(1), FP32_12_68_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18040 { FP32_12_67_9(1), FP32_12_68_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18041 { FP32_2(0), FP32_2(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18042 { FP32_2(0), FP32_2(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18043 { FP32_2(1), FP32_2(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18044 { FP32_2(1), FP32_2(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18045 { FP32_BIG_INT(0), FP32_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18046 { FP32_BIG_INT(1), FP32_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 16772 18047 }; 16773 /** quiet PE + round toward positive infinity*/16774 static BS3CPUINSTR4_ TEST1_VALUES_PS_T const s_aValuesPI[] =18048 /** quiet PE + rounding controlled by MXCSR (reserved encoding) */ 18049 static BS3CPUINSTR4_ROUNDSS_VALUES_T const s_aValuesNV[] = 16775 18050 { 16776 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 16777 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 16778 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 16779 /*mxcsr:in */ 0, 16780 /*128:out */ 0, 16781 /*256:out */ 0 }, 16782 }; 16783 /** raise PE + round toward nearest even */ 16784 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesPE[] = 16785 { 16786 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 16787 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 16788 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 16789 /*mxcsr:in */ 0, 16790 /*128:out */ 0, 16791 /*256:out */ 0 }, 16792 }; 16793 /** quiet PE + round toward zero */ 16794 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesZR[] = 16795 { 16796 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 16797 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 16798 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 16799 /*mxcsr:in */ 0, 16800 /*128:out */ 0, 16801 /*256:out */ 0 }, 16802 }; 16803 /** quiet PE + rounding controlled by MXCSR (invalid encoding) */ 16804 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesNV[] = 16805 { 16806 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 16807 { /*src2 */ { FP32_2(1), FP32_RAND_x7_V3 } }, 16808 { /* => */ { FP32_0(0), FP32_RAND_x7_V3 } }, 16809 /*mxcsr:in */ 0, 16810 /*128:out */ 0, 16811 /*256:out */ 0 }, 16812 }; 16813 /** quiet PE + round toward nearest even + same-register */ 16814 static BS3CPUINSTR4_TEST1_VALUES_PS_T const s_aValuesSR[] = 16815 { 16816 /* 0*/{ { /*src1 */ { FP32_0(0), FP32_RAND_x7_V2 } }, 16817 { /*src2 */ { FP32_ROW_UNUSED } }, 16818 { /* => */ { FP32_0(0), FP32_RAND_x7_V2 } }, 16819 /*mxcsr:in */ 0, 16820 /*128:out */ 0, 16821 /*256:out */ 0 }, 18051 /* 18052 * Normals. 18053 */ 18054 /* 0*/{ FP32_0_1(0), FP32_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18055 { FP32_0_5(0), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18056 { FP32_0_5(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18057 { FP32_0_5(1), FP32_1(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18058 { FP32_0_5(1), FP32_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18059 { FP32_0_5_DN(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18060 { FP32_0_5_UP(0), FP32_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18061 { FP32_12_67_5(0), FP32_12_67_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18062 { FP32_2(0), FP32_2(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 16822 18063 }; 16823 18064 16824 18065 static BS3CPUINSTR4_TEST1_T const s_aTests[] = 16825 18066 { 16826 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_000h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16827 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_008h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16828 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_009h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16829 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00ah), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16830 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00bh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16831 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00ch), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16832 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00dh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16833 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00eh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16834 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00fh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16835 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_0ffh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16836 { BS3_INSTR4_ALL(roundss_XMM1_FSxBX_008h), 255, RM_MEM, T_SSE4_1, XMM1, XMM1, 16837 { BS3_INSTR4_C64(roundss_XMM8_XMM9_008h), 255, RM_REG, T_SSE4_1, XMM8, XMM8, 16838 { BS3_INSTR4_C64(roundss_XMM8_FSxBX_008h), 255, RM_MEM, T_SSE4_1, XMM8, XMM8, 16839 16840 { BS3_INSTR4_ALL(vroundss_XMM1_XMM1_XMM2_008h), 255, RM_REG, T_AVX_128, XMM1, XMM1, 16841 { BS3_INSTR4_ALL(vroundss_XMM1_XMM1_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM1, XMM1, 16842 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM1_008h), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16843 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_000h), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16844 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_008h), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16845 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_009h), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16846 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00ah), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16847 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00bh), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16848 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00ch), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16849 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00dh), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16850 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00eh), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16851 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00fh), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16852 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_0ffh), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16853 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM1, XMM2, 16854 { BS3_INSTR4_C64(vroundss_XMM8_XMM8_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM8, XMM8, 16855 { BS3_INSTR4_C64(vroundss_XMM8_XMM9_XMM10_008h), 255, RM_REG, T_AVX_128, XMM8, XMM9, 16856 { BS3_INSTR4_C64(vroundss_XMM8_XMM9_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM8, XMM9, 16857 16858 { BS3_INSTR4_ALL(roundss_XMM1_XMM1_008h), 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_TEST_ARRAY(s_aValuesSR) },16859 { BS3_INSTR4_C64(roundss_XMM8_XMM8_008h), 255, RM_REG, T_SSE4_1, XMM8, NOREG, XMM8, PASS_TEST_ARRAY(s_aValuesSR) },16860 { BS3_INSTR4_ALL(vroundss_XMM1_XMM1_XMM1_008h), 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_TEST_ARRAY(s_aValuesSR) },16861 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM2_008h), 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_TEST_ARRAY(s_aValuesSR) },16862 { BS3_INSTR4_C64(vroundss_XMM8_XMM8_XMM8_008h), 255, RM_REG, T_AVX_128, XMM8, NOREG, XMM8, PASS_TEST_ARRAY(s_aValuesSR) },18067 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_000h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesPE) }, 18068 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_008h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesNE) }, 18069 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_009h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesNI) }, 18070 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00ah), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesPI) }, 18071 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00bh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesZR) }, 18072 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00ch), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesMX) }, 18073 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00dh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesMX) }, 18074 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00eh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesMX) }, 18075 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_00fh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesMX) }, 18076 { BS3_INSTR4_ALL(roundss_XMM1_XMM2_0ffh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesNV) }, 18077 { BS3_INSTR4_ALL(roundss_XMM1_FSxBX_008h), 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18078 { BS3_INSTR4_C64(roundss_XMM8_XMM9_008h), 255, RM_REG, T_SSE4_1, XMM8, XMM8, XMM9, PASS_TEST_ARRAY(s_aValuesNE) }, 18079 { BS3_INSTR4_C64(roundss_XMM8_FSxBX_008h), 255, RM_MEM, T_SSE4_1, XMM8, XMM8, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18080 18081 { BS3_INSTR4_ALL(vroundss_XMM1_XMM1_XMM2_008h), 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesNE) }, 18082 { BS3_INSTR4_ALL(vroundss_XMM1_XMM1_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18083 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM1_008h), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesNE) }, 18084 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_000h), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesPE) }, 18085 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_008h), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesNE) }, 18086 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_009h), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesNI) }, 18087 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00ah), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesPI) }, 18088 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00bh), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesZR) }, 18089 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00ch), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesMX) }, 18090 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00dh), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesMX) }, 18091 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00eh), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesMX) }, 18092 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_00fh), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesMX) }, 18093 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM3_0ffh), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesNV) }, 18094 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18095 { BS3_INSTR4_C64(vroundss_XMM8_XMM8_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM8, XMM8, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18096 { BS3_INSTR4_C64(vroundss_XMM8_XMM9_XMM10_008h), 255, RM_REG, T_AVX_128, XMM8, XMM9, XMM10, PASS_TEST_ARRAY(s_aValuesNE) }, 18097 { BS3_INSTR4_C64(vroundss_XMM8_XMM9_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM8, XMM9, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18098 18099 { BS3_INSTR4_ALL(roundss_XMM1_XMM1_008h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, NOREG, PASS_TEST_ARRAY(s_aValuesNE) }, 18100 { BS3_INSTR4_C64(roundss_XMM8_XMM8_008h), 255, RM_REG, T_SSE4_1, XMM8, XMM8, NOREG, PASS_TEST_ARRAY(s_aValuesNE) }, 18101 { BS3_INSTR4_ALL(vroundss_XMM1_XMM1_XMM1_008h), 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_TEST_ARRAY(s_aValuesNE) }, 18102 { BS3_INSTR4_ALL(vroundss_XMM1_XMM2_XMM2_008h), 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_TEST_ARRAY(s_aValuesNE) }, 18103 { BS3_INSTR4_C64(vroundss_XMM8_XMM8_XMM8_008h), 255, RM_REG, T_AVX_128, XMM8, XMM8, NOREG, PASS_TEST_ARRAY(s_aValuesNE) }, 16863 18104 }; 16864 18105 16865 return bs3CpuInstr4_WorkerTestType1 (bMode, PASS_ARRAY(s_aTests), PASS_ARRAY(g_aXcptConfig3));18106 return bs3CpuInstr4_WorkerTestType1_P(bMode, PASS_ARRAY(s_aTests), PASS_ARRAY(g_aXcptConfig3), bs3CpuInstr4_WorkerTestType1_Provider_roundss); 16866 18107 } 16867 18108 18109 18110 typedef struct BS3CPUINSTR4_ROUNDSD_VALUES_T 18111 { 18112 RTFLOAT64U uSrc; 18113 RTFLOAT64U uDst; 18114 uint16_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ 18115 uint16_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 18116 } BS3CPUINSTR4_ROUNDSD_VALUES_T; 18117 18118 static DECLCALLBACK(PBS3CPUINSTR4_TEST1_VALUES_T) bs3CpuInstr4_WorkerTestType1_Provider_roundsd(void *paValues, const unsigned cValues, const unsigned iVal) 18119 { 18120 static BS3CPUINSTR4_TEST1_VALUES_PD_T sValues; 18121 BS3CPUINSTR4_ROUNDSD_VALUES_T *psValuesIn = &((BS3CPUINSTR4_ROUNDSD_VALUES_T *)paValues)[iVal]; 18122 unsigned iCnt; 18123 18124 sValues.uSrc1.ar64[0] = psValuesIn->uSrc; 18125 sValues.uSrc2.ar64[0] = psValuesIn->uSrc; 18126 sValues.uDstOut.ar64[0] = psValuesIn->uDst; 18127 for (iCnt = 2; iCnt < RT_ELEMENTS(sValues.uSrc1.ymm.au32); iCnt++) 18128 { 18129 sValues.uSrc1.ymm.au32[iCnt] = bs3CpuInstrX_SimpleRand(); 18130 sValues.uSrc2.ymm.au32[iCnt] = bs3CpuInstrX_SimpleRand(); 18131 sValues.uDstOut.ymm.au32[iCnt] = sValues.uSrc1.ymm.au32[iCnt]; 18132 } 18133 sValues.uMxCsr = psValuesIn->uMxCsr; 18134 sValues.u128ExpectedMxCsr = psValuesIn->u128ExpectedMxCsr; 18135 return (PBS3CPUINSTR4_TEST1_VALUES_T)&sValues; 18136 } 16868 18137 16869 18138 /* … … 16872 18141 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_roundsd(uint8_t bMode) 16873 18142 { 16874 /** quiet PE + round toward nearest even*/16875 static BS3CPUINSTR4_ TEST1_VALUES_PD_T const s_aValuesNE[] =18143 /** quiet PE + round toward nearest (even) + main testing + plenty of testing instruction-overrides-MXCSR */ 18144 static BS3CPUINSTR4_ROUNDSD_VALUES_T const s_aValuesNE[] = 16876 18145 { 16877 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 16878 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 16879 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 16880 /*mxcsr:in */ 0, 16881 /*128:out */ 0, 16882 /*256:out */ 0 }, 16883 { { /*src1 */ { FP64_0(1), FP64_RAND_V1(0) } }, 16884 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 16885 { /* => */ { FP64_0(1), FP64_RAND_V2(0) } }, 16886 /*mxcsr:in */ 0, 16887 /*128:out */ 0, 16888 /*256:out */ 0 }, 18146 /*src*/ /* => */ /*mxcsr:in*/ /*128:out*/ 18147 /* 18148 * Zero. 18149 */ 18150 /* 0*/{ FP64_0(0), FP64_0(0), 0, 0 }, 18151 { FP64_0(1), FP64_0(1), 0, 0 }, 18152 /* 18153 * Infinity. 18154 */ 18155 /* 2*/{ FP64_INF(0), FP64_INF(0), 0, 0 }, 18156 { FP64_INF(1), FP64_INF(1), 0, 0 }, 18157 /* 18158 * Normals. 18159 */ 18160 /* 4*/{ FP64_0_1(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18161 { FP64_0_1(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18162 { FP64_0_1(1), FP64_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18163 { FP64_0_1(1), FP64_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18164 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18165 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18166 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18167 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18168 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18169 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18170 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18171 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18172 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18173 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18174 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18175 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18176 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18177 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18178 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18179 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18180 { FP64_0_9(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18181 { FP64_0_9(0), FP64_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18182 { FP64_0_9(1), FP64_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18183 { FP64_0_9(1), FP64_1(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18184 { FP64_1(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18185 { FP64_1(1), FP64_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18186 { FP64_12_89_1(0), FP64_12_89_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18187 { FP64_12_89_1(0), FP64_12_89_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18188 { FP64_12_89_1(1), FP64_12_89_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18189 { FP64_12_89_1(1), FP64_12_89_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18190 { FP64_12_89_5(0), FP64_12_90_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18191 { FP64_12_89_5(0), FP64_12_90_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18192 { FP64_12_89_5(1), FP64_12_90_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18193 { FP64_12_89_5(1), FP64_12_90_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18194 { FP64_12_89_9(0), FP64_12_90_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18195 { FP64_12_89_9(0), FP64_12_90_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18196 { FP64_12_89_9(1), FP64_12_90_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18197 { FP64_12_89_9(1), FP64_12_90_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18198 { FP64_2(0), FP64_2(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18199 { FP64_2(0), FP64_2(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18200 { FP64_2(1), FP64_2(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18201 { FP64_2(1), FP64_2(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18202 { FP64_BIG_INT(0), FP64_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18203 { FP64_BIG_INT(1), FP64_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18204 }; 18205 /** quiet PE + round toward negative infinity */ 18206 static BS3CPUINSTR4_ROUNDSD_VALUES_T const s_aValuesNI[] = 18207 { 18208 /* 18209 * Normals. 18210 */ 18211 /* 0*/{ FP64_0_1(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18212 { FP64_0_1(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18213 { FP64_0_1(1), FP64_1(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18214 { FP64_0_1(1), FP64_1(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18215 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18216 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18217 { FP64_0_5(1), FP64_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18218 { FP64_0_5(1), FP64_1(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18219 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18220 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18221 { FP64_0_5_UP(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18222 { FP64_0_5_UP(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18223 { FP64_0_9(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18224 { FP64_0_9(1), FP64_1(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18225 { FP64_1(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18226 { FP64_1(1), FP64_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18227 { FP64_12_89_1(0), FP64_12_89_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18228 { FP64_12_89_1(1), FP64_12_90_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18229 { FP64_12_89_5(0), FP64_12_89_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18230 { FP64_12_89_5(1), FP64_12_90_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18231 { FP64_12_89_9(0), FP64_12_89_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18232 { FP64_12_89_9(1), FP64_12_90_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP, }, /* MXCSR overridden by instruction */ 18233 { FP64_2(0), FP64_2(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18234 { FP64_2(1), FP64_2(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18235 { FP64_BIG_INT(0), FP64_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18236 { FP64_BIG_INT(1), FP64_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18237 }; 18238 /** quiet PE + round toward positive infinity */ 18239 static BS3CPUINSTR4_ROUNDSD_VALUES_T const s_aValuesPI[] = 18240 { 18241 /* 18242 * Normals. 18243 */ 18244 /* 0*/{ FP64_0_1(0), FP64_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18245 { FP64_0_1(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18246 { FP64_0_1(1), FP64_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18247 { FP64_0_1(1), FP64_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18248 { FP64_0_5(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18249 { FP64_0_5(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18250 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18251 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18252 { FP64_0_5_DN(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18253 { FP64_0_5_DN(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18254 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18255 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18256 { FP64_0_9(0), FP64_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18257 { FP64_0_9(1), FP64_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18258 { FP64_1(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18259 { FP64_1(1), FP64_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18260 { FP64_12_89_1(0), FP64_12_90_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18261 { FP64_12_89_1(1), FP64_12_89_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18262 { FP64_12_89_5(0), FP64_12_90_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18263 { FP64_12_89_5(1), FP64_12_89_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18264 { FP64_12_89_9(0), FP64_12_90_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18265 { FP64_12_89_9(1), FP64_12_89_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18266 { FP64_2(0), FP64_2(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18267 { FP64_2(1), FP64_2(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18268 { FP64_BIG_INT(0), FP64_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18269 { FP64_BIG_INT(1), FP64_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18270 }; 18271 /** quiet PE + round toward zero */ 18272 static BS3CPUINSTR4_ROUNDSD_VALUES_T const s_aValuesZR[] = 18273 { 18274 /* 18275 * Normals. 18276 */ 18277 /* 0*/{ FP64_0_1(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18278 { FP64_0_1(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18279 { FP64_0_1(1), FP64_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18280 { FP64_0_1(1), FP64_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18281 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18282 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18283 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18284 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18285 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18286 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18287 { FP64_0_5_UP(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18288 { FP64_0_5_UP(0), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18289 { FP64_0_9(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18290 { FP64_0_9(1), FP64_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18291 { FP64_1(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18292 { FP64_1(1), FP64_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18293 { FP64_12_89_1(0), FP64_12_89_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18294 { FP64_12_89_1(1), FP64_12_89_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18295 { FP64_12_89_5(0), FP64_12_89_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18296 { FP64_12_89_5(1), FP64_12_89_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18297 { FP64_12_89_9(0), FP64_12_89_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18298 { FP64_12_89_9(1), FP64_12_89_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18299 { FP64_2(0), FP64_2(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18300 { FP64_2(1), FP64_2(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18301 { FP64_BIG_INT(0), FP64_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, /* MXCSR overridden by instruction */ 18302 { FP64_BIG_INT(1), FP64_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 16889 18303 }; 16890 18304 /** quiet PE + rounding controlled by MXCSR */ 16891 static BS3CPUINSTR4_ TEST1_VALUES_PD_T const s_aValuesMX[] =18305 static BS3CPUINSTR4_ROUNDSD_VALUES_T const s_aValuesMX[] = 16892 18306 { 16893 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 16894 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 16895 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 16896 /*mxcsr:in */ 0, 16897 /*128:out */ 0, 16898 /*256:out */ 0 }, 18307 /* 18308 * Normals. 18309 */ 18310 /* 0*/{ FP64_0_1(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18311 { FP64_0_1(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18312 { FP64_0_1(1), FP64_1(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18313 { FP64_0_1(1), FP64_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18314 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18315 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18316 { FP64_0_5(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18317 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18318 { FP64_0_5(1), FP64_1(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18319 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18320 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18321 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18322 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18323 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18324 { FP64_0_5_DN(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18325 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18326 { FP64_0_5_UP(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18327 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18328 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18329 { FP64_0_5_UP(0), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18330 { FP64_0_9(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18331 { FP64_0_9(0), FP64_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18332 { FP64_0_9(1), FP64_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18333 { FP64_0_9(1), FP64_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18334 { FP64_1(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18335 { FP64_1(1), FP64_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18336 { FP64_12_89_1(0), FP64_12_89_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18337 { FP64_12_89_1(0), FP64_12_90_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18338 { FP64_12_89_1(1), FP64_12_90_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18339 { FP64_12_89_1(1), FP64_12_89_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18340 { FP64_12_89_5(0), FP64_12_90_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18341 { FP64_12_89_5(0), FP64_12_89_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18342 { FP64_12_89_5(1), FP64_12_90_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18343 { FP64_12_89_5(1), FP64_12_89_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18344 { FP64_12_89_9(0), FP64_12_89_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18345 { FP64_12_89_9(0), FP64_12_90_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18346 { FP64_12_89_9(1), FP64_12_90_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18347 { FP64_12_89_9(1), FP64_12_90_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18348 { FP64_2(0), FP64_2(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18349 { FP64_2(0), FP64_2(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18350 { FP64_2(1), FP64_2(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18351 { FP64_2(1), FP64_2(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18352 { FP64_BIG_INT(0), FP64_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18353 { FP64_BIG_INT(1), FP64_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 16899 18354 }; 16900 /** quiet PE + round toward negative infinity*/16901 static BS3CPUINSTR4_ TEST1_VALUES_PD_T const s_aValuesNI[] =18355 /** raise PE + round toward nearest (even) */ 18356 static BS3CPUINSTR4_ROUNDSD_VALUES_T const s_aValuesPE[] = 16902 18357 { 16903 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 16904 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 16905 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 16906 /*mxcsr:in */ 0, 16907 /*128:out */ 0, 16908 /*256:out */ 0 }, 18358 /* 18359 * Normals. 18360 */ 18361 /* 0*/{ FP64_0_1(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18362 { FP64_0_1(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18363 { FP64_0_1(1), FP64_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18364 { FP64_0_1(1), FP64_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18365 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18366 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18367 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18368 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18369 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18370 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18371 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18372 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18373 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18374 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18375 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18376 { FP64_0_5_DN(0), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18377 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18378 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18379 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18380 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18381 { FP64_0_9(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18382 { FP64_0_9(0), FP64_1(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18383 { FP64_0_9(1), FP64_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18384 { FP64_0_9(1), FP64_1(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18385 { FP64_1(0), FP64_1(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, /* MXCSR overridden by instruction */ 18386 { FP64_1(1), FP64_1(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18387 { FP64_12_89_1(0), FP64_12_89_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18388 { FP64_12_89_1(0), FP64_12_89_0(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18389 { FP64_12_89_1(1), FP64_12_89_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18390 { FP64_12_89_1(1), FP64_12_89_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18391 { FP64_12_89_5(0), FP64_12_90_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18392 { FP64_12_89_5(0), FP64_12_90_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18393 { FP64_12_89_5(1), FP64_12_90_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18394 { FP64_12_89_5(1), FP64_12_90_0(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18395 { FP64_12_89_9(0), FP64_12_90_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18396 { FP64_12_89_9(0), FP64_12_90_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18397 { FP64_12_89_9(1), FP64_12_90_0(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN | X86_MXCSR_PE }, /* MXCSR overridden by instruction */ 18398 { FP64_12_89_9(1), FP64_12_90_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE }, 18399 { FP64_2(0), FP64_2(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18400 { FP64_2(0), FP64_2(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 18401 { FP64_2(1), FP64_2(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18402 { FP64_2(1), FP64_2(1), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, /* MXCSR overridden by instruction */ 18403 { FP64_BIG_INT(0), FP64_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18404 { FP64_BIG_INT(1), FP64_BIG_INT(1), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, /* MXCSR overridden by instruction */ 16909 18405 }; 16910 /** quiet PE + round toward positive infinity*/16911 static BS3CPUINSTR4_ TEST1_VALUES_PD_T const s_aValuesPI[] =18406 /** quiet PE + rounding controlled by MXCSR (reserved encoding) */ 18407 static BS3CPUINSTR4_ROUNDSD_VALUES_T const s_aValuesNV[] = 16912 18408 { 16913 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 16914 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 16915 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 16916 /*mxcsr:in */ 0, 16917 /*128:out */ 0, 16918 /*256:out */ 0 }, 16919 }; 16920 /** raise PE + round toward nearest even */ 16921 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesPE[] = 16922 { 16923 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 16924 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 16925 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 16926 /*mxcsr:in */ 0, 16927 /*128:out */ 0, 16928 /*256:out */ 0 }, 16929 }; 16930 /** quiet PE + round toward zero */ 16931 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesZR[] = 16932 { 16933 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 16934 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 16935 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 16936 /*mxcsr:in */ 0, 16937 /*128:out */ 0, 16938 /*256:out */ 0 }, 16939 }; 16940 /** quiet PE + rounding controlled by MXCSR (invalid encoding) */ 16941 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesNV[] = 16942 { 16943 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V1(0) } }, 16944 { /*src2 */ { FP64_2(1), FP64_RAND_V2(0) } }, 16945 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 16946 /*mxcsr:in */ 0, 16947 /*128:out */ 0, 16948 /*256:out */ 0 }, 16949 }; 16950 /** quiet PE + round toward nearest even + same-register */ 16951 static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValuesSR[] = 16952 { 16953 /* 0*/{ { /*src1 */ { FP64_0(0), FP64_RAND_V2(0) } }, 16954 { /*src2 */ { FP64_ROW_UNUSED } }, 16955 { /* => */ { FP64_0(0), FP64_RAND_V2(0) } }, 16956 /*mxcsr:in */ 0, 16957 /*128:out */ 0, 16958 /*256:out */ 0 }, 18409 /* 18410 * Normals. 18411 */ 18412 /* 0*/{ FP64_0_1(0), FP64_0(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18413 { FP64_0_5(0), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18414 { FP64_0_5(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18415 { FP64_0_5(1), FP64_1(1), X86_MXCSR_RC_DOWN, X86_MXCSR_RC_DOWN }, 18416 { FP64_0_5(1), FP64_0(1), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 18417 { FP64_0_5_DN(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18418 { FP64_0_5_UP(0), FP64_1(0), X86_MXCSR_RC_UP, X86_MXCSR_RC_UP }, 18419 { FP64_12_89_5(0), FP64_12_89_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_RC_ZERO }, 18420 { FP64_2(0), FP64_2(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST }, 16959 18421 }; 16960 18422 16961 18423 static BS3CPUINSTR4_TEST1_T const s_aTests[] = 16962 18424 { 16963 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_000h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16964 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_008h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16965 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_009h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16966 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00ah), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16967 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00bh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16968 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00ch), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16969 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00dh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16970 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00eh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16971 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00fh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16972 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_0ffh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, 16973 { BS3_INSTR4_ALL(roundsd_XMM1_FSxBX_008h), 255, RM_MEM, T_SSE4_1, XMM1, XMM1, 16974 { BS3_INSTR4_C64(roundsd_XMM8_XMM9_008h), 255, RM_REG, T_SSE4_1, XMM8, XMM8, 16975 { BS3_INSTR4_C64(roundsd_XMM8_FSxBX_008h), 255, RM_MEM, T_SSE4_1, XMM8, XMM8, 16976 16977 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM1_XMM2_008h), 255, RM_REG, T_AVX_128, XMM1, XMM1, 16978 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM1_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM1, XMM1, 16979 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM1_008h), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16980 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_000h), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16981 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_008h), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16982 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_009h), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16983 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00ah), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16984 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00bh), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16985 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00ch), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16986 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00dh), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16987 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00eh), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16988 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00fh), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16989 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_0ffh), 255, RM_REG, T_AVX_128, XMM1, XMM2, 16990 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM1, XMM2, 16991 { BS3_INSTR4_C64(vroundsd_XMM8_XMM8_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM8, XMM8, 16992 { BS3_INSTR4_C64(vroundsd_XMM8_XMM9_XMM10_008h), 255, RM_REG, T_AVX_128, XMM8, XMM9, 16993 { BS3_INSTR4_C64(vroundsd_XMM8_XMM9_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM8, XMM9, 16994 16995 { BS3_INSTR4_ALL(roundsd_XMM1_XMM1_008h), 255, RM_REG, T_SSE4_1, XMM1, NOREG, XMM1, PASS_TEST_ARRAY(s_aValuesSR) },16996 { BS3_INSTR4_C64(roundsd_XMM8_XMM8_008h), 255, RM_REG, T_SSE4_1, XMM8, NOREG, XMM8, PASS_TEST_ARRAY(s_aValuesSR) },16997 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM1_XMM1_008h), 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM1, PASS_TEST_ARRAY(s_aValuesSR) },16998 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM2_008h), 255, RM_REG, T_AVX_128, XMM1, NOREG, XMM2, PASS_TEST_ARRAY(s_aValuesSR) },16999 { BS3_INSTR4_C64(vroundsd_XMM8_XMM8_XMM8_008h), 255, RM_REG, T_AVX_128, XMM8, NOREG, XMM8, PASS_TEST_ARRAY(s_aValuesSR) },18425 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_000h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesPE) }, 18426 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_008h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesNE) }, 18427 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_009h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesNI) }, 18428 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00ah), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesPI) }, 18429 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00bh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesZR) }, 18430 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00ch), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesMX) }, 18431 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00dh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesMX) }, 18432 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00eh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesMX) }, 18433 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_00fh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesMX) }, 18434 { BS3_INSTR4_ALL(roundsd_XMM1_XMM2_0ffh), 255, RM_REG, T_SSE4_1, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesNV) }, 18435 { BS3_INSTR4_ALL(roundsd_XMM1_FSxBX_008h), 255, RM_MEM, T_SSE4_1, XMM1, XMM1, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18436 { BS3_INSTR4_C64(roundsd_XMM8_XMM9_008h), 255, RM_REG, T_SSE4_1, XMM8, XMM8, XMM9, PASS_TEST_ARRAY(s_aValuesNE) }, 18437 { BS3_INSTR4_C64(roundsd_XMM8_FSxBX_008h), 255, RM_MEM, T_SSE4_1, XMM8, XMM8, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18438 18439 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM1_XMM2_008h), 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM2, PASS_TEST_ARRAY(s_aValuesNE) }, 18440 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM1_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM1, XMM1, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18441 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM1_008h), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesNE) }, 18442 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_000h), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesPE) }, 18443 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_008h), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesNE) }, 18444 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_009h), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesNI) }, 18445 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00ah), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesPI) }, 18446 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00bh), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesZR) }, 18447 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00ch), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesMX) }, 18448 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00dh), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesMX) }, 18449 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00eh), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesMX) }, 18450 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_00fh), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesMX) }, 18451 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM3_0ffh), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM3, PASS_TEST_ARRAY(s_aValuesNV) }, 18452 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM1, XMM2, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18453 { BS3_INSTR4_C64(vroundsd_XMM8_XMM8_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM8, XMM8, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18454 { BS3_INSTR4_C64(vroundsd_XMM8_XMM9_XMM10_008h), 255, RM_REG, T_AVX_128, XMM8, XMM9, XMM10, PASS_TEST_ARRAY(s_aValuesNE) }, 18455 { BS3_INSTR4_C64(vroundsd_XMM8_XMM9_FSxBX_008h), 255, RM_MEM, T_AVX_128, XMM8, XMM9, FSxBX, PASS_TEST_ARRAY(s_aValuesNE) }, 18456 18457 { BS3_INSTR4_ALL(roundsd_XMM1_XMM1_008h), 255, RM_REG, T_SSE4_1, XMM1, XMM1, NOREG, PASS_TEST_ARRAY(s_aValuesNE) }, 18458 { BS3_INSTR4_C64(roundsd_XMM8_XMM8_008h), 255, RM_REG, T_SSE4_1, XMM8, XMM8, NOREG, PASS_TEST_ARRAY(s_aValuesNE) }, 18459 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM1_XMM1_008h), 255, RM_REG, T_AVX_128, XMM1, XMM1, NOREG, PASS_TEST_ARRAY(s_aValuesNE) }, 18460 { BS3_INSTR4_ALL(vroundsd_XMM1_XMM2_XMM2_008h), 255, RM_REG, T_AVX_128, XMM1, XMM2, NOREG, PASS_TEST_ARRAY(s_aValuesNE) }, 18461 { BS3_INSTR4_C64(vroundsd_XMM8_XMM8_XMM8_008h), 255, RM_REG, T_AVX_128, XMM8, XMM8, NOREG, PASS_TEST_ARRAY(s_aValuesNE) }, 17000 18462 }; 17001 18463 17002 return bs3CpuInstr4_WorkerTestType1 (bMode, PASS_ARRAY(s_aTests), PASS_ARRAY(g_aXcptConfig3));18464 return bs3CpuInstr4_WorkerTestType1_P(bMode, PASS_ARRAY(s_aTests), PASS_ARRAY(g_aXcptConfig3), bs3CpuInstr4_WorkerTestType1_Provider_roundsd); 17003 18465 } 17004 18466
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