Changeset 107048 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Nov 20, 2024 3:22:19 AM (2 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: Implement SIMD FP testcases for [v]roundp[ds], [v]rounds[ds] -- denormals, invalids; bugref:10658; jiraref:VBP-1205

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (6 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -16623 +16623 @@
               /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ X86_MXCSR_RC_ZERO },
+    /*
+     * Denormals.
+     */
+    /*14*/{ { /*src1     */ { FP32_DENORM_MAX(0), FP32_DENORM_MIN(0), FP32_DENORM_MAX(1), FP32_DENORM_MIN(1), FP32_DENORM_V1(0), FP32_DENORM_V2(1), FP32_DENORM_V3(0), FP32_DENORM_V4(1) } },
+            { /*unused   */ { FP32_ROW_UNUSED } },
+            { /* =>      */ { FP32_0(0),          FP32_0(0),          FP32_0(1),          FP32_0(1),          FP32_0(0),         FP32_0(1),         FP32_0(0),         FP32_0(1)         } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
+    /*
+     * Invalids.
+     */
+    /*15*/{ { /*src1     */ { FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_0_9(0), FP32_QNAN_V2(1), FP32_QNAN_V3(0), FP32_QNAN_V4(1), FP32_0_1(1), FP32_QNAN_V6(1) } },
+            { /*unused   */ { FP32_ROW_UNUSED } },
+            { /* =>      */ { FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_1(0),   FP32_QNAN_V2(1), FP32_QNAN_V3(0), FP32_QNAN_V4(1), FP32_0(1),   FP32_QNAN_V6(1) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
+          { { /*src1     */ { FP32_SNAN_MAX(0), FP32_SNAN_MAX(1), FP32_0_9(0), FP32_SNAN_V2(1), FP32_SNAN_V3(0), FP32_SNAN_V4(1), FP32_0_1(1), FP32_SNAN_V6(1) } },
+            { /*unused   */ { FP32_ROW_UNUSED } },
+            { /* =>      */ { FP32_QNAN_MAX(0), FP32_QNAN_MAX(1), FP32_1(0),   FP32_QNAN_V2(1), FP32_QNAN_V3(0), FP32_QNAN_V4(1), FP32_0(1),   FP32_QNAN_V6(1) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
+    /*
+     * Overflow, Underflow not possible.
+     */
     };
     /** quiet PE + round toward negative infinity */
@@ -17165 +17192 @@
               /*128:out  */ X86_MXCSR_RC_ZERO,
               /*256:out  */ X86_MXCSR_RC_ZERO },
+    /*
+     * Denormals.
+     */
+    /*26*/{ { /*src1     */ { FP64_DENORM_MAX(0), FP64_DENORM_MIN(1), FP64_DENORM_V2(1), FP64_DENORM_V3(0) } },
+            { /*unused   */ { FP64_ROW_UNUSED } },
+            { /* =>      */ { FP64_0(0),          FP64_0(1),          FP64_0(1),         FP64_0(0)         } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
+    /*
+     * Invalids.
+     */
+    /*27*/{ { /*src1     */ { FP64_QNAN_MAX(0), FP64_0_9(0), FP64_QNAN_V2(1), FP64_QNAN_V3(0) } },
+            { /*unused   */ { FP64_ROW_UNUSED } },
+            { /* =>      */ { FP64_QNAN_MAX(0), FP64_1(0),   FP64_QNAN_V2(1), FP64_QNAN_V3(0) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ 0,
+              /*256:out  */ 0 },
+          { { /*src1     */ { FP64_SNAN_MAX(1), FP64_SNAN_V3(0), FP64_0_1(1), FP64_SNAN_V1(1) } },
+            { /*unused   */ { FP64_ROW_UNUSED } },
+            { /* =>      */ { FP64_QNAN_MAX(1), FP64_QNAN_V3(0), FP64_0(1),   FP64_QNAN_V1(1) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_IE,
+              /*256:out  */ X86_MXCSR_IE },
+    /*
+     * Overflow, Underflow not possible.
+     */
     };
     /** quiet PE + round toward negative infinity */
@@ -17844 +17898 @@
           {    FP32_BIG_INT(0), FP32_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST },
           {    FP32_BIG_INT(1), FP32_BIG_INT(1), X86_MXCSR_RC_UP,      X86_MXCSR_RC_UP      }, /* MXCSR overridden by instruction */
+    /*
+     * Denormals.
+     */
+    /*48*/{    FP32_DENORM_MAX(0), FP32_0(0),    0,                    0                    },
+          {    FP32_DENORM_MIN(1), FP32_0(1),    0,                    0                    },
+    /*
+     * Invalids.
+     */
+    /*50*/{    FP32_QNAN_MAX(0), FP32_QNAN_MAX(0), 0,                  0                    },
+          {    FP32_QNAN_MAX(1), FP32_QNAN_MAX(1), 0,                  0                    },
+          {    FP32_QNAN_V1(0),  FP32_QNAN_V1(0),  0,                  0                    },
+          {    FP32_SNAN_MAX(0), FP32_QNAN_MAX(0), 0,                  X86_MXCSR_IE         },
+          {    FP32_SNAN_MAX(1), FP32_QNAN_MAX(1), 0,                  X86_MXCSR_IE         },
+          {    FP32_SNAN_V2(1),  FP32_QNAN_V2(1),  0,                  X86_MXCSR_IE         },
+    /*
+     * Overflow, Underflow not possible.
+     */
     };
     /** quiet PE + round toward negative infinity */
@@ -17999 +18070 @@
     {
     /*
-     * Normals.
+     * Normals & Precision.
      */
     /* 0*/{    FP32_0_1(0),     FP32_0(0),       X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE },
@@ -18202 +18273 @@
           {    FP64_BIG_INT(0), FP64_BIG_INT(0), X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST },
           {    FP64_BIG_INT(1), FP64_BIG_INT(1), X86_MXCSR_RC_UP,      X86_MXCSR_RC_UP      }, /* MXCSR overridden by instruction */
+    /*
+     * Denormals.
+     */
+    /*48*/{    FP64_DENORM_MAX(0), FP64_0(0),    0,                    0                    },
+          {    FP64_DENORM_MIN(1), FP64_0(1),    0,                    0                    },
+    /*
+     * Invalids.
+     */
+    /*50*/{    FP64_QNAN_MAX(0), FP64_QNAN_MAX(0), 0,                  0                    },
+          {    FP64_QNAN_MAX(1), FP64_QNAN_MAX(1), 0,                  0                    },
+          {    FP64_QNAN_V1(0),  FP64_QNAN_V1(0),  0,                  0                    },
+          {    FP64_SNAN_MAX(0), FP64_QNAN_MAX(0), 0,                  X86_MXCSR_IE         },
+          {    FP64_SNAN_MAX(1), FP64_QNAN_MAX(1), 0,                  X86_MXCSR_IE         },
+          {    FP64_SNAN_V2(1),  FP64_QNAN_V2(1),  0,                  X86_MXCSR_IE         },
+    /*
+     * Overflow, Underflow not possible.
+     */
     };
     /** quiet PE + round toward negative infinity */
@@ -18357 +18445 @@
     {
     /*
-     * Normals.
+     * Normals & Precision.
      */
     /* 0*/{    FP64_0_1(0),     FP64_0(0),       X86_MXCSR_RC_NEAREST, X86_MXCSR_RC_NEAREST | X86_MXCSR_PE },