VirtualBox

Changeset 107113 in vbox for trunk/src/VBox/VMM/VMMAll


Ignore:
Timestamp:
Nov 22, 2024 10:48:00 AM (3 months ago)
Author:
vboxsync
Message:

VMM: bugref:10759 Restructure the APIC to allow different backends to be used.

Location:
trunk/src/VBox/VMM/VMMAll
Files:
1 added
18 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r106061 r107113  
    3333#define VMCPU_INCL_CPUM_GST_CTX /* for macOS hack */
    3434#include "APICInternal.h"
    35 #include <VBox/vmm/apic.h>
    3635#include <VBox/vmm/pdmdev.h>
    3736#include <VBox/vmm/pdmapi.h>
    … …  
    418417
    419418/**
    420  * Returns whether the APIC is hardware enabled or not.
    421  *
    422  * @returns true if enabled, false otherwise.
    423  * @param   pVCpu           The cross context virtual CPU structure.
    424  */
    425 VMM_INT_DECL(bool) APICIsEnabled(PCVMCPUCC pVCpu)
     419 * @interface_method_impl{PDMAPICBACKEND,pfnisEnabled}
     420 */
     421static DECLCALLBACK(bool) apicIsEnabled(PCVMCPUCC pVCpu)
    426422{
    427423    PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    … …  
    464460 * @param   offReg          The offset of the register being read.
    465461 */
    466 DECLINLINE(uint32_t) apicReadRaw32(PCXAPICPAGE pXApicPage, uint16_t offReg)
    467 {
    468     Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
    469     uint8_t  const *pbXApic =  (const uint8_t *)pXApicPage;
     462static DECLCALLBACK(uint32_t) apicReadRaw32(PCVMCPUCC pVCpu, uint16_t offReg)
     463{
     464    PCXAPICPAGE pcXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
     465    Assert(offReg < sizeof(*pcXApicPage) - sizeof(uint32_t));
     466    uint8_t  const *pbXApic =  (const uint8_t *)pcXApicPage;
    470467    uint32_t const  uValue  = *(const uint32_t *)(pbXApic + offReg);
    471468    return uValue;
    … …  
    638635                {
    639636                    PVMCPUCC pItVCpu = pVM->CTX_SUFF(apCpus)[idCpu];
    640                     if (APICIsEnabled(pItVCpu))
    641                         fAccepted = apicPostInterrupt(pItVCpu, uVector, enmTriggerMode, uSrcTag);
     637                    if (apicIsEnabled(pItVCpu))
     638                        fAccepted = apicPostInterrupt(pItVCpu, uVector, enmTriggerMode, false /* fAutoEoi */, uSrcTag);
    642639                }
    643640            break;
    … …  
    649646            AssertMsgBreak(idCpu < pVM->cCpus, ("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode! idCpu=%u\n", idCpu));
    650647            PVMCPUCC pVCpuDst = pVM->CTX_SUFF(apCpus)[idCpu];
    651             if (APICIsEnabled(pVCpuDst))
    652                 fAccepted = apicPostInterrupt(pVCpuDst, uVector, enmTriggerMode, uSrcTag);
     648            if (apicIsEnabled(pVCpuDst))
     649                fAccepted = apicPostInterrupt(pVCpuDst, uVector, enmTriggerMode, false /* fAutoEoi */, uSrcTag);
    653650            else
    654651                AssertMsgFailed(("APIC: apicSendIntr: Target APIC not enabled in lowest-priority delivery mode! idCpu=%u\n", idCpu));
    … …  
    674671                {
    675672                    PVMCPUCC pItVCpu = pVM->CTX_SUFF(apCpus)[idCpu];
    676                     if (APICIsEnabled(pItVCpu))
     673                    if (apicIsEnabled(pItVCpu))
    677674                    {
    678675                        Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
    … …  
    11141111 *
    11151112 * @remarks This function is used by both x2APIC interface and the Hyper-V
    1116  *          interface, see APICHvSetIcr. The Hyper-V spec isn't clear what
    1117  *          happens when invalid bits are set. For the time being, it will
    1118  *          \#GP like a regular x2APIC access.
    1119  */
    1120 static VBOXSTRICTRC apicSetIcr(PVMCPUCC pVCpu, uint64_t u64Icr, int rcRZ)
     1113 *          interface, see PDMApicHvSetIcr. The Hyper-V spec isn't clear what
     1114 *          happens when invalid bits are set. For the time being, it will \#GP like
     1115 *          a regular x2APIC access.
     1116 */
     1117static DECLCALLBACK(VBOXSTRICTRC) apicSetIcr(PVMCPUCC pVCpu, uint64_t u64Icr, int rcRZ)
    11211118{
    11221119    VMCPU_ASSERT_EMT(pVCpu);
    … …  
    12011198     *
    12021199     * In all other instances, whenever the TPR or ISR changes, we need to update the PPR
    1203      * as well (e.g. like we do manually in apicR3InitIpi and by calling apicUpdatePpr).
     1200     * as well (e.g. like we do manually in apicInitIpi and by calling apicUpdatePpr).
    12041201     */
    12051202    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
    … …  
    12491246 *                                  this write.
    12501247 */
    1251 static VBOXSTRICTRC apicSetEoi(PVMCPUCC pVCpu, uint32_t uEoi, bool fForceX2ApicBehaviour)
     1248static DECLCALLBACK(VBOXSTRICTRC) apicSetEoi(PVMCPUCC pVCpu, uint32_t uEoi, bool fForceX2ApicBehaviour)
    12521249{
    12531250    VMCPU_ASSERT_EMT(pVCpu);
    … …  
    12831280             *
    12841281             * The broadcast to I/O APIC can re-trigger new interrupts to arrive via the bus. However,
    1285              * APICUpdatePendingInterrupts() which updates TMR can only be done from EMT which we
     1282             * apicUpdatePendingInterrupts() which updates TMR can only be done from EMT which we
    12861283             * currently are on, so no possibility of concurrent updates.
    12871284             */
    … …  
    16471644 * @param   pVCpu           The cross context virtual CPU structure.
    16481645 */
    1649 DECLINLINE(uint64_t) apicGetIcrNoCheck(PVMCPUCC pVCpu)
     1646static DECLCALLBACK(uint64_t) apicGetIcrNoCheck(PVMCPUCC pVCpu)
    16501647{
    16511648    PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
    … …  
    16711668    Assert(offReg <= XAPIC_OFF_MAX_VALID);
    16721669
    1673     PXAPICPAGE   pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    16741670    uint32_t     uValue = 0;
    16751671    VBOXSTRICTRC rc = VINF_SUCCESS;
    … …  
    17081704                       && offReg != XAPIC_OFF_ICR_HI
    17091705                       && offReg != XAPIC_OFF_EOI));
    1710             uValue = apicReadRaw32(pXApicPage, offReg);
     1706            uValue = apicReadRaw32(pVCpu, offReg);
    17111707            Log2(("APIC%u: apicReadRegister: offReg=%#x uValue=%#x\n", pVCpu->idCpu, offReg, uValue));
    17121708            break;
    … …  
    18821878
    18831879/**
    1884  * Reads an APIC MSR.
    1885  *
    1886  * @returns Strict VBox status code.
    1887  * @param   pVCpu           The cross context virtual CPU structure.
    1888  * @param   u32Reg          The MSR being read.
    1889  * @param   pu64Value       Where to store the read value.
    1890  */
    1891 VMM_INT_DECL(VBOXSTRICTRC) APICReadMsr(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
     1880 * @interface_method_impl{PDMAPICBACKEND,pfnReadMsr}
     1881 */
     1882static DECLCALLBACK(VBOXSTRICTRC) apicReadMsr(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
    18921883{
    18931884    /*
    … …  
    19021893     */
    19031894    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
    1904     if (APICIsEnabled(pVCpu))
     1895    if (apicIsEnabled(pVCpu))
    19051896    { /* likely */ }
    19061897    else
    … …  
    19851976            case MSR_IA32_X2APIC_TIMER_DCR:
    19861977            {
    1987                 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    19881978                uint16_t const offReg = X2APIC_GET_XAPIC_OFF(u32Reg);
    1989                 *pu64Value = apicReadRaw32(pXApicPage, offReg);
     1979                *pu64Value = apicReadRaw32(pVCpu, offReg);
    19901980                break;
    19911981            }
    … …  
    20302020
    20312021/**
    2032  * Writes an APIC MSR.
    2033  *
    2034  * @returns Strict VBox status code.
    2035  * @param   pVCpu           The cross context virtual CPU structure.
    2036  * @param   u32Reg          The MSR being written.
    2037  * @param   u64Value        The value to write.
    2038  */
    2039 VMM_INT_DECL(VBOXSTRICTRC) APICWriteMsr(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t u64Value)
     2022 * @interface_method_impl{PDMAPICBACKEND,pfnWriteMsr}
     2023 */
     2024static DECLCALLBACK(VBOXSTRICTRC) apicWriteMsr(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t u64Value)
    20402025{
    20412026    /*
    … …  
    20492034     */
    20502035    PCAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
    2051     if (APICIsEnabled(pVCpu))
     2036    if (apicIsEnabled(pVCpu))
    20522037    { /* likely */ }
    20532038    else
    … …  
    21352120            {
    21362121                uint8_t const uVector = XAPIC_SELF_IPI_GET_VECTOR(u32Value);
    2137                 apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE, 0 /* uSrcTag */);
     2122                apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE, false /* fAutoEoi */, 0 /* uSrcTag */);
    21382123                rcStrict = VINF_SUCCESS;
    21392124                break;
    … …  
    22482233
    22492234/**
    2250  * Initializes per-VCPU APIC to the state following an INIT reset
    2251  * ("Wait-for-SIPI" state).
    2252  *
    2253  * @param   pVCpu       The cross context virtual CPU structure.
    2254  */
    2255 void apicInitIpi(PVMCPUCC pVCpu)
     2235 * @interface_method_impl{PDMAPICBACKEND,pfnInitIpi}
     2236 */
     2237static DECLCALLBACK(void) apicInitIpi(PVMCPUCC pVCpu)
    22562238{
    22572239    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    … …  
    23772359
    23782360/**
    2379  * Sets the APIC base MSR.
    2380  *
    2381  * @returns VBox status code - no informational ones, esp. not
    2382  *          VINF_CPUM_R3_MSR_WRITE.  Only the following two:
    2383  * @retval  VINF_SUCCESS
    2384  * @retval  VERR_CPUM_RAISE_GP_0
    2385  *
    2386  * @param   pVCpu       The cross context virtual CPU structure.
    2387  * @param   u64BaseMsr  The value to set.
    2388  */
    2389 VMM_INT_DECL(int) APICSetBaseMsr(PVMCPUCC pVCpu, uint64_t u64BaseMsr)
     2361 * @interface_method_impl{PDMAPICBACKEND,pfnSetBaseMsr}
     2362 */
     2363static DECLCALLBACK(int) apicSetBaseMsr(PVMCPUCC pVCpu, uint64_t u64BaseMsr)
    23902364{
    23912365    Assert(pVCpu);
    … …  
    23972371    uint64_t uBaseMsr   = pApicCpu->uApicBaseMsr;
    23982372
    2399     Log2(("APIC%u: ApicSetBaseMsr: u64BaseMsr=%#RX64 enmNewMode=%s enmOldMode=%s\n", pVCpu->idCpu, u64BaseMsr,
     2373    Log2(("APIC%u: apicSetBaseMsr: u64BaseMsr=%#RX64 enmNewMode=%s enmOldMode=%s\n", pVCpu->idCpu, u64BaseMsr,
    24002374          apicGetModeName(enmNewMode), apicGetModeName(enmOldMode)));
    24012375
    … …  
    25172491
    25182492/**
    2519  * Gets the APIC base MSR (no checks are performed wrt APIC hardware or its
    2520  * state).
    2521  *
    2522  * @returns The base MSR value.
    2523  * @param   pVCpu       The cross context virtual CPU structure.
    2524  */
    2525 VMM_INT_DECL(uint64_t) APICGetBaseMsrNoCheck(PCVMCPUCC pVCpu)
     2493 * @interface_method_impl{PDMAPICBACKEND,pfnGetBaseMsrNoCheck}
     2494 */
     2495static DECLCALLBACK(uint64_t) apicGetBaseMsrNoCheck(PCVMCPUCC pVCpu)
    25262496{
    25272497    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    … …  
    25322502
    25332503/**
    2534  * Gets the APIC base MSR.
    2535  *
    2536  * @returns Strict VBox status code.
    2537  * @param   pVCpu       The cross context virtual CPU structure.
    2538  * @param   pu64Value   Where to store the MSR value.
    2539  */
    2540 VMM_INT_DECL(VBOXSTRICTRC) APICGetBaseMsr(PVMCPUCC pVCpu, uint64_t *pu64Value)
     2504 * @interface_method_impl{PDMAPICBACKEND,pfnGetBaseMsr}
     2505 */
     2506static DECLCALLBACK(VBOXSTRICTRC) apicGetBaseMsr(PVMCPUCC pVCpu, uint64_t *pu64Value)
    25412507{
    25422508    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    … …  
    25452511    if (pApic->enmMaxMode != PDMAPICMODE_NONE)
    25462512    {
    2547         *pu64Value = APICGetBaseMsrNoCheck(pVCpu);
     2513        *pu64Value = apicGetBaseMsrNoCheck(pVCpu);
    25482514        return VINF_SUCCESS;
    25492515    }
    … …  
    25562522
    25572523/**
    2558  * Sets the TPR (Task Priority Register).
    2559  *
    2560  * @retval  VINF_SUCCESS
    2561  * @retval  VERR_CPUM_RAISE_GP_0
    2562  * @retval  VERR_PDM_NO_APIC_INSTANCE
    2563  *
    2564  * @param   pVCpu       The cross context virtual CPU structure.
    2565  * @param   u8Tpr       The TPR value to set.
    2566  */
    2567 VMMDECL(int) APICSetTpr(PVMCPUCC pVCpu, uint8_t u8Tpr)
    2568 {
    2569     if (APICIsEnabled(pVCpu))
    2570         return apicSetTprEx(pVCpu, u8Tpr, false /* fForceX2ApicBehaviour */);
     2524 * @interface_method_impl{PDMAPICBACKEND,pfnSetTpr}
     2525 */
     2526static DECLCALLBACK(int) apicSetTpr(PVMCPUCC pVCpu, uint8_t u8Tpr, bool fForceX2ApicBehaviour)
     2527{
     2528    if (apicIsEnabled(pVCpu))
     2529        return apicSetTprEx(pVCpu, u8Tpr, fForceX2ApicBehaviour);
    25712530    return VERR_PDM_NO_APIC_INSTANCE;
    25722531}
    … …  
    25972556
    25982557/**
    2599  * Gets the APIC TPR (Task Priority Register).
    2600  *
    2601  * @returns VBox status code.
    2602  * @param   pVCpu           The cross context virtual CPU structure.
    2603  * @param   pu8Tpr          Where to store the TPR.
    2604  * @param   pfPending       Where to store whether there is a pending interrupt
    2605  *                          (optional, can be NULL).
    2606  * @param   pu8PendingIntr  Where to store the highest-priority pending
    2607  *                          interrupt (optional, can be NULL).
    2608  */
    2609 VMMDECL(int) APICGetTpr(PCVMCPUCC pVCpu, uint8_t *pu8Tpr, bool *pfPending, uint8_t *pu8PendingIntr)
     2558 * @interface_method_impl{PDMAPICBACKEND,pfnGetTpr}
     2559 */
     2560static DECLCALLBACK(int) apicGetTpr(PCVMCPUCC pVCpu, uint8_t *pu8Tpr, bool *pfPending, uint8_t *pu8PendingIntr)
    26102561{
    26112562    VMCPU_ASSERT_EMT(pVCpu);
    2612     if (APICIsEnabled(pVCpu))
     2563    if (apicIsEnabled(pVCpu))
    26132564    {
    26142565        PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
    … …  
    26322583
    26332584/**
    2634  * Gets the APIC timer frequency.
    2635  *
    2636  * @returns Strict VBox status code.
    2637  * @param   pVM             The cross context VM structure.
    2638  * @param   pu64Value       Where to store the timer frequency.
    2639  */
    2640 VMM_INT_DECL(int) APICGetTimerFreq(PVMCC pVM, uint64_t *pu64Value)
     2585 * @interface_method_impl{PDMAPICBACKEND,pfnGetTimerFreq}
     2586 */
     2587static DECLCALLBACK(int) apicGetTimerFreq(PVMCC pVM, uint64_t *pu64Value)
    26412588{
    26422589    /*
    … …  
    26472594
    26482595    PVMCPUCC pVCpu = pVM->CTX_SUFF(apCpus)[0];
    2649     if (APICIsEnabled(pVCpu))
     2596    if (apicIsEnabled(pVCpu))
    26502597    {
    26512598        PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    … …  
    26582605
    26592606/**
    2660  * Delivers an interrupt message via the system bus.
    2661  *
    2662  * @returns VBox status code.
    2663  * @param   pVM             The cross context VM structure.
    2664  * @param   uDest           The destination mask.
    2665  * @param   uDestMode       The destination mode.
    2666  * @param   uDeliveryMode   The delivery mode.
    2667  * @param   uVector         The interrupt vector.
    2668  * @param   uPolarity       The interrupt line polarity.
    2669  * @param   uTriggerMode    The trigger mode.
    2670  * @param   uSrcTag         The interrupt source tag (debugging).
    2671  */
    2672 VMM_INT_DECL(int) APICBusDeliver(PVMCC pVM, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
    2673                                  uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uSrcTag)
     2607 * @interface_method_impl{PDMAPICBACKEND,pfnBusDeliver}
     2608 */
     2609static DECLCALLBACK(int) apicBusDeliver(PVMCC pVM, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
     2610                                        uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uSrcTag)
    26742611{
    26752612    NOREF(uPolarity);
    … …  
    26782615     * If the APIC isn't enabled, do nothing and pretend success.
    26792616     */
    2680     if (APICIsEnabled(pVM->CTX_SUFF(apCpus)[0]))
     2617    if (apicIsEnabled(pVM->CTX_SUFF(apCpus)[0]))
    26812618    { /* likely */ }
    26822619    else
    … …  
    27102647
    27112648/**
    2712  * Assert/de-assert the local APIC's LINT0/LINT1 interrupt pins.
    2713  *
    2714  * @returns Strict VBox status code.
    2715  * @param   pVCpu       The cross context virtual CPU structure.
    2716  * @param   u8Pin       The interrupt pin (0 for LINT0 or 1 for LINT1).
    2717  * @param   u8Level     The level (0 for low or 1 for high).
    2718  * @param   rcRZ        The return code if the operation cannot be performed in
    2719  *                      the current context.
    2720  *
    2721  * @note    All callers totally ignores the status code!
    2722  */
    2723 VMM_INT_DECL(VBOXSTRICTRC) APICLocalInterrupt(PVMCPUCC pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
     2649 * @interface_method_impl{PDMAPICBACKEND,pfnSetLocalInterrupt}
     2650 */
     2651static DECLCALLBACK(VBOXSTRICTRC) apicSetLocalInterrupt(PVMCPUCC pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
    27242652{
    27252653    AssertReturn(u8Pin <= 1, VERR_INVALID_PARAMETER);
    … …  
    27292657
    27302658    /* If the APIC is enabled, the interrupt is subject to LVT programming. */
    2731     if (APICIsEnabled(pVCpu))
     2659    if (apicIsEnabled(pVCpu))
    27322660    {
    27332661        PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
    … …  
    27412669        Assert(u8Pin < RT_ELEMENTS(s_au16LvtOffsets));
    27422670        uint16_t const offLvt = s_au16LvtOffsets[u8Pin];
    2743         uint32_t const uLvt   = apicReadRaw32(pXApicPage, offLvt);
     2671        uint32_t const uLvt   = apicReadRaw32(pVCpu, offLvt);
    27442672
    27452673        /* If software hasn't masked the interrupt in the LVT entry, proceed interrupt processing. */
    … …  
    28312759                case XAPICDELIVERYMODE_EXTINT:
    28322760                {
    2833                     Log2(("APIC%u: apicLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
     2761                    Log2(("APIC%u: apicSetLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
    28342762                          u8Level ? "Raising" : "Lowering", u8Pin));
    28352763                    if (u8Level)
    … …  
    28592787        {
    28602788            /* LINT0 behaves as an external interrupt pin. */
    2861             Log2(("APIC%u: apicLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
     2789            Log2(("APIC%u: apicSetLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
    28622790                  u8Level ? "raising" : "lowering"));
    28632791            if (u8Level)
    … …  
    28692797        {
    28702798            /* LINT1 behaves as NMI. */
    2871             Log2(("APIC%u: apicLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
     2799            Log2(("APIC%u: apicSetLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
    28722800            apicSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
    28732801        }
    … …  
    28792807
    28802808/**
    2881  * Gets the next highest-priority interrupt from the APIC, marking it as an
    2882  * "in-service" interrupt.
    2883  *
    2884  * @returns VBox status code.
    2885  * @param   pVCpu       The cross context virtual CPU structure.
    2886  * @param   pu8Vector   Where to store the vector.
    2887  * @param   puSrcTag    Where to store the interrupt source tag (debugging).
    2888  */
    2889 VMM_INT_DECL(int) APICGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Vector, uint32_t *puSrcTag)
     2809 * @interface_method_impl{PDMAPICBACKEND,pfnGetInterrupt}
     2810 */
     2811static DECLCALLBACK(int) apicGetInterrupt(PVMCPUCC pVCpu, uint8_t *pu8Vector, uint32_t *puSrcTag)
    28902812{
    28912813    VMCPU_ASSERT_EMT(pVCpu);
    … …  
    28952817
    28962818    PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    2897     bool const fApicHwEnabled = APICIsEnabled(pVCpu);
     2819    bool const fApicHwEnabled = apicIsEnabled(pVCpu);
    28982820    if (   fApicHwEnabled
    28992821        && pXApicPage->svr.u.fApicSoftwareEnable)
    … …  
    31123034 * @param   uVector             The vector of the interrupt to be posted.
    31133035 * @param   enmTriggerMode      The trigger mode of the interrupt.
     3036 * @param   fAutoEoi            Whether this interrupt has automatic EOI
     3037 *                              treatment.
    31143038 * @param   uSrcTag             The interrupt source tag (debugging).
    31153039 *
    31163040 * @thread  Any.
    31173041 */
    3118 bool apicPostInterrupt(PVMCPUCC pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode, uint32_t uSrcTag)
     3042DECLCALLBACK(bool) apicPostInterrupt(PVMCPUCC pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode, bool fAutoEoi,
     3043                                     uint32_t uSrcTag)
    31193044{
    31203045    Assert(pVCpu);
    31213046    Assert(uVector > XAPIC_ILLEGAL_VECTOR_END);
     3047    RT_NOREF(fAutoEoi);
    31223048
    31233049    PVMCC    pVM       = pVCpu->CTX_SUFF(pVM);
    … …  
    32543180
    32553181
     3182#if 0
    32563183/**
    32573184 * Queues a pending interrupt as in-service.
    … …  
    33223249    }
    33233250}
    3324 
    3325 
    3326 /**
    3327  * Updates pending interrupts from the pending-interrupt bitmaps to the IRR.
    3328  *
    3329  * @param   pVCpu               The cross context virtual CPU structure.
    3330  *
    3331  * @note    NEM/win is ASSUMING the an up to date TPR is not required here.
    3332  */
    3333 VMMDECL(void) APICUpdatePendingInterrupts(PVMCPUCC pVCpu)
     3251#endif
     3252
     3253
     3254/**
     3255 * @interface_method_impl{PDMAPICBACKEND,pfnUpdatePendingInterrupts}
     3256 */
     3257static DECLCALLBACK(void) apicUpdatePendingInterrupts(PVMCPUCC pVCpu)
    33343258{
    33353259    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    … …  
    33393263    bool       fHasPendingIntrs = false;
    33403264
    3341     Log3(("APIC%u: APICUpdatePendingInterrupts:\n", pVCpu->idCpu));
     3265    Log3(("APIC%u: apicUpdatePendingInterrupts:\n", pVCpu->idCpu));
    33423266    STAM_PROFILE_START(&pApicCpu->StatUpdatePendingIntrs, a);
    33433267
    … …  
    34033327
    34043328    STAM_PROFILE_STOP(&pApicCpu->StatUpdatePendingIntrs, a);
    3405     Log3(("APIC%u: APICUpdatePendingInterrupts: fHasPendingIntrs=%RTbool\n", pVCpu->idCpu, fHasPendingIntrs));
     3329    Log3(("APIC%u: apicUpdatePendingInterrupts: fHasPendingIntrs=%RTbool\n", pVCpu->idCpu, fHasPendingIntrs));
    34063330
    34073331    if (   fHasPendingIntrs
    … …  
    34113335
    34123336
    3413 /**
    3414  * Gets the highest priority pending interrupt.
    3415  *
    3416  * @returns true if any interrupt is pending, false otherwise.
    3417  * @param   pVCpu               The cross context virtual CPU structure.
    3418  * @param   pu8PendingIntr      Where to store the interrupt vector if the
    3419  *                              interrupt is pending.
    3420  */
    3421 VMM_INT_DECL(bool) APICGetHighestPendingInterrupt(PVMCPUCC pVCpu, uint8_t *pu8PendingIntr)
    3422 {
    3423     VMCPU_ASSERT_EMT(pVCpu);
    3424     return apicGetHighestPendingInterrupt(pVCpu, pu8PendingIntr);
    3425 }
    3426 
    3427 
    3428 /**
    3429  * Posts an interrupt to a target APIC, Hyper-V interface.
    3430  *
    3431  * @param   pVCpu               The cross context virtual CPU structure.
    3432  * @param   uVector             The vector of the interrupt to be posted.
    3433  * @param   fAutoEoi            Whether this interrupt has automatic EOI
    3434  *                              treatment.
    3435  * @param   enmTriggerMode      The trigger mode of the interrupt.
    3436  *
    3437  * @thread  Any.
    3438  */
    3439 VMM_INT_DECL(void) APICHvSendInterrupt(PVMCPUCC pVCpu, uint8_t uVector, bool fAutoEoi, XAPICTRIGGERMODE enmTriggerMode)
    3440 {
    3441     Assert(pVCpu);
    3442     Assert(!fAutoEoi);    /** @todo AutoEOI.  */
    3443     RT_NOREF(fAutoEoi);
    3444     apicPostInterrupt(pVCpu, uVector, enmTriggerMode, 0 /* uSrcTag */);
    3445 }
    3446 
    3447 
    3448 /**
    3449  * Sets the Task Priority Register (TPR), Hyper-V interface.
    3450  *
    3451  * @returns Strict VBox status code.
    3452  * @param   pVCpu       The cross context virtual CPU structure.
    3453  * @param   uTpr        The TPR value to set.
    3454  *
    3455  * @remarks Validates like in x2APIC mode.
    3456  */
    3457 VMM_INT_DECL(VBOXSTRICTRC) APICHvSetTpr(PVMCPUCC pVCpu, uint8_t uTpr)
    3458 {
    3459     Assert(pVCpu);
    3460     VMCPU_ASSERT_EMT(pVCpu);
    3461     return apicSetTprEx(pVCpu, uTpr, true /* fForceX2ApicBehaviour */);
    3462 }
    3463 
    3464 
    3465 /**
    3466  * Gets the Task Priority Register (TPR), Hyper-V interface.
    3467  *
    3468  * @returns The TPR value.
    3469  * @param   pVCpu           The cross context virtual CPU structure.
    3470  */
    3471 VMM_INT_DECL(uint8_t) APICHvGetTpr(PVMCPUCC pVCpu)
    3472 {
    3473     Assert(pVCpu);
    3474     VMCPU_ASSERT_EMT(pVCpu);
    3475 
    3476     /*
    3477      * The APIC could be operating in xAPIC mode and thus we should not use the apicReadMsr()
    3478      * interface which validates the APIC mode and will throw a #GP(0) if not in x2APIC mode.
    3479      * We could use the apicReadRegister() MMIO interface, but why bother getting the PDMDEVINS
    3480      * pointer, so just directly read the APIC page.
    3481      */
    3482     PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
    3483     return apicReadRaw32(pXApicPage, XAPIC_OFF_TPR);
    3484 }
    3485 
    3486 
    3487 /**
    3488  * Sets the Interrupt Command Register (ICR), Hyper-V interface.
    3489  *
    3490  * @returns Strict VBox status code.
    3491  * @param   pVCpu       The cross context virtual CPU structure.
    3492  * @param   uIcr        The ICR value to set.
    3493  */
    3494 VMM_INT_DECL(VBOXSTRICTRC) APICHvSetIcr(PVMCPUCC pVCpu, uint64_t uIcr)
    3495 {
    3496     Assert(pVCpu);
    3497     VMCPU_ASSERT_EMT(pVCpu);
    3498     return apicSetIcr(pVCpu, uIcr, VINF_CPUM_R3_MSR_WRITE);
    3499 }
    3500 
    3501 
    3502 /**
    3503  * Gets the Interrupt Command Register (ICR), Hyper-V interface.
    3504  *
    3505  * @returns The ICR value.
    3506  * @param   pVCpu           The cross context virtual CPU structure.
    3507  */
    3508 VMM_INT_DECL(uint64_t) APICHvGetIcr(PVMCPUCC pVCpu)
    3509 {
    3510     Assert(pVCpu);
    3511     VMCPU_ASSERT_EMT(pVCpu);
    3512     return apicGetIcrNoCheck(pVCpu);
    3513 }
    3514 
    3515 
    3516 /**
    3517  * Sets the End-Of-Interrupt (EOI) register, Hyper-V interface.
    3518  *
    3519  * @returns Strict VBox status code.
    3520  * @param   pVCpu           The cross context virtual CPU structure.
    3521  * @param   uEoi            The EOI value.
    3522  */
    3523 VMM_INT_DECL(VBOXSTRICTRC) APICHvSetEoi(PVMCPUCC pVCpu, uint32_t uEoi)
    3524 {
    3525     Assert(pVCpu);
    3526     VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    3527     return apicSetEoi(pVCpu, uEoi, true /* fForceX2ApicBehaviour */);
    3528 }
    3529 
    3530 
    3531 /**
    3532  * Gets the APIC page pointers for the specified VCPU.
    3533  *
    3534  * @returns VBox status code.
    3535  * @param   pVCpu           The cross context virtual CPU structure.
    3536  * @param   pHCPhys         Where to store the host-context physical address.
    3537  * @param   pR0Ptr          Where to store the ring-0 address.
    3538  * @param   pR3Ptr          Where to store the ring-3 address (optional).
    3539  */
    3540 VMM_INT_DECL(int) APICGetApicPageForCpu(PCVMCPUCC pVCpu, PRTHCPHYS pHCPhys, PRTR0PTR pR0Ptr, PRTR3PTR pR3Ptr)
     3337#ifdef IN_RING0
     3338/**
     3339 * @interface_method_impl{PDMAPICBACKEND,pfnGetApicPageForCpu}
     3340 */
     3341static DECLCALLBACK(int) apicR0VBoxGetApicPageForCpu(PCVMCPUCC pVCpu, PRTHCPHYS pHCPhys, PRTR0PTR pR0Ptr, PRTR3PTR pR3Ptr)
    35413342{
    35423343    AssertReturn(pVCpu,   VERR_INVALID_PARAMETER);
    … …  
    35533354    return VINF_SUCCESS;
    35543355}
     3356#endif /* IN_RING0 */
    35553357
    35563358#ifndef IN_RING3
    … …  
    35723374    rc = PDMDevHlpApicSetUpContext(pDevIns);
    35733375    AssertRCReturn(rc, rc);
     3376
     3377    rc = PDMApicRegisterBackend(pVM, PDMAPICBACKENDTYPE_VBOX, &g_ApicBackend);
     3378    AssertLogRelRCReturn(rc, rc);
    35743379
    35753380    rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, apicWriteMmio, apicReadMmio, NULL /*pvUser*/);
    … …  
    36543459};
    36553460
     3461/**
     3462 * The VirtualBox APIC backend.
     3463 */
     3464const PDMAPICBACKEND g_ApicBackend =
     3465{
     3466    /* .pfnIsEnabled = */               apicIsEnabled,
     3467    /* .pfnInitIpi = */                 apicInitIpi,
     3468    /* .pfnGetBaseMsrNoCheck = */       apicGetBaseMsrNoCheck,
     3469    /* .pfnGetBaseMsr = */              apicGetBaseMsr,
     3470    /* .pfnSetBaseMsr = */              apicSetBaseMsr,
     3471    /* .pfnReadRaw32 = */               apicReadRaw32,
     3472    /* .pfnReadMsr = */                 apicReadMsr,
     3473    /* .pfnWriteMsr = */                apicWriteMsr,
     3474    /* .pfnGetTpr = */                  apicGetTpr,
     3475    /* .pfnSetTpr = */                  apicSetTpr,
     3476    /* .pfnGetIcrNoCheck = */           apicGetIcrNoCheck,
     3477    /* .pfnSetIcr = */                  apicSetIcr,
     3478    /* .pfnGetTimerFreq = */            apicGetTimerFreq,
     3479    /* .pfnSetLocalInterrupt = */       apicSetLocalInterrupt,
     3480    /* .pfnGetInterrupt = */            apicGetInterrupt,
     3481    /* .pfnPostInterrupt = */           apicPostInterrupt,
     3482    /* .pfnUpdatePendingInterrupts = */ apicUpdatePendingInterrupts,
     3483    /* .pfnBusDeliver = */              apicBusDeliver,
     3484    /* .pfnSetEoi = */                  apicSetEoi,
     3485#if defined(IN_RING3)
     3486    /* .pfnHvSetCompatMode = */         apicR3HvSetCompatMode,
     3487#elif defined(IN_RING0)
     3488    /* .pfnGetApicPageForCpu = */       apicR0VBoxGetApicPageForCpu,
     3489#endif
     3490};
     3491

  • trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp

    r106061 r107113  
    3232#define LOG_GROUP LOG_GROUP_CPUM
    3333#include <VBox/vmm/cpum.h>
    34 #include <VBox/vmm/apic.h>
     34#include <VBox/vmm/pdmapic.h>
    3535#include <VBox/vmm/hm.h>
    3636#include <VBox/vmm/hm_vmx.h>
    … …  
    235235{
    236236    RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
    237     return APICGetBaseMsr(pVCpu, puValue);
     237    return PDMApicGetBaseMsr(pVCpu, puValue);
    238238}
    239239
    … …  
    243243{
    244244    RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange); RT_NOREF_PV(uValue); RT_NOREF_PV(uRawValue);
    245     return APICSetBaseMsr(pVCpu, uValue);
     245    return PDMApicSetBaseMsr(pVCpu, uValue);
    246246}
    247247
    … …  
    13471347    }
    13481348#endif
    1349     return APICReadMsr(pVCpu, idMsr, puValue);
     1349    return PDMApicReadMsr(pVCpu, idMsr, puValue);
    13501350}
    13511351
    … …  
    13671367    }
    13681368#endif
    1369     return APICWriteMsr(pVCpu, idMsr, uValue);
     1369    return PDMApicWriteMsr(pVCpu, idMsr, uValue);
    13701370}
    13711371

  • trunk/src/VBox/VMM/VMMAll/CPUMAllRegs-armv8.cpp

    r106381 r107113  
    3333#include <VBox/vmm/cpum.h>
    3434#include <VBox/vmm/dbgf.h>
    35 #include <VBox/vmm/apic.h>
     35#include <VBox/vmm/pdmapic.h>
    3636#include <VBox/vmm/pgm.h>
    3737#include <VBox/vmm/mm.h>

  • trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

    r106061 r107113  
    3333#include <VBox/vmm/cpum.h>
    3434#include <VBox/vmm/dbgf.h>
    35 #include <VBox/vmm/apic.h>
     35#include <VBox/vmm/pdmapic.h>
    3636#include <VBox/vmm/pgm.h>
    3737#include <VBox/vmm/mm.h>
    … …  
    716716            CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
    717717            uint8_t u8Tpr;
    718             int rc = APICGetTpr(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
     718            int rc = PDMApicGetTpr(pVCpu, &u8Tpr, NULL /* pfPending */, NULL /* pu8PendingIrq */);
    719719            if (RT_FAILURE(rc))
    720720            {

  • trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp

    r106061 r107113  
    3939#include <VBox/vmm/pdmapi.h>
    4040#include <VBox/vmm/pgm.h>
    41 #include <VBox/vmm/apic.h>
     41#include <VBox/vmm/pdmapic.h>
    4242#include <VBox/vmm/em.h>
    4343#include "GIMHvInternal.h"
    … …  
    605605
    606606        case MSR_GIM_HV_TPR:
    607             *puValue = APICHvGetTpr(pVCpu);
     607            *puValue = PDMApicHvGetTpr(pVCpu);
    608608            return VINF_SUCCESS;
    609609
    610610        case MSR_GIM_HV_ICR:
    611             *puValue = APICHvGetIcr(pVCpu);
     611            *puValue = PDMApicHvGetIcr(pVCpu);
    612612            return VINF_SUCCESS;
    613613
    … …  
    630630        case MSR_GIM_HV_APIC_FREQ:
    631631        {
    632             int rc = APICGetTimerFreq(pVM, puValue);
     632            int rc = PDMApicGetTimerFreq(pVM, puValue);
    633633            if (RT_FAILURE(rc))
    634634                return VERR_CPUM_RAISE_GP_0;
    … …  
    772772    {
    773773        case MSR_GIM_HV_TPR:
    774             return APICHvSetTpr(pVCpu, uRawValue);
     774            return PDMApicHvSetTpr(pVCpu, uRawValue);
    775775
    776776        case MSR_GIM_HV_EOI:
    777             return APICHvSetEoi(pVCpu, uRawValue);
     777            return PDMApicHvSetEoi(pVCpu, uRawValue);
    778778
    779779        case MSR_GIM_HV_ICR:
    780             return APICHvSetIcr(pVCpu, uRawValue);
     780            return PDMApicHvSetIcr(pVCpu, uRawValue);
    781781
    782782        case MSR_GIM_HV_GUEST_OS_ID:

  • trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp

    r106061 r107113  
    3333#define VMCPU_INCL_CPUM_GST_CTX
    3434#include "HMInternal.h"
    35 #include <VBox/vmm/apic.h>
     35#include <VBox/vmm/pdmapic.h>
    3636#include <VBox/vmm/gim.h>
    3737#include <VBox/vmm/iem.h>
    … …  
    103103            {
    104104                bool fPending;
    105                 int  rc = APICGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
     105                int  rc = PDMApicGetTpr(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
    106106                AssertRC(rc);
    107107
    … …  
    126126                    u8Tpr = (uint8_t)pPatch->uSrcOperand;
    127127
    128                 int rc2 = APICSetTpr(pVCpu, u8Tpr);
     128                int rc2 = PDMApicSetTpr(pVCpu, u8Tpr);
    129129                AssertRC(rc2);
    130130                pCtx->rip += pPatch->cbOp;

  • trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

    r106061 r107113  
    124124#include <VBox/vmm/iem.h>
    125125#include <VBox/vmm/cpum.h>
    126 #include <VBox/vmm/apic.h>
     126#include <VBox/vmm/pdmapic.h>
    127127#include <VBox/vmm/pdm.h>
    128128#include <VBox/vmm/pgm.h>

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp

    r106362 r107113  
    3535#include <VBox/vmm/iem.h>
    3636#include <VBox/vmm/cpum.h>
    37 #include <VBox/vmm/apic.h>
     37#include <VBox/vmm/pdmapic.h>
    3838#include <VBox/vmm/pdm.h>
    3939#include <VBox/vmm/pgm.h>
    … …  
    56995699#endif
    57005700            uint8_t uTpr;
    5701             int rc = APICGetTpr(pVCpu, &uTpr, NULL, NULL);
     5701            int rc = PDMApicGetTpr(pVCpu, &uTpr, NULL, NULL);
    57025702            if (RT_SUCCESS(rc))
    57035703                crX = uTpr >> 4;
    … …  
    62986298#endif
    62996299            uint8_t const u8Tpr = (uint8_t)uNewCrX << 4;
    6300             APICSetTpr(pVCpu, u8Tpr);
     6300            PDMApicSetTpr(pVCpu, u8Tpr);
    63016301            rcStrict = VINF_SUCCESS;
    63026302            break;

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImplSvmInstr.cpp

    r106061 r107113  
    3333#define VMCPU_INCL_CPUM_GST_CTX
    3434#include <VBox/vmm/iem.h>
    35 #include <VBox/vmm/apic.h>
     35#include <VBox/vmm/pdmapic.h>
    3636#include <VBox/vmm/cpum.h>
    3737#include <VBox/vmm/dbgf.h>

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp

    r106061 r107113  
    3333#define VMCPU_INCL_CPUM_GST_CTX
    3434#include <VBox/vmm/iem.h>
    35 #include <VBox/vmm/apic.h>
    3635#include <VBox/vmm/cpum.h>
    3736#include <VBox/vmm/dbgf.h>
    … …  
    4948#include <VBox/err.h>
    5049#include <VBox/param.h>
     50#include <VBox/apic.h>
    5151#include <VBox/disopcode-x86-amd64.h>
    5252#include <iprt/asm-math.h>

  • trunk/src/VBox/VMM/VMMAll/IEMAllIntprTables.h

    r106061 r107113  
    4242#include <VBox/vmm/iem.h>
    4343#include <VBox/vmm/cpum.h>
    44 #include <VBox/vmm/apic.h>
     44#include <VBox/vmm/pdmapic.h>
    4545#include <VBox/vmm/pdm.h>
    4646#include <VBox/vmm/pgm.h>

  • trunk/src/VBox/VMM/VMMAll/IEMAllThrdFuncs.cpp

    r106427 r107113  
    3737#include <VBox/vmm/iem.h>
    3838#include <VBox/vmm/cpum.h>
    39 #include <VBox/vmm/apic.h>
     39#include <VBox/vmm/pdmapic.h>
    4040#include <VBox/vmm/pdm.h>
    4141#include <VBox/vmm/pgm.h>

  • trunk/src/VBox/VMM/VMMAll/IEMAllThrdFuncsBltIn.cpp

    r106061 r107113  
    3737#include <VBox/vmm/iem.h>
    3838#include <VBox/vmm/cpum.h>
    39 #include <VBox/vmm/apic.h>
     39#include <VBox/vmm/pdmapic.h>
    4040#include <VBox/vmm/pdm.h>
    4141#include <VBox/vmm/pgm.h>

  • trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp

    r106453 r107113  
    5252#include <VBox/vmm/iem.h>
    5353#include <VBox/vmm/cpum.h>
    54 #include <VBox/vmm/apic.h>
     54#include <VBox/vmm/pdmapic.h>
    5555#include <VBox/vmm/pdm.h>
    5656#include <VBox/vmm/pgm.h>

  • trunk/src/VBox/VMM/VMMAll/IEMAllThrdTables.h

    r106401 r107113  
    4343#include <VBox/vmm/iem.h>
    4444#include <VBox/vmm/cpum.h>
    45 #include <VBox/vmm/apic.h>
     45#include <VBox/vmm/pdmapic.h>
    4646#include <VBox/vmm/pdm.h>
    4747#include <VBox/vmm/pgm.h>

  • trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h

    r106519 r107113  
    330330        if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
    331331        {
    332             ADD_REG64(WHvX64RegisterApicBase, APICGetBaseMsrNoCheck(pVCpu));
     332            ADD_REG64(WHvX64RegisterApicBase, PDMApicGetBaseMsrNoCheck(pVCpu));
    333333            ADD_REG64(WHvX64RegisterPat, pVCpu->cpum.GstCtx.msrPAT);
    334334#if 0 /** @todo check if WHvX64RegisterMsrMtrrCap works here... */
    … …  
    815815    {
    816816        Assert(aenmNames[iReg] == WHvX64RegisterCr8);
    817         APICSetTpr(pVCpu, (uint8_t)aValues[iReg].Reg64 << 4);
     817        PDMApicSetTpr(pVCpu, (uint8_t)aValues[iReg].Reg64 << 4);
    818818        iReg++;
    819819    }
    … …  
    950950        {
    951951            Assert(aenmNames[iReg] == WHvX64RegisterApicBase);
    952             const uint64_t uOldBase = APICGetBaseMsrNoCheck(pVCpu);
     952            const uint64_t uOldBase = PDMApicGetBaseMsrNoCheck(pVCpu);
    953953            if (aValues[iReg].Reg64 != uOldBase)
    954954            {
    955955                Log7(("NEM/%u: MSR APICBase changed %RX64 -> %RX64 (%RX64)\n",
    956956                      pVCpu->idCpu, uOldBase, aValues[iReg].Reg64, aValues[iReg].Reg64 ^ uOldBase));
    957                 int rc2 = APICSetBaseMsr(pVCpu, aValues[iReg].Reg64);
     957                int rc2 = PDMApicSetBaseMsr(pVCpu, aValues[iReg].Reg64);
    958958                AssertLogRelMsg(rc2 == VINF_SUCCESS, ("%Rrc %RX64\n", rc2, aValues[iReg].Reg64));
    959959            }
    … …  
    14601460                                                                    pExitCtx->ExecutionState.InterruptShadow,
    14611461                                                                    pExitCtx->Rip);
    1462     APICSetTpr(pVCpu, pExitCtx->Cr8 << 4);
     1462    PDMApicSetTpr(pVCpu, pExitCtx->Cr8 << 4);
    14631463
    14641464    pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_APIC_TPR);
    … …  
    23922392    if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
    23932393    {
    2394         APICUpdatePendingInterrupts(pVCpu);
     2394        PDMApicUpdatePendingInterrupts(pVCpu);
    23952395        if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
    23962396                                      | VMCPU_FF_INTERRUPT_NMI  | VMCPU_FF_INTERRUPT_SMI))
    … …  
    24792479            uint8_t bTpr = 0;
    24802480            uint8_t bPendingIntr = 0;
    2481             int rc = APICGetTpr(pVCpu, &bTpr, &fPendingIntr, &bPendingIntr);
     2481            int rc = PDMApicGetTpr(pVCpu, &bTpr, &fPendingIntr, &bPendingIntr);
    24822482            AssertRC(rc);
    24832483            *pfInterruptWindows |= ((bPendingIntr >> 4) << NEM_WIN_INTW_F_PRIO_SHIFT) | NEM_WIN_INTW_F_REGULAR;

  • trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

    r106061 r107113  
    3939# include <VBox/vmm/gic.h>
    4040#else
    41 # include <VBox/vmm/apic.h>
     41# include <VBox/vmm/pdmapic.h>
    4242#endif
    4343
    … …  
    7676
    7777        uint32_t uTagSrc;
    78         rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
     78        rc = PDMApicGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
    7979        if (RT_SUCCESS(rc))
    8080        {
    … …  
    326326VMM_INT_DECL(bool) PDMHasApic(PVM pVM)
    327327{
    328     return pVM->pdm.s.Apic.pDevInsR3 != NIL_RTR3PTR;
     328    return pVM->pdm.s.Ic.pDevInsR3 != NIL_RTR3PTR;
    329329}
    330330

  • trunk/src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h

    r106362 r107113  
    17001700        {
    17011701            if (   PDMHasApic(pVCpu->CTX_SUFF(pVM))
    1702                 && APICIsEnabled(pVCpu))
     1702                && PDMApicIsEnabled(pVCpu))
    17031703            {
    17041704                /*
    … …  
    17101710                    uint8_t u8Tpr         = 0;
    17111711                    uint8_t u8PendingIntr = 0;
    1712                     int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
     1712                    int rc = PDMApicGetTpr(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
    17131713                    AssertRC(rc);
    17141714
    … …  
    43514351     */
    43524352    if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
    4353         APICUpdatePendingInterrupts(pVCpu);
     4353        PDMApicUpdatePendingInterrupts(pVCpu);
    43544354
    43554355    /*
    … …  
    49714971                    /*
    49724972                     * If the CPU doesn't have TPR shadowing, we will always get a VM-exit on TPR changes and
    4973                      * APICSetTpr() will end up setting the VMCPU_FF_INTERRUPT_APIC if required, so there is no
     4973                     * PDMApicSetTpr() will end up setting the VMCPU_FF_INTERRUPT_APIC if required, so there is no
    49744974                     * need to re-set this force-flag here.
    49754975                     */
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