VirtualBox

Changeset 107113 in vbox for trunk/src/VBox/VMM/VMMR3


Ignore:
Timestamp:
Nov 22, 2024 10:48:00 AM (3 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
166080
Message:

VMM: bugref:10759 Restructure the APIC to allow different backends to be used.

Location:
trunk/src/VBox/VMM/VMMR3
Files:
18 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r106518 r107113  
    3333#include <VBox/log.h>
    3434#include "APICInternal.h"
    35 #include <VBox/vmm/apic.h>
    3635#include <VBox/vmm/cpum.h>
    3736#include <VBox/vmm/hm.h>
    … …  
    217216
    218217/**
    219  * Receives an INIT IPI.
    220  *
    221  * @param   pVCpu   The cross context virtual CPU structure.
    222  */
    223 VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
    224 {
    225     VMCPU_ASSERT_EMT(pVCpu);
    226     LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
    227     apicInitIpi(pVCpu);
    228 }
    229 
    230 
    231 /**
    232  * Sets whether Hyper-V compatibility mode (MSR interface) is enabled or not.
    233  *
    234  * This mode is a hybrid of xAPIC and x2APIC modes, some caveats:
    235  * 1. MSRs are used even ones that are missing (illegal) in x2APIC like DFR.
    236  * 2. A single ICR is used by the guest to send IPIs rather than 2 ICR writes.
    237  * 3. It is unclear what the behaviour will be when invalid bits are set,
    238  *    currently we follow x2APIC behaviour of causing a \#GP.
    239  *
    240  * @param   pVM                 The cross context VM structure.
    241  * @param   fHyperVCompatMode   Whether the compatibility mode is enabled.
    242  */
    243 VMMR3_INT_DECL(void) APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode)
    244 {
    245     Assert(pVM);
     218 * @interface_method_impl{PDMAPICBACKEND,pfnHvSetCompatMode}
     219 */
     220DECLCALLBACK(int) apicR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode)
     221{
    246222    PAPIC pApic = VM_TO_APIC(pVM);
     223    if (pApic->fHyperVCompatMode ^ fHyperVCompatMode)
     224        LogRel(("APIC: %s Hyper-V x2APIC compatibility mode\n", fHyperVCompatMode ? "Enabling" : "Disabling"));
     225
    247226    pApic->fHyperVCompatMode = fHyperVCompatMode;
    248 
    249     if (fHyperVCompatMode)
    250         LogRel(("APIC: Enabling Hyper-V x2APIC compatibility mode\n"));
    251 
    252227    int rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
    253228    AssertLogRelRC(rc);
     229    return rc;
    254230}
    255231
    … …  
    977953
    978954        /* Update interrupts from the pending-interrupts bitmaps to the IRR. */
    979         APICUpdatePendingInterrupts(pVCpu);
     955        PDMApicUpdatePendingInterrupts(pVCpu);
    980956
    981957        /* Save the auxiliary data. */
    … …  
    11391115        uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
    11401116        Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
    1141         apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE, 0 /* uSrcTag */);
     1117        apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE, false /* fAutoEoi */, 0 /* uSrcTag */);
    11421118    }
    11431119
    … …  
    14711447     */
    14721448    rc = PDMDevHlpApicRegister(pDevIns);
     1449    AssertLogRelRCReturn(rc, rc);
     1450
     1451    rc = PDMApicRegisterBackend(pVM, PDMAPICBACKENDTYPE_VBOX, &g_ApicBackend);
    14731452    AssertLogRelRCReturn(rc, rc);
    14741453
    … …  
    15861565
    15871566        APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs,
    1588                                                        "/PROF/CPU%u/APIC/UpdatePendingInterrupts", "Profiling of APICUpdatePendingInterrupts");
     1567                                                       "/PROF/CPU%u/APIC/UpdatePendingInterrupts", "Profiling of apicUpdatePendingInterrupts");
    15891568        APIC_PROF_COUNTER(&pApicCpu->StatPostIntr,     "/PROF/CPU%u/APIC/PostInterrupt",  "Profiling of APICPostInterrupt");
    15901569#endif

  • trunk/src/VBox/VMM/VMMR3/CPUM.cpp

    r106061 r107113  
    122122#include <VBox/vmm/cpumctx-v1_6.h>
    123123#include <VBox/vmm/pgm.h>
    124 #include <VBox/vmm/apic.h>
     124#include <VBox/vmm/pdmapic.h>
    125125#include <VBox/vmm/mm.h>
    126126#include <VBox/vmm/em.h>

  • trunk/src/VBox/VMM/VMMR3/CPUMDbg-armv8.cpp

    r106365 r107113  
    3333#include <VBox/vmm/cpum.h>
    3434#include <VBox/vmm/dbgf.h>
    35 #include <VBox/vmm/apic.h>
     35#include <VBox/vmm/pdmapic.h>
    3636#include "CPUMInternal-armv8.h"
    3737#include <VBox/vmm/vm.h>

  • trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp

    r106061 r107113  
    3333#include <VBox/vmm/cpum.h>
    3434#include <VBox/vmm/dbgf.h>
    35 #include <VBox/vmm/apic.h>
     35#include <VBox/vmm/pdmapic.h>
    3636#include "CPUMInternal.h"
    3737#include <VBox/vmm/vm.h>
    … …  
    501501        case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
    502502        case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
    503         case 8: rc = APICSetTpr(pVCpu, (uint8_t)(u64Value << 4)); break;
     503        case 8: rc = PDMApicSetTpr(pVCpu, (uint8_t)(u64Value << 4)); break;
    504504        default:
    505505            AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE);

  • trunk/src/VBox/VMM/VMMR3/DBGFCoreWrite.cpp

    r106061 r107113  
    6969#include <VBox/vmm/cpum.h>
    7070#include <VBox/vmm/pgm.h>
    71 #include <VBox/vmm/apic.h>
     71#include <VBox/vmm/pdmapic.h>
    7272#include <VBox/vmm/dbgf.h>
    7373#include <VBox/vmm/dbgfcorefmt.h>
    … …  
    390390    pDbgfCpu->msrSFMASK       = pCtx->msrSFMASK;
    391391    pDbgfCpu->msrKernelGSBase = pCtx->msrKERNELGSBASE;
    392     pDbgfCpu->msrApicBase     = APICGetBaseMsrNoCheck(pVCpu);
     392    pDbgfCpu->msrApicBase     = PDMApicGetBaseMsrNoCheck(pVCpu);
    393393    pDbgfCpu->msrTscAux       = CPUMGetGuestTscAux(pVCpu);
    394394    pDbgfCpu->aXcr[0]         = pCtx->aXcr[0];

  • trunk/src/VBox/VMM/VMMR3/EM.cpp

    r106375 r107113  
    5757#include <VBox/vmm/dbgf.h>
    5858#include <VBox/vmm/pgm.h>
    59 #include <VBox/vmm/apic.h>
     59#include <VBox/vmm/pdmapic.h>
    6060#include <VBox/vmm/tm.h>
    6161#include <VBox/vmm/mm.h>
    … …  
    16591659         */
    16601660        if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
    1661             APICUpdatePendingInterrupts(pVCpu);
     1661            PDMApicUpdatePendingInterrupts(pVCpu);
    16621662
    16631663        /*
    … …  
    26242624                        {
    26252625                            if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
    2626                                 APICUpdatePendingInterrupts(pVCpu);
     2626                                PDMApicUpdatePendingInterrupts(pVCpu);
    26272627
    26282628                            if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC

  • trunk/src/VBox/VMM/VMMR3/GIMHv.cpp

    r106061 r107113  
    3131*********************************************************************************************************************************/
    3232#define LOG_GROUP LOG_GROUP_GIM
    33 #include <VBox/vmm/apic.h>
     33#include <VBox/vmm/pdmapic.h>
    3434#include <VBox/vmm/gim.h>
    3535#include <VBox/vmm/cpum.h>
    … …  
    598598     */
    599599    if (pHv->uHyperHints & GIM_HV_HINT_X2APIC_MSRS)
    600         APICR3HvSetCompatMode(pVM, true);
     600        PDMR3ApicHvSetCompatMode(pVM, true);
    601601
    602602    return rc;
    … …  
    11211121            uint8_t const uVector  = MSR_GIM_HV_SINT_GET_VECTOR(uSint);
    11221122            bool const    fAutoEoi = MSR_GIM_HV_SINT_IS_AUTOEOI(uSint);
    1123             APICHvSendInterrupt(pVCpu, uVector, fAutoEoi, XAPICTRIGGERMODE_EDGE);
     1123            PDMApicHvSendInterrupt(pVCpu, uVector, fAutoEoi, XAPICTRIGGERMODE_EDGE);
    11241124        }
    11251125    }

  • trunk/src/VBox/VMM/VMMR3/GIMMinimal.cpp

    r106061 r107113  
    3434#include <VBox/vmm/cpum.h>
    3535#include <VBox/vmm/tm.h>
    36 #include <VBox/vmm/apic.h>
     36#include <VBox/vmm/pdmapic.h>
    3737#include "GIMInternal.h"
    3838#include <VBox/vmm/vm.h>
    … …  
    106106     *
    107107     * This is done in the init. completed routine as we need PDM to be
    108      * initialized (otherwise APICGetTimerFreq() would fail).
     108     * initialized (otherwise PDMApicGetTimerFreq() would fail).
    109109     */
    110110    CPUMCPUIDLEAF HyperLeaf;
    … …  
    123123         */
    124124        uint64_t uApicFreq;
    125         rc = APICGetTimerFreq(pVM, &uApicFreq);
     125        rc = PDMApicGetTimerFreq(pVM, &uApicFreq);
    126126        AssertLogRelRCReturn(rc, rc);
    127127

  • trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin.cpp

    r106362 r107113  
    4040#include <VBox/vmm/iem.h>
    4141#include <VBox/vmm/em.h>
    42 #include <VBox/vmm/apic.h>
     42#include <VBox/vmm/pdmapic.h>
    4343#include <VBox/vmm/pdm.h>
    4444#include <VBox/vmm/hm.h>
    … …  
    18591859        vmxHCExportGuestApicTpr(pVCpu, pVmxTransient);
    18601860
    1861         rc = APICGetTpr(pVCpu, &pVmxTransient->u8GuestTpr, NULL /*pfPending*/, NULL /*pu8PendingIntr*/);
     1861        rc = PDMApicGetTpr(pVCpu, &pVmxTransient->u8GuestTpr, NULL /*pfPending*/, NULL /*pu8PendingIntr*/);
    18621862        AssertRC(rc);
    18631863

  • trunk/src/VBox/VMM/VMMR3/NEMR3Native-linux.cpp

    r106061 r107113  
    3535#include <VBox/vmm/iem.h>
    3636#include <VBox/vmm/em.h>
    37 #include <VBox/vmm/apic.h>
     37#include <VBox/vmm/pdmapic.h>
    3838#include <VBox/vmm/pdm.h>
    3939#include <VBox/vmm/trpm.h>
    … …  
    704704     * VBox always has the right base register value, so it's one directional.
    705705     */
    706     uint64_t const uApicBase = APICGetBaseMsrNoCheck(pVCpu);
     706    uint64_t const uApicBase = PDMApicGetBaseMsrNoCheck(pVCpu);
    707707    if (   (fExtrn & (  CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_TABLE_MASK | CPUMCTX_EXTRN_CR_MASK
    708708                      | CPUMCTX_EXTRN_EFER      | CPUMCTX_EXTRN_APIC_TPR))
    … …  
    10821082    if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
    10831083    {
    1084         APICUpdatePendingInterrupts(pVCpu);
     1084        PDMApicUpdatePendingInterrupts(pVCpu);
    10851085        if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
    10861086                                      | VMCPU_FF_INTERRUPT_NMI  | VMCPU_FF_INTERRUPT_SMI))
    … …  
    11571157                 */
    11581158                if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_APIC_TPR)
    1159                     APICSetTpr(pVCpu, (uint8_t)pRun->cr8 << 4);
     1159                    PDMApicSetTpr(pVCpu, (uint8_t)pRun->cr8 << 4);
    11601160
    11611161                uint8_t bInterrupt;

  • trunk/src/VBox/VMM/VMMR3/NEMR3Native-win-armv8.cpp

    r107033 r107113  
    5858#include <VBox/vmm/iem.h>
    5959#include <VBox/vmm/em.h>
    60 #include <VBox/vmm/apic.h>
     60#include <VBox/vmm/pdmapic.h>
    6161#include <VBox/vmm/pdm.h>
    6262#include <VBox/vmm/dbgftrace.h>

  • trunk/src/VBox/VMM/VMMR3/NEMR3Native-win.cpp

    r106520 r107113  
    5858#include <VBox/vmm/iem.h>
    5959#include <VBox/vmm/em.h>
    60 #include <VBox/vmm/apic.h>
     60#include <VBox/vmm/pdmapic.h>
    6161#include <VBox/vmm/pdm.h>
    6262#include <VBox/vmm/dbgftrace.h>

  • trunk/src/VBox/VMM/VMMR3/PDM.cpp

    r106061 r107113  
    605605     * The registered APIC.
    606606     */
    607     if (pVM->pdm.s.Apic.pDevInsRC)
    608         pVM->pdm.s.Apic.pDevInsRC           += offDelta;
     607    if (pVM->pdm.s.Ic.pDevInsRC)
     608        pVM->pdm.s.Ic.pDevInsRC             += offDelta;
    609609
    610610    /*

  • trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

    r106061 r107113  
    41934193     * as they need to communicate and share state easily.
    41944194     */
    4195     AssertMsgReturnStmt(pVM->pdm.s.Apic.pDevInsR3 == NULL,
     4195    AssertMsgReturnStmt(pVM->pdm.s.Ic.pDevInsR3 == NULL,
    41964196                        ("%s/%u: Only one APIC device is supported!\n", pDevIns->pReg->szName, pDevIns->iInstance),
    41974197                        RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw),
    … …  
    42014201     * Set the ring-3 and raw-mode bits, leave the ring-0 to ring-0 setup.
    42024202     */
    4203     pVM->pdm.s.Apic.pDevInsR3 = pDevIns;
     4203    pVM->pdm.s.Ic.pDevInsR3 = pDevIns;
    42044204#ifdef VBOX_WITH_RAW_MODE_KEEP
    4205     pVM->pdm.s.Apic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
    4206     Assert(pVM->pdm.s.Apic.pDevInsRC || !VM_IS_RAW_MODE_ENABLED(pVM));
     4205    pVM->pdm.s.Ic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
     4206    Assert(pVM->pdm.s.Ic.pDevInsRC || !VM_IS_RAW_MODE_ENABLED(pVM));
    42074207#endif
    42084208
    … …  
    42454245     * If the I/O APIC does GC stuff so must the APIC.
    42464246     */
    4247     AssertMsgReturnStmt(pVM->pdm.s.Apic.pDevInsR3 != NULL,
     4247    AssertMsgReturnStmt(pVM->pdm.s.Ic.pDevInsR3 != NULL,
    42484248                        ("Configuration error / Init order error! No APIC!\n"),
    42494249                        RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw),

  • trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp

    r106061 r107113  
    3636#include <VBox/vmm/hm.h>
    3737#ifndef VBOX_VMM_TARGET_ARMV8
    38 # include <VBox/vmm/apic.h>
     38# include <VBox/vmm/pdmapic.h>
    3939#endif
    4040#include <VBox/vmm/vm.h>
    … …  
    7272#else
    7373    PVMCPU pVCpu = pVM->apCpusR3[0];  /* for PIC we always deliver to CPU 0, SMP uses APIC */
    74     APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
     74    PDMApicSetLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
    7575#endif
    7676}
    … …  
    9191#else
    9292    PVMCPU pVCpu = pVM->apCpusR3[0];  /* for PIC we always deliver to CPU 0, SMP uses APIC */
    93     APICLocalInterrupt(pVCpu, 0 /* u8Pin */,  0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
     93    PDMApicSetLocalInterrupt(pVCpu, 0 /* u8Pin */,  0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
    9494#endif
    9595}
    … …  
    146146#else
    147147    PVM pVM = pDevIns->Internal.s.pVMR3;
    148     return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
     148    return PDMApicBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
    149149#endif
    150150}

  • trunk/src/VBox/VMM/VMMR3/PDMDevice.cpp

    r106476 r107113  
    3838# include <VBox/vmm/pmu.h>
    3939#else
    40 # include <VBox/vmm/apic.h>
     40# include <VBox/vmm/pdmapic.h>
    4141#endif
    4242#include <VBox/vmm/cfgm.h>

  • trunk/src/VBox/VMM/VMMR3/VM.cpp

    r106061 r107113  
    6969#include <VBox/vmm/iem.h>
    7070#include <VBox/vmm/nem.h>
    71 #include <VBox/vmm/apic.h>
     71#include <VBox/vmm/pdmapic.h>
    7272#include <VBox/vmm/tm.h>
    7373#include <VBox/vmm/stam.h>

  • trunk/src/VBox/VMM/VMMR3/VMM.cpp

    r106061 r107113  
    133133# include <VBox/vmm/gic.h>
    134134#else
    135 # include <VBox/vmm/apic.h>
     135# include <VBox/vmm/pdmapic.h>
    136136#endif
    137137#include <VBox/vmm/ssm.h>
    … …  
    14351435    PDMR3ResetCpu(pVCpu);   /* Only clears pending interrupts force flags */
    14361436# if !defined(VBOX_VMM_TARGET_ARMV8)
    1437     APICR3InitIpi(pVCpu);
     1437    PDMR3ApicInitIpi(pVCpu);
    14381438# endif
    14391439    TRPMR3ResetCpu(pVCpu);
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