Changeset 107147 in vbox
- Timestamp:
- Nov 26, 2024 11:08:34 AM (7 weeks ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-4-template.mac (modified) (1 diff)
-
bs3-cpu-instr-4.c32 (modified) (11 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac
r106974 r107147 1135 1135 EMIT_INSTR_PLUS_ICEBP vroundss, XMM1, XMM2, XMM2, 008h 1136 1136 EMIT_INSTR_PLUS_ICEBP_C64 vroundss, XMM8, XMM8, XMM8, 008h 1137 1138 ; 1139 ;; comiss 1140 ; 1141 EMIT_INSTR_PLUS_ICEBP comiss, XMM1, XMM2 1142 EMIT_INSTR_PLUS_ICEBP comiss, XMM1, FSxBX 1143 EMIT_INSTR_PLUS_ICEBP comiss, XMM1, XMM1 1144 EMIT_INSTR_PLUS_ICEBP_C64 comiss, XMM8, XMM9 1145 EMIT_INSTR_PLUS_ICEBP_C64 comiss, XMM8, FSxBX 1146 EMIT_INSTR_PLUS_ICEBP_C64 comiss, XMM8, XMM8 1147 1148 EMIT_INSTR_PLUS_ICEBP vcomiss, XMM1, XMM2 1149 EMIT_INSTR_PLUS_ICEBP vcomiss, XMM1, FSxBX 1150 EMIT_INSTR_PLUS_ICEBP vcomiss, XMM1, XMM1 1151 EMIT_INSTR_PLUS_ICEBP_C64 vcomiss, XMM8, XMM9 1152 EMIT_INSTR_PLUS_ICEBP_C64 vcomiss, XMM8, FSxBX 1153 EMIT_INSTR_PLUS_ICEBP_C64 vcomiss, XMM8, XMM8 1154 1155 ; 1156 ;; ucomiss 1157 ; 1158 EMIT_INSTR_PLUS_ICEBP ucomiss, XMM1, XMM2 1159 EMIT_INSTR_PLUS_ICEBP ucomiss, XMM1, FSxBX 1160 EMIT_INSTR_PLUS_ICEBP ucomiss, XMM1, XMM1 1161 EMIT_INSTR_PLUS_ICEBP_C64 ucomiss, XMM8, XMM9 1162 EMIT_INSTR_PLUS_ICEBP_C64 ucomiss, XMM8, FSxBX 1163 EMIT_INSTR_PLUS_ICEBP_C64 ucomiss, XMM8, XMM8 1164 1165 EMIT_INSTR_PLUS_ICEBP vucomiss, XMM1, XMM2 1166 EMIT_INSTR_PLUS_ICEBP vucomiss, XMM1, FSxBX 1167 EMIT_INSTR_PLUS_ICEBP vucomiss, XMM1, XMM1 1168 EMIT_INSTR_PLUS_ICEBP_C64 vucomiss, XMM8, XMM9 1169 EMIT_INSTR_PLUS_ICEBP_C64 vucomiss, XMM8, FSxBX 1170 EMIT_INSTR_PLUS_ICEBP_C64 vucomiss, XMM8, XMM8 1171 1172 ; 1173 ;; comisd 1174 ; 1175 EMIT_INSTR_PLUS_ICEBP comisd, XMM1, XMM2 1176 EMIT_INSTR_PLUS_ICEBP comisd, XMM1, FSxBX 1177 EMIT_INSTR_PLUS_ICEBP comisd, XMM1, XMM1 1178 EMIT_INSTR_PLUS_ICEBP_C64 comisd, XMM8, XMM9 1179 EMIT_INSTR_PLUS_ICEBP_C64 comisd, XMM8, FSxBX 1180 EMIT_INSTR_PLUS_ICEBP_C64 comisd, XMM8, XMM8 1181 1182 EMIT_INSTR_PLUS_ICEBP vcomisd, XMM1, XMM2 1183 EMIT_INSTR_PLUS_ICEBP vcomisd, XMM1, FSxBX 1184 EMIT_INSTR_PLUS_ICEBP vcomisd, XMM1, XMM1 1185 EMIT_INSTR_PLUS_ICEBP_C64 vcomisd, XMM8, XMM9 1186 EMIT_INSTR_PLUS_ICEBP_C64 vcomisd, XMM8, FSxBX 1187 EMIT_INSTR_PLUS_ICEBP_C64 vcomisd, XMM8, XMM8 1188 1189 ; 1190 ;; ucomisd 1191 ; 1192 EMIT_INSTR_PLUS_ICEBP ucomisd, XMM1, XMM2 1193 EMIT_INSTR_PLUS_ICEBP ucomisd, XMM1, FSxBX 1194 EMIT_INSTR_PLUS_ICEBP ucomisd, XMM1, XMM1 1195 EMIT_INSTR_PLUS_ICEBP_C64 ucomisd, XMM8, XMM9 1196 EMIT_INSTR_PLUS_ICEBP_C64 ucomisd, XMM8, FSxBX 1197 EMIT_INSTR_PLUS_ICEBP_C64 ucomisd, XMM8, XMM8 1198 1199 EMIT_INSTR_PLUS_ICEBP vucomisd, XMM1, XMM2 1200 EMIT_INSTR_PLUS_ICEBP vucomisd, XMM1, FSxBX 1201 EMIT_INSTR_PLUS_ICEBP vucomisd, XMM1, XMM1 1202 EMIT_INSTR_PLUS_ICEBP_C64 vucomisd, XMM8, XMM9 1203 EMIT_INSTR_PLUS_ICEBP_C64 vucomisd, XMM8, FSxBX 1204 EMIT_INSTR_PLUS_ICEBP_C64 vucomisd, XMM8, XMM8 1137 1205 1138 1206 ; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32
r107048 r107147 2463 2463 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 2464 2464 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ 2465 uint 8_t afPadding[2]; /**< Alignment padding.*/2465 uint16_t afEflOut; /**< x86 eflags, if nonzero */ 2466 2466 } BS3CPUINSTR4_TEST1_VALUES_T; 2467 2467 typedef BS3CPUINSTR4_TEST1_VALUES_T BS3_FAR *PBS3CPUINSTR4_TEST1_VALUES_T; … … 2479 2479 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 2480 2480 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ 2481 uint 8_t afPadding[2]; /**< Alignment padding.*/2481 uint16_t afEflOut; /**< x86 eflags, if nonzero */ 2482 2482 } BS3CPUINSTR4_TEST1_VALUES_PS_T; 2483 2483 AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); … … 2501 2501 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 2502 2502 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ 2503 uint 8_t afPadding[2]; /**< Alignment padding.*/2503 uint16_t afEflOut; /**< x86 eflags, if nonzero */ 2504 2504 } BS3CPUINSTR4_TEST1_VALUES_PD_T; 2505 2505 AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); … … 2523 2523 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 2524 2524 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ 2525 uint 8_t afPadding[2]; /**< Alignment padding.*/2525 uint16_t afEflOut; /**< x86 eflags, if nonzero */ 2526 2526 } BS3CPUINSTR4_TEST1_VALUES_SS_T; 2527 2527 AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); … … 2545 2545 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 2546 2546 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ 2547 uint 8_t afPadding[2]; /**< Alignment padding.*/2547 uint16_t afEflOut; /**< x86 eflags, if nonzero */ 2548 2548 } BS3CPUINSTR4_TEST1_VALUES_SD_T; 2549 2549 AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_SD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); … … 2567 2567 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 2568 2568 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ 2569 uint 8_t afPadding[2]; /**< Alignment padding.*/2569 uint16_t afEflOut; /**< x86 eflags, if nonzero */ 2570 2570 } BS3CPUINSTR4_TEST1_VALUES_PD2PS_T; 2571 2571 AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PD2PS_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); … … 2589 2589 uint32_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 2590 2590 uint32_t u256ExpectedMxCsr; /**< Expected MXCSR for a 256-bit instructions. */ 2591 uint 8_t afPadding[2]; /**< Alignment padding.*/2591 uint16_t afEflOut; /**< x86 eflags, if nonzero */ 2592 2592 } BS3CPUINSTR4_TEST1_VALUES_PS2PD_T; 2593 2593 AssertCompile(sizeof(BS3CPUINSTR4_TEST1_VALUES_PS2PD_T) == sizeof(BS3CPUINSTR4_TEST1_VALUES_T)); … … 2598 2598 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS2PD_T, u128ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u128ExpectedMxCsr); 2599 2599 AssertCompileMembersSameSizeAndOffset(BS3CPUINSTR4_TEST1_VALUES_PS2PD_T, u256ExpectedMxCsr, BS3CPUINSTR4_TEST1_VALUES_T, u256ExpectedMxCsr); 2600 2601 #define BS3_EFLAGS_EXPECTED RT_BIT_32(15) 2600 2602 2601 2603 typedef struct BS3CPUINSTR4_TEST1_T … … 3013 3015 pTrapFrame->Ctx.rflags.u32 |= X86_EFL_AC; 3014 3016 } 3017 if (fNonFpOK && !fFpXcptExpected && (pValues->afEflOut & BS3_EFLAGS_EXPECTED)) 3018 pCtx->rflags.u32 = pCtx->rflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF) | (pValues->afEflOut & ~BS3_EFLAGS_EXPECTED); 3015 3019 if (bXcptExpect == X86_XCPT_PF) 3016 3020 pCtx->cr2.u = (uintptr_t)puMemOp; … … 18554 18558 18555 18559 18560 typedef struct BS3CPUINSTR4_COMISS_VALUES_T 18561 { 18562 RTFLOAT32U uSrc1; 18563 RTFLOAT32U uSrc2; 18564 uint16_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ 18565 uint16_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 18566 uint16_t afEflOut; 18567 } BS3CPUINSTR4_COMISS_VALUES_T; 18568 18569 static DECLCALLBACK(PBS3CPUINSTR4_TEST1_VALUES_T) bs3CpuInstr4_WorkerTestType1_Provider_comiss(void *paValues, const unsigned cValues, const unsigned iVal) 18570 { 18571 static BS3CPUINSTR4_TEST1_VALUES_PS_T sValues; 18572 BS3CPUINSTR4_COMISS_VALUES_T *psValuesIn = &((BS3CPUINSTR4_COMISS_VALUES_T *)paValues)[iVal]; 18573 unsigned iCnt; 18574 18575 sValues.uSrc1.ar32[0] = psValuesIn->uSrc1; 18576 sValues.uSrc2.ar32[0] = psValuesIn->uSrc2; 18577 sValues.uDstOut.ar32[0] = psValuesIn->uSrc2; 18578 for (iCnt = 1; iCnt < RT_ELEMENTS(sValues.uSrc1.ymm.au32); iCnt++) 18579 { 18580 sValues.uSrc1.ymm.au32[iCnt] = bs3CpuInstrX_SimpleRand(); 18581 sValues.uSrc2.ymm.au32[iCnt] = bs3CpuInstrX_SimpleRand(); 18582 sValues.uDstOut.ymm.au32[iCnt] = sValues.uSrc2.ymm.au32[iCnt]; 18583 } 18584 sValues.uMxCsr = psValuesIn->uMxCsr; 18585 sValues.u128ExpectedMxCsr = psValuesIn->u128ExpectedMxCsr; 18586 sValues.afEflOut = psValuesIn->afEflOut; 18587 return (PBS3CPUINSTR4_TEST1_VALUES_T)&sValues; 18588 } 18589 18590 #define COMISS_UN (BS3_EFLAGS_EXPECTED | X86_EFL_CF | X86_EFL_PF | X86_EFL_ZF) 18591 #define COMISS_GT (BS3_EFLAGS_EXPECTED | 0) 18592 #define COMISS_LT (BS3_EFLAGS_EXPECTED | X86_EFL_CF) 18593 #define COMISS_EQ (BS3_EFLAGS_EXPECTED | X86_EFL_ZF) 18594 18595 /* Standard */ 18596 static BS3CPUINSTR4_COMISS_VALUES_T const s_aValuesComiss[] = 18597 { 18598 /*src1*/ /*src2*/ /*mxcsr:in*/ /*128:out*/ /*x86eflags:out*/ 18599 /* 18600 * Zero. 18601 */ 18602 /* 0*/{ FP32_0(0), FP32_0(0), 0, 0, COMISS_EQ }, 18603 { FP32_0(1), FP32_0(1), 0, 0, COMISS_EQ }, 18604 { FP32_0(0), FP32_0(1), 0, 0, COMISS_EQ }, 18605 /* 18606 * Infinity. 18607 */ 18608 /* 3*/{ FP32_INF(0), FP32_INF(0), 0, 0, COMISS_EQ }, 18609 { FP32_INF(1), FP32_INF(1), 0, 0, COMISS_EQ }, 18610 { FP32_INF(0), FP32_INF(1), 0, 0, COMISS_LT }, 18611 { FP32_INF(1), FP32_INF(0), 0, 0, COMISS_GT }, 18612 { FP32_INF(1), FP32_2(0), 0, 0, COMISS_GT }, 18613 { FP32_INF(0), FP32_1(0), 0, 0, COMISS_LT }, 18614 /* 18615 * Normals. 18616 */ 18617 /* 9*/{ FP32_0_1(0), FP32_0(0), 0, 0, COMISS_LT }, 18618 { FP32_NORM_V1(0), FP32_NORM_V1(1), 0, 0, COMISS_LT }, 18619 { FP32_NORM_V2(0), FP32_NORM_V3(0), 0, 0, COMISS_GT }, 18620 { FP32_NORM_V0(1), FP32_NORM_V0(1), 0, 0, COMISS_EQ }, 18621 /* 18622 * Denormals. 18623 */ 18624 /*13*/{ FP32_DENORM_MAX(0), FP32_0(0), 0, X86_MXCSR_DE, COMISS_LT }, 18625 { FP32_DENORM_MIN(1), FP32_0(0), 0, X86_MXCSR_DE, COMISS_GT }, 18626 { FP32_DENORM_MIN(1), FP32_0(0), X86_MXCSR_RC_UP, X86_MXCSR_DE | X86_MXCSR_RC_UP, COMISS_GT }, 18627 { FP32_DENORM_MIN(1), FP32_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_DE | X86_MXCSR_RC_DOWN, COMISS_GT }, 18628 { FP32_DENORM_MIN(1), FP32_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_DE | X86_MXCSR_RC_ZERO, COMISS_GT }, 18629 { FP32_DENORM_MIN(1), FP32_0(0), X86_MXCSR_FZ, X86_MXCSR_DE | X86_MXCSR_FZ, COMISS_GT }, 18630 { FP32_DENORM_MIN(1), FP32_0(0), X86_MXCSR_DAZ, X86_MXCSR_DAZ, COMISS_EQ }, 18631 { FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), 0, X86_MXCSR_DE, COMISS_EQ }, 18632 { FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), 0, X86_MXCSR_DE, COMISS_EQ }, 18633 /* 18634 * Invalids. 18635 */ 18636 /*22*/{ FP32_QNAN_MAX(0), FP32_SNAN_V0(0), 0, X86_MXCSR_IE, COMISS_UN }, 18637 { FP32_SNAN_V1(1), FP32_QNAN_V2(0), 0, X86_MXCSR_IE, COMISS_UN }, 18638 { FP32_SNAN_MAX(0), FP32_QNAN_MAX(0), 0, X86_MXCSR_IE, COMISS_UN }, 18639 { FP32_QNAN_MAX(1), FP32_SNAN_MAX(1), 0, X86_MXCSR_IE, COMISS_UN }, 18640 /* 18641 * Overflow, Underflow not possible. 18642 */ 18643 }; 18644 /* Same-register */ 18645 static BS3CPUINSTR4_COMISS_VALUES_T const s_aValuesComissSR[] = 18646 { 18647 /*src1*/ /*src2*/ /*mxcsr:in*/ /*128:out*/ /*x86eflags:out*/ 18648 /* 18649 * Zero. 18650 */ 18651 /* 0*/{ FP32_0(0), FP32_0(0), 0, 0, COMISS_EQ }, 18652 { FP32_0(1), FP32_0(1), 0, 0, COMISS_EQ }, 18653 /* 18654 * Infinity. 18655 */ 18656 /* 2*/{ FP32_INF(0), FP32_INF(0), 0, 0, COMISS_EQ }, 18657 { FP32_INF(1), FP32_INF(1), 0, 0, COMISS_EQ }, 18658 /* 18659 * Normals. 18660 */ 18661 /* 4*/{ FP32_0_1(0), FP32_0_1(0), 0, 0, COMISS_EQ }, 18662 /* 18663 * Denormals. 18664 */ 18665 /* 5*/{ FP32_DENORM_MAX(0), FP32_DENORM_MAX(0), 0, X86_MXCSR_DE, COMISS_EQ }, 18666 { FP32_DENORM_MIN(1), FP32_DENORM_MIN(1), 0, X86_MXCSR_DE, COMISS_EQ }, 18667 /* 18668 * Invalids. 18669 */ 18670 /* 7*/{ FP32_SNAN_MAX(0), FP32_SNAN_MAX(0), 0, X86_MXCSR_IE, COMISS_UN }, 18671 /* 18672 * Overflow, Underflow not possible. 18673 */ 18674 }; 18675 18676 /* 18677 * [V]COMISS. 18678 */ 18679 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_comiss(uint8_t bMode) 18680 { 18681 /* QNANs for comiss (IE) */ 18682 static BS3CPUINSTR4_COMISS_VALUES_T const s_aValuesComissQC[] = 18683 { 18684 /*src1*/ /*src2*/ /*mxcsr:in*/ /*128:out*/ /*x86eflags:out*/ 18685 /* 0*/{ FP32_QNAN_MAX(0), FP32_QNAN_MAX(0), 0, X86_MXCSR_IE, COMISS_UN }, 18686 { FP32_QNAN_V1(1), FP32_QNAN_V1(1), 0, X86_MXCSR_IE, COMISS_UN }, 18687 { FP32_NORM_V2(0), FP32_QNAN_V1(1), 0, X86_MXCSR_IE, COMISS_UN }, 18688 { FP32_QNAN_V3(0), FP32_NORM_V0(0), 0, X86_MXCSR_IE, COMISS_UN }, 18689 }; 18690 18691 static BS3CPUINSTR4_TEST1_T const s_aTests[] = 18692 { 18693 { BS3_INSTR4_ALL(comiss_XMM1_XMM1), 255, RM_REG, T_SSE, XMM1, XMM1, XMM1, PASS_TEST_ARRAY(s_aValuesComissSR) }, 18694 { BS3_INSTR4_ALL(comiss_XMM1_XMM2), 255, RM_REG, T_SSE, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComiss) }, 18695 { BS3_INSTR4_ALL(comiss_XMM1_FSxBX), 255, RM_MEM, T_SSE, XMM1, FSxBX, XMM1, PASS_TEST_ARRAY(s_aValuesComiss) }, 18696 { BS3_INSTR4_C64(comiss_XMM8_XMM8), 255, RM_REG, T_SSE, XMM8, XMM8, XMM8, PASS_TEST_ARRAY(s_aValuesComissSR) }, 18697 { BS3_INSTR4_C64(comiss_XMM8_XMM9), 255, RM_REG, T_SSE, XMM8, XMM9, XMM8, PASS_TEST_ARRAY(s_aValuesComiss) }, 18698 { BS3_INSTR4_C64(comiss_XMM8_FSxBX), 255, RM_MEM, T_SSE, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComiss) }, 18699 { BS3_INSTR4_ALL(comiss_XMM1_XMM2), 255, RM_REG, T_SSE, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComissQC) }, 18700 { BS3_INSTR4_C64(comiss_XMM8_FSxBX), 255, RM_MEM, T_SSE, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComissQC) }, 18701 18702 { BS3_INSTR4_ALL(vcomiss_XMM1_XMM1), 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM1, PASS_TEST_ARRAY(s_aValuesComissSR) }, 18703 { BS3_INSTR4_ALL(vcomiss_XMM1_XMM2), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComiss) }, 18704 { BS3_INSTR4_ALL(vcomiss_XMM1_FSxBX), 255, RM_MEM, T_AVX_128, XMM1, FSxBX, XMM1, PASS_TEST_ARRAY(s_aValuesComiss) }, 18705 { BS3_INSTR4_C64(vcomiss_XMM8_XMM8), 255, RM_REG, T_AVX_128, XMM8, XMM8, XMM8, PASS_TEST_ARRAY(s_aValuesComissSR) }, 18706 { BS3_INSTR4_C64(vcomiss_XMM8_XMM9), 255, RM_REG, T_AVX_128, XMM8, XMM9, XMM8, PASS_TEST_ARRAY(s_aValuesComiss) }, 18707 { BS3_INSTR4_C64(vcomiss_XMM8_FSxBX), 255, RM_MEM, T_AVX_128, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComiss) }, 18708 { BS3_INSTR4_ALL(vcomiss_XMM1_XMM2), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComissQC) }, 18709 { BS3_INSTR4_C64(vcomiss_XMM8_FSxBX), 255, RM_MEM, T_AVX_128, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComissQC) }, 18710 }; 18711 18712 return bs3CpuInstr4_WorkerTestType1_P(bMode, PASS_ARRAY(s_aTests), PASS_ARRAY(g_aXcptConfig3), bs3CpuInstr4_WorkerTestType1_Provider_comiss); 18713 } 18714 18715 18716 /* 18717 * [V]UCOMISS. 18718 */ 18719 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_ucomiss(uint8_t bMode) 18720 { 18721 /* QNANs for ucomiss (!IE) */ 18722 static BS3CPUINSTR4_COMISS_VALUES_T const s_aValuesComissQU[] = 18723 { 18724 /*src1*/ /*src2*/ /*mxcsr:in*/ /*128:out*/ /*x86eflags:out*/ 18725 /* 0*/{ FP32_QNAN_MAX(0), FP32_QNAN_MAX(0), 0, 0, COMISS_UN }, 18726 { FP32_QNAN_V1(1), FP32_QNAN_V1(1), 0, 0, COMISS_UN }, 18727 { FP32_NORM_V2(0), FP32_QNAN_V1(1), 0, 0, COMISS_UN }, 18728 { FP32_QNAN_V3(0), FP32_NORM_V0(0), 0, 0, COMISS_UN }, 18729 }; 18730 18731 static BS3CPUINSTR4_TEST1_T const s_aTests[] = 18732 { 18733 { BS3_INSTR4_ALL(ucomiss_XMM1_XMM1), 255, RM_REG, T_SSE, XMM1, XMM1, XMM1, PASS_TEST_ARRAY(s_aValuesComissSR) }, 18734 { BS3_INSTR4_ALL(ucomiss_XMM1_XMM2), 255, RM_REG, T_SSE, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComiss) }, 18735 { BS3_INSTR4_ALL(ucomiss_XMM1_FSxBX), 255, RM_MEM, T_SSE, XMM1, FSxBX, XMM1, PASS_TEST_ARRAY(s_aValuesComiss) }, 18736 { BS3_INSTR4_C64(ucomiss_XMM8_XMM8), 255, RM_REG, T_SSE, XMM8, XMM8, XMM8, PASS_TEST_ARRAY(s_aValuesComissSR) }, 18737 { BS3_INSTR4_C64(ucomiss_XMM8_XMM9), 255, RM_REG, T_SSE, XMM8, XMM9, XMM8, PASS_TEST_ARRAY(s_aValuesComiss) }, 18738 { BS3_INSTR4_C64(ucomiss_XMM8_FSxBX), 255, RM_MEM, T_SSE, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComiss) }, 18739 { BS3_INSTR4_ALL(ucomiss_XMM1_XMM2), 255, RM_REG, T_SSE, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComissQU) }, 18740 { BS3_INSTR4_C64(ucomiss_XMM8_FSxBX), 255, RM_MEM, T_SSE, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComissQU) }, 18741 18742 { BS3_INSTR4_ALL(vucomiss_XMM1_XMM1), 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM1, PASS_TEST_ARRAY(s_aValuesComissSR) }, 18743 { BS3_INSTR4_ALL(vucomiss_XMM1_XMM2), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComiss) }, 18744 { BS3_INSTR4_ALL(vucomiss_XMM1_FSxBX), 255, RM_MEM, T_AVX_128, XMM1, FSxBX, XMM1, PASS_TEST_ARRAY(s_aValuesComiss) }, 18745 { BS3_INSTR4_C64(vucomiss_XMM8_XMM8), 255, RM_REG, T_AVX_128, XMM8, XMM8, XMM8, PASS_TEST_ARRAY(s_aValuesComissSR) }, 18746 { BS3_INSTR4_C64(vucomiss_XMM8_XMM9), 255, RM_REG, T_AVX_128, XMM8, XMM9, XMM8, PASS_TEST_ARRAY(s_aValuesComiss) }, 18747 { BS3_INSTR4_C64(vucomiss_XMM8_FSxBX), 255, RM_MEM, T_AVX_128, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComiss) }, 18748 { BS3_INSTR4_ALL(vucomiss_XMM1_XMM2), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComissQU) }, 18749 { BS3_INSTR4_C64(vucomiss_XMM8_FSxBX), 255, RM_MEM, T_AVX_128, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComissQU) }, 18750 }; 18751 18752 return bs3CpuInstr4_WorkerTestType1_P(bMode, PASS_ARRAY(s_aTests), PASS_ARRAY(g_aXcptConfig3), bs3CpuInstr4_WorkerTestType1_Provider_comiss); 18753 } 18754 18755 18756 typedef struct BS3CPUINSTR4_COMISD_VALUES_T 18757 { 18758 RTFLOAT64U uSrc1; 18759 RTFLOAT64U uSrc2; 18760 uint16_t uMxCsr; /**< MXCSR to set prior to executing the instruction. */ 18761 uint16_t u128ExpectedMxCsr; /**< Expected MXCSR for a 128-bit instruction. */ 18762 uint16_t afEflOut; 18763 } BS3CPUINSTR4_COMISD_VALUES_T; 18764 18765 static DECLCALLBACK(PBS3CPUINSTR4_TEST1_VALUES_T) bs3CpuInstr4_WorkerTestType1_Provider_comisd(void *paValues, const unsigned cValues, const unsigned iVal) 18766 { 18767 static BS3CPUINSTR4_TEST1_VALUES_PD_T sValues; 18768 BS3CPUINSTR4_COMISD_VALUES_T *psValuesIn = &((BS3CPUINSTR4_COMISD_VALUES_T *)paValues)[iVal]; 18769 unsigned iCnt; 18770 18771 sValues.uSrc1.ar64[0] = psValuesIn->uSrc1; 18772 sValues.uSrc2.ar64[0] = psValuesIn->uSrc2; 18773 sValues.uDstOut.ar64[0] = psValuesIn->uSrc2; 18774 for (iCnt = 2; iCnt < RT_ELEMENTS(sValues.uSrc1.ymm.au32); iCnt++) 18775 { 18776 sValues.uSrc1.ymm.au32[iCnt] = bs3CpuInstrX_SimpleRand(); 18777 sValues.uSrc2.ymm.au32[iCnt] = bs3CpuInstrX_SimpleRand(); 18778 sValues.uDstOut.ymm.au32[iCnt] = sValues.uSrc2.ymm.au32[iCnt]; 18779 } 18780 sValues.uMxCsr = psValuesIn->uMxCsr; 18781 sValues.u128ExpectedMxCsr = psValuesIn->u128ExpectedMxCsr; 18782 sValues.afEflOut = psValuesIn->afEflOut; 18783 return (PBS3CPUINSTR4_TEST1_VALUES_T)&sValues; 18784 } 18785 18786 /* Standard */ 18787 static BS3CPUINSTR4_COMISD_VALUES_T const s_aValuesComisd[] = 18788 { 18789 /*src1*/ /*src2*/ /*mxcsr:in*/ /*128:out*/ /*x86eflags:out*/ 18790 /* 18791 * Zero. 18792 */ 18793 /* 0*/{ FP64_0(0), FP64_0(0), 0, 0, COMISS_EQ }, 18794 { FP64_0(1), FP64_0(1), 0, 0, COMISS_EQ }, 18795 { FP64_0(0), FP64_0(1), 0, 0, COMISS_EQ }, 18796 /* 18797 * Infinity. 18798 */ 18799 /* 3*/{ FP64_INF(0), FP64_INF(0), 0, 0, COMISS_EQ }, 18800 { FP64_INF(1), FP64_INF(1), 0, 0, COMISS_EQ }, 18801 { FP64_INF(0), FP64_INF(1), 0, 0, COMISS_LT }, 18802 { FP64_INF(1), FP64_INF(0), 0, 0, COMISS_GT }, 18803 { FP64_INF(1), FP64_2(0), 0, 0, COMISS_GT }, 18804 { FP64_INF(0), FP64_1(0), 0, 0, COMISS_LT }, 18805 /* 18806 * Normals. 18807 */ 18808 /* 9*/{ FP64_0_1(0), FP64_0(0), 0, 0, COMISS_LT }, 18809 { FP64_NORM_V1(0), FP64_NORM_V1(1), 0, 0, COMISS_LT }, 18810 { FP64_NORM_V3(0), FP64_NORM_V2(0), 0, 0, COMISS_GT }, 18811 { FP64_NORM_V0(1), FP64_NORM_V0(1), 0, 0, COMISS_EQ }, 18812 /* 18813 * Denormals. 18814 */ 18815 /*13*/{ FP64_DENORM_MAX(0), FP64_0(0), 0, X86_MXCSR_DE, COMISS_LT }, 18816 { FP64_DENORM_MIN(1), FP64_0(0), 0, X86_MXCSR_DE, COMISS_GT }, 18817 { FP64_DENORM_MIN(1), FP64_0(0), X86_MXCSR_RC_UP, X86_MXCSR_DE | X86_MXCSR_RC_UP, COMISS_GT }, 18818 { FP64_DENORM_MIN(1), FP64_0(0), X86_MXCSR_RC_DOWN, X86_MXCSR_DE | X86_MXCSR_RC_DOWN, COMISS_GT }, 18819 { FP64_DENORM_MIN(1), FP64_0(0), X86_MXCSR_RC_ZERO, X86_MXCSR_DE | X86_MXCSR_RC_ZERO, COMISS_GT }, 18820 { FP64_DENORM_MIN(1), FP64_0(0), X86_MXCSR_FZ, X86_MXCSR_DE | X86_MXCSR_FZ, COMISS_GT }, 18821 { FP64_DENORM_MIN(1), FP64_0(0), X86_MXCSR_DAZ, X86_MXCSR_DAZ, COMISS_EQ }, 18822 { FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), 0, X86_MXCSR_DE, COMISS_EQ }, 18823 { FP64_DENORM_MIN(1), FP64_DENORM_MIN(1), 0, X86_MXCSR_DE, COMISS_EQ }, 18824 /* 18825 * Invalids. 18826 */ 18827 /*22*/{ FP64_QNAN_MAX(0), FP64_SNAN_V0(0), 0, X86_MXCSR_IE, COMISS_UN }, 18828 { FP64_SNAN_V1(1), FP64_QNAN_V2(0), 0, X86_MXCSR_IE, COMISS_UN }, 18829 { FP64_SNAN_MAX(0), FP64_QNAN_MAX(0), 0, X86_MXCSR_IE, COMISS_UN }, 18830 { FP64_QNAN_MAX(1), FP64_SNAN_MAX(1), 0, X86_MXCSR_IE, COMISS_UN }, 18831 /* 18832 * Overflow, Underflow not possible. 18833 */ 18834 }; 18835 /* Same-register */ 18836 static BS3CPUINSTR4_COMISD_VALUES_T const s_aValuesComisdSR[] = 18837 { 18838 /*src1*/ /*src2*/ /*mxcsr:in*/ /*128:out*/ /*x86eflags:out*/ 18839 /* 18840 * Zero. 18841 */ 18842 /* 0*/{ FP64_0(0), FP64_0(0), 0, 0, COMISS_EQ }, 18843 { FP64_0(1), FP64_0(1), 0, 0, COMISS_EQ }, 18844 /* 18845 * Infinity. 18846 */ 18847 /* 2*/{ FP64_INF(0), FP64_INF(0), 0, 0, COMISS_EQ }, 18848 { FP64_INF(1), FP64_INF(1), 0, 0, COMISS_EQ }, 18849 /* 18850 * Normals. 18851 */ 18852 /* 4*/{ FP64_0_1(0), FP64_0_1(0), 0, 0, COMISS_EQ }, 18853 /* 18854 * Denormals. 18855 */ 18856 /* 5*/{ FP64_DENORM_MAX(0), FP64_DENORM_MAX(0), 0, X86_MXCSR_DE, COMISS_EQ }, 18857 { FP64_DENORM_MIN(1), FP64_DENORM_MIN(1), 0, X86_MXCSR_DE, COMISS_EQ }, 18858 /* 18859 * Invalids. 18860 */ 18861 /* 7*/{ FP64_SNAN_MAX(0), FP64_SNAN_MAX(0), 0, X86_MXCSR_IE, COMISS_UN }, 18862 /* 18863 * Overflow, Underflow not possible. 18864 */ 18865 }; 18866 18867 /* 18868 * [V]COMISD. 18869 */ 18870 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_comisd(uint8_t bMode) 18871 { 18872 /* QNANs for comisd (IE) */ 18873 static BS3CPUINSTR4_COMISD_VALUES_T const s_aValuesComisdQC[] = 18874 { 18875 /*src1*/ /*src2*/ /*mxcsr:in*/ /*128:out*/ /*x86eflags:out*/ 18876 /* 0*/{ FP64_QNAN_MAX(0), FP64_QNAN_MAX(0), 0, X86_MXCSR_IE, COMISS_UN }, 18877 { FP64_QNAN_V1(1), FP64_QNAN_V1(1), 0, X86_MXCSR_IE, COMISS_UN }, 18878 { FP64_NORM_V2(0), FP64_QNAN_V1(1), 0, X86_MXCSR_IE, COMISS_UN }, 18879 { FP64_QNAN_V3(0), FP64_NORM_V0(0), 0, X86_MXCSR_IE, COMISS_UN }, 18880 }; 18881 18882 static BS3CPUINSTR4_TEST1_T const s_aTests[] = 18883 { 18884 { BS3_INSTR4_ALL(comisd_XMM1_XMM1), 255, RM_REG, T_SSE, XMM1, XMM1, XMM1, PASS_TEST_ARRAY(s_aValuesComisdSR) }, 18885 { BS3_INSTR4_ALL(comisd_XMM1_XMM2), 255, RM_REG, T_SSE, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComisd) }, 18886 { BS3_INSTR4_ALL(comisd_XMM1_FSxBX), 255, RM_MEM, T_SSE, XMM1, FSxBX, XMM1, PASS_TEST_ARRAY(s_aValuesComisd) }, 18887 { BS3_INSTR4_C64(comisd_XMM8_XMM8), 255, RM_REG, T_SSE, XMM8, XMM8, XMM8, PASS_TEST_ARRAY(s_aValuesComisdSR) }, 18888 { BS3_INSTR4_C64(comisd_XMM8_XMM9), 255, RM_REG, T_SSE, XMM8, XMM9, XMM8, PASS_TEST_ARRAY(s_aValuesComisd) }, 18889 { BS3_INSTR4_C64(comisd_XMM8_FSxBX), 255, RM_MEM, T_SSE, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComisd) }, 18890 { BS3_INSTR4_ALL(comisd_XMM1_XMM2), 255, RM_REG, T_SSE, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComisdQC) }, 18891 { BS3_INSTR4_C64(comisd_XMM8_FSxBX), 255, RM_MEM, T_SSE, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComisdQC) }, 18892 18893 { BS3_INSTR4_ALL(vcomisd_XMM1_XMM1), 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM1, PASS_TEST_ARRAY(s_aValuesComisdSR) }, 18894 { BS3_INSTR4_ALL(vcomisd_XMM1_XMM2), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComisd) }, 18895 { BS3_INSTR4_ALL(vcomisd_XMM1_FSxBX), 255, RM_MEM, T_AVX_128, XMM1, FSxBX, XMM1, PASS_TEST_ARRAY(s_aValuesComisd) }, 18896 { BS3_INSTR4_C64(vcomisd_XMM8_XMM8), 255, RM_REG, T_AVX_128, XMM8, XMM8, XMM8, PASS_TEST_ARRAY(s_aValuesComisdSR) }, 18897 { BS3_INSTR4_C64(vcomisd_XMM8_XMM9), 255, RM_REG, T_AVX_128, XMM8, XMM9, XMM8, PASS_TEST_ARRAY(s_aValuesComisd) }, 18898 { BS3_INSTR4_C64(vcomisd_XMM8_FSxBX), 255, RM_MEM, T_AVX_128, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComisd) }, 18899 { BS3_INSTR4_ALL(vcomisd_XMM1_XMM2), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComisdQC) }, 18900 { BS3_INSTR4_C64(vcomisd_XMM8_FSxBX), 255, RM_MEM, T_AVX_128, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComisdQC) }, 18901 }; 18902 18903 return bs3CpuInstr4_WorkerTestType1_P(bMode, PASS_ARRAY(s_aTests), PASS_ARRAY(g_aXcptConfig3), bs3CpuInstr4_WorkerTestType1_Provider_comisd); 18904 } 18905 18906 18907 /* 18908 * [V]UCOMISD. 18909 */ 18910 BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_ucomisd(uint8_t bMode) 18911 { 18912 /* QNANs for ucomisd (!IE) */ 18913 static BS3CPUINSTR4_COMISD_VALUES_T const s_aValuesComisdQU[] = 18914 { 18915 /*src1*/ /*src2*/ /*mxcsr:in*/ /*128:out*/ /*x86eflags:out*/ 18916 /* 0*/{ FP64_QNAN_MAX(0), FP64_QNAN_MAX(0), 0, 0, COMISS_UN }, 18917 { FP64_QNAN_V1(1), FP64_QNAN_V1(1), 0, 0, COMISS_UN }, 18918 { FP64_NORM_V2(0), FP64_QNAN_V1(1), 0, 0, COMISS_UN }, 18919 { FP64_QNAN_V3(0), FP64_NORM_V0(0), 0, 0, COMISS_UN }, 18920 }; 18921 18922 static BS3CPUINSTR4_TEST1_T const s_aTests[] = 18923 { 18924 { BS3_INSTR4_ALL(ucomisd_XMM1_XMM1), 255, RM_REG, T_SSE, XMM1, XMM1, XMM1, PASS_TEST_ARRAY(s_aValuesComisdSR) }, 18925 { BS3_INSTR4_ALL(ucomisd_XMM1_XMM2), 255, RM_REG, T_SSE, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComisd) }, 18926 { BS3_INSTR4_ALL(ucomisd_XMM1_FSxBX), 255, RM_MEM, T_SSE, XMM1, FSxBX, XMM1, PASS_TEST_ARRAY(s_aValuesComisd) }, 18927 { BS3_INSTR4_C64(ucomisd_XMM8_XMM8), 255, RM_REG, T_SSE, XMM8, XMM8, XMM8, PASS_TEST_ARRAY(s_aValuesComisdSR) }, 18928 { BS3_INSTR4_C64(ucomisd_XMM8_XMM9), 255, RM_REG, T_SSE, XMM8, XMM9, XMM8, PASS_TEST_ARRAY(s_aValuesComisd) }, 18929 { BS3_INSTR4_C64(ucomisd_XMM8_FSxBX), 255, RM_MEM, T_SSE, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComisd) }, 18930 { BS3_INSTR4_ALL(ucomisd_XMM1_XMM2), 255, RM_REG, T_SSE, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComisdQU) }, 18931 { BS3_INSTR4_C64(ucomisd_XMM8_FSxBX), 255, RM_MEM, T_SSE, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComisdQU) }, 18932 18933 { BS3_INSTR4_ALL(vucomisd_XMM1_XMM1), 255, RM_REG, T_AVX_128, XMM1, XMM1, XMM1, PASS_TEST_ARRAY(s_aValuesComisdSR) }, 18934 { BS3_INSTR4_ALL(vucomisd_XMM1_XMM2), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComisd) }, 18935 { BS3_INSTR4_ALL(vucomisd_XMM1_FSxBX), 255, RM_MEM, T_AVX_128, XMM1, FSxBX, XMM1, PASS_TEST_ARRAY(s_aValuesComisd) }, 18936 { BS3_INSTR4_C64(vucomisd_XMM8_XMM8), 255, RM_REG, T_AVX_128, XMM8, XMM8, XMM8, PASS_TEST_ARRAY(s_aValuesComisdSR) }, 18937 { BS3_INSTR4_C64(vucomisd_XMM8_XMM9), 255, RM_REG, T_AVX_128, XMM8, XMM9, XMM8, PASS_TEST_ARRAY(s_aValuesComisd) }, 18938 { BS3_INSTR4_C64(vucomisd_XMM8_FSxBX), 255, RM_MEM, T_AVX_128, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComisd) }, 18939 { BS3_INSTR4_ALL(vucomisd_XMM1_XMM2), 255, RM_REG, T_AVX_128, XMM1, XMM2, XMM1, PASS_TEST_ARRAY(s_aValuesComisdQU) }, 18940 { BS3_INSTR4_C64(vucomisd_XMM8_FSxBX), 255, RM_MEM, T_AVX_128, XMM8, FSxBX, XMM8, PASS_TEST_ARRAY(s_aValuesComisdQU) }, 18941 }; 18942 18943 return bs3CpuInstr4_WorkerTestType1_P(bMode, PASS_ARRAY(s_aTests), PASS_ARRAY(g_aXcptConfig3), bs3CpuInstr4_WorkerTestType1_Provider_comisd); 18944 } 18945 18946 18556 18947 /* 18557 18948 * CVTPI2PS. … … 23325 23716 { "[v]roundss", bs3CpuInstr4_v_roundss, 0 }, 23326 23717 { "[v]roundsd", bs3CpuInstr4_v_roundsd, 0 }, 23718 { "[v]comiss", bs3CpuInstr4_v_comiss, 0 }, 23719 { "[v]ucomiss", bs3CpuInstr4_v_ucomiss, 0 }, 23720 { "[v]comisd", bs3CpuInstr4_v_comisd, 0 }, 23721 { "[v]ucomisd", bs3CpuInstr4_v_ucomisd, 0 }, 23327 23722 { "cvtpi2ps", bs3CpuInstr4_cvtpi2ps, 0 }, 23328 23723 { "cvtps2pi", bs3CpuInstr4_cvtps2pi, 0 },
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