Changeset 107278 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Dec 10, 2024 12:54:07 PM (5 weeks ago)

Author:

vboxsync

Message:

VMM/IEM: fix SSE cvtdq2pd raising spurious #GP; bugref:10816; jiraref:VBP-1476

• improperly fixed with a cast; proper fix caused far too much cascading trouble
• improve internal doc of various TODO_XXX_BUG stuff

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (6 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -2092 +2092 @@
         pCtx->cr0.u32 &= ~X86_CR0_TS;
 
-    if (pConfig->fCr4OsFxSR)
-        pCtx->cr4.u32 |= X86_CR4_OSFXSR;
-    else
-        pCtx->cr4.u32 &= ~X86_CR4_OSFXSR;
-
     if (pConfig->fCr4OsXmmExcpt && g_afTypeSupports[T_SSE])
         pCtx->cr4.u32 |= X86_CR4_OSXMMEEXCPT;
@@ -3258 +3253 @@
 /** @todo 'master switch' turns on all IEM misbehaviors documented below */
 #ifdef TODO_EXPOSE_IEM_ERRATA
-# define TODO_X86_MXCSR_PE_IEM
-# define TODO_X86_MXCSR_PE_IEM_SSE
-# define TODO_X86_MXCSR_UE_IEM
-# define TODO_CVTDQ2PD_M64_IEM
-# define TODO_MXCSR_ORDER      /* (test harness issue, not IEM) */
+# define TODO_X86_MXCSR_PE_IEM       /* mul/div instructions: IEM fails to set X86_MXCSR_PE like HW does */
+# define TODO_X86_MXCSR_PE_IEM_SSE   /* sub/mul instructions: IEM fails to set X86_MXCSR_PE like HW does */
+# define TODO_X86_MXCSR_UE_IEM       /* various instructions: IEM fails to set X86_MXCSR_UE like HW does */
+# define TODO_IEM_ASM_COREDUMP       /* certain instructions dump core when x86-on-x86 IEM built *WITHOUT* IEM_WITHOUT_ASSEMBLY=1 */
+# define TODO_MXCSR_ORDER            /* (test harness issue, not IEM) */
+# undef  BS3_MXCSR_PE_FUZZY          /* most or all mentions of BS3_MXCSR_PE_FUZZY represent cases where */
+# define BS3_MXCSR_PE_FUZZY 0        /*    IEM behavior disagrees with hardware; they need investigation */
 #endif /* TODO_EXPOSE_IEM_ERRATA */
 
@@ -23462 +23459 @@
     {
         { BS3_INSTR4_ALL(cvtdq2pd_XMM1_XMM2),   255,             RM_REG,    T_SSE2,    XMM1, XMM2,  NOREG, 0, PASS_TEST_ARRAY(s_aValues) },
-#ifdef TODO_CVTDQ2PD_M64_IEM /** @todo THIS FAILS ON IEM: unexpected #GP */
         { BS3_INSTR4_ALL(cvtdq2pd_XMM1_FSxBX),  X86_XCPT_AC,     RM_MEM,    T_SSE2,    XMM1, FSxBX, NOREG, 0, PASS_TEST_ARRAY(s_aValues) },
-#endif /* TODO_CVTDQ2PD_M64_IEM */
 
         { BS3_INSTR4_ALL(vcvtdq2pd_XMM1_XMM2),  255,             RM_REG,    T_AVX_128, XMM1, XMM2,  NOREG, 0, PASS_TEST_ARRAY(s_aValues) },
@@ -23477 +23472 @@
 
         { BS3_INSTR4_C64(cvtdq2pd_XMM8_XMM9),   255,             RM_REG,    T_SSE2,    XMM8, XMM9,  NOREG, 0, PASS_TEST_ARRAY(s_aValues) },
-#ifdef TODO_CVTDQ2PD_M64_IEM /** @todo THIS FAILS ON IEM: unexpected #GP */
         { BS3_INSTR4_C64(cvtdq2pd_XMM8_FSxBX),  X86_XCPT_AC,     RM_MEM,    T_SSE2,    XMM8, FSxBX, NOREG, 0, PASS_TEST_ARRAY(s_aValues) },
-#endif /* TODO_CVTDQ2PD_M64_IEM */
 
         { BS3_INSTR4_C64(vcvtdq2pd_XMM8_XMM9),  255,             RM_REG,    T_AVX_128, XMM8, XMM9,  NOREG, 0, PASS_TEST_ARRAY(s_aValues) },
@@ -24873 +24866 @@
 # endif /* BS3_CPU_INSTR_4 */
 # if defined(BS3_CPU_INSTR_5)
-        { "[v]rcpps",       bs3CpuInstr4_v_rcpps,     0 },
+#  ifdef TODO_IEM_ASM_COREDUMP
+        { "[v]rcpps",       bs3CpuInstr4_v_rcpps,     0 },  // COREDUMP in asm-iem
+#  endif /* TODO_IEM_ASM_COREDUMP */
         { "[v]rcpss",       bs3CpuInstr4_v_rcpss,     0 },
-        { "[v]sqrtps",      bs3CpuInstr4_v_sqrtps,    0 },
-        { "[v]sqrtpd",      bs3CpuInstr4_v_sqrtpd,    0 },
+#  ifdef TODO_IEM_ASM_COREDUMP
+        { "[v]sqrtps",      bs3CpuInstr4_v_sqrtps,    0 },  // COREDUMP in asm-iem
+        { "[v]sqrtpd",      bs3CpuInstr4_v_sqrtpd,    0 },  // COREDUMP in asm-iem
+#  endif /* TODO_IEM_ASM_COREDUMP */
         { "[v]sqrtss",      bs3CpuInstr4_v_sqrtss,    0 },
         { "[v]sqrtsd",      bs3CpuInstr4_v_sqrtsd,    0 },
-        { "[v]rsqrtps",     bs3CpuInstr4_v_rsqrtps,   0 },
+#  ifdef TODO_IEM_ASM_COREDUMP
+        { "[v]rsqrtps",     bs3CpuInstr4_v_rsqrtps,   0 },  // COREDUMP in asm-iem
+#  endif /* TODO_IEM_ASM_COREDUMP */
         { "[v]rsqrtss",     bs3CpuInstr4_v_rsqrtss,   0 },
         { "[v]dpps",        bs3CpuInstr4_v_dpps,      0 },
@@ -24907 +24906 @@
         { "[v]cvtsd2si",    bs3CpuInstr4_v_cvtsd2si,  0 },
         { "[v]cvttsd2si",   bs3CpuInstr4_v_cvttsd2si, 0 },
-        { "[v]cvtdq2ps",    bs3CpuInstr4_v_cvtdq2ps,  0 },
-        { "[v]cvtps2dq",    bs3CpuInstr4_v_cvtps2dq,  0 },
-        { "[v]cvttps2dq",   bs3CpuInstr4_v_cvttps2dq, 0 },
+#  ifdef TODO_IEM_ASM_COREDUMP
+        { "[v]cvtdq2ps",    bs3CpuInstr4_v_cvtdq2ps,  0 },  // COREDUMP in asm-iem
+        { "[v]cvtps2dq",    bs3CpuInstr4_v_cvtps2dq,  0 },  // COREDUMP in asm-iem
+        { "[v]cvttps2dq",   bs3CpuInstr4_v_cvttps2dq, 0 },  // COREDUMP in asm-iem
+#  endif /* TODO_IEM_ASM_COREDUMP */
         { "[v]cvtdq2pd",    bs3CpuInstr4_v_cvtdq2pd,  0 },
         { "[v]cvtpd2dq",    bs3CpuInstr4_v_cvtpd2dq,  0 },