Index: trunk/include/VBox/vmm/cpum-armv8.h
===================================================================
--- trunk/include/VBox/vmm/cpum-armv8.h	(revision 107389)
+++ trunk/include/VBox/vmm/cpum-armv8.h	(revision 107650)
@@ -197,45 +197,4 @@
 
 
-/**
- * CPU ID registers.
- */
-typedef struct CPUMIDREGS
-{
-    /** Content of the ID_AA64PFR0_EL1 register. */
-    uint64_t        u64RegIdAa64Pfr0El1;
-    /** Content of the ID_AA64PFR1_EL1 register. */
-    uint64_t        u64RegIdAa64Pfr1El1;
-    /** Content of the ID_AA64DFR0_EL1 register. */
-    uint64_t        u64RegIdAa64Dfr0El1;
-    /** Content of the ID_AA64DFR1_EL1 register. */
-    uint64_t        u64RegIdAa64Dfr1El1;
-    /** Content of the ID_AA64AFR0_EL1 register. */
-    uint64_t        u64RegIdAa64Afr0El1;
-    /** Content of the ID_AA64AFR1_EL1 register. */
-    uint64_t        u64RegIdAa64Afr1El1;
-    /** Content of the ID_AA64ISAR0_EL1 register. */
-    uint64_t        u64RegIdAa64Isar0El1;
-    /** Content of the ID_AA64ISAR1_EL1 register. */
-    uint64_t        u64RegIdAa64Isar1El1;
-    /** Content of the ID_AA64ISAR2_EL1 register. */
-    uint64_t        u64RegIdAa64Isar2El1;
-    /** Content of the ID_AA64MMFR0_EL1 register. */
-    uint64_t        u64RegIdAa64Mmfr0El1;
-    /** Content of the ID_AA64MMFR1_EL1 register. */
-    uint64_t        u64RegIdAa64Mmfr1El1;
-    /** Content of the ID_AA64MMFR2_EL1 register. */
-    uint64_t        u64RegIdAa64Mmfr2El1;
-    /** Content of the CLIDR_EL1 register. */
-    uint64_t        u64RegClidrEl1;
-    /** Content of the CTR_EL0 register. */
-    uint64_t        u64RegCtrEl0;
-    /** Content of the DCZID_EL0 register. */
-    uint64_t        u64RegDczidEl0;
-} CPUMIDREGS;
-/** Pointer to CPU ID registers. */
-typedef CPUMIDREGS *PCPUMIDREGS;
-/** Pointer to a const CPU ID registers structure. */
-typedef CPUMIDREGS const *PCCPUMIDREGS;
-
 
 /** @name Changed flags.
@@ -280,7 +239,7 @@
 
 VMMR3DECL(int)          CPUMR3SysRegRangesInsert(PVM pVM, PCCPUMSYSREGRANGE pNewRange);
-VMMR3DECL(int)          CPUMR3PopulateFeaturesByIdRegisters(PVM pVM, PCCPUMIDREGS pIdRegs);
-
-VMMR3_INT_DECL(int)     CPUMR3QueryGuestIdRegs(PVM pVM, PCCPUMIDREGS *ppIdRegs);
+VMMR3DECL(int)          CPUMR3PopulateFeaturesByIdRegisters(PVM pVM, PCCPUMARMV8IDREGS pIdRegs);
+
+VMMR3_INT_DECL(int)     CPUMR3QueryGuestIdRegs(PVM pVM, PCCPUMARMV8IDREGS *ppIdRegs);
 
 /** @} */
Index: trunk/include/VBox/vmm/cpum-x86-amd64.h
===================================================================
--- trunk/include/VBox/vmm/cpum-x86-amd64.h	(revision 107389)
+++ trunk/include/VBox/vmm/cpum-x86-amd64.h	(revision 107650)
@@ -812,9 +812,4 @@
 #ifndef VBOX_FOR_DTRACE_LIB
 
-#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
-VMMDECL(int)            CPUMCpuIdCollectLeavesX86(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
-VMMDECL(CPUMCPUVENDOR)  CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
-#endif
-
 VMM_INT_DECL(bool)      CPUMAssertGuestRFlagsCookie(PVM pVM, PVMCPU pVCpu);
 
@@ -2329,5 +2324,4 @@
 /** @} */
 
-VMMDECL(bool)           CPUMSupportsXSave(PVM pVM);
 VMMDECL(bool)           CPUMIsHostUsingSysEnter(PVM pVM);
 VMMDECL(bool)           CPUMIsHostUsingSysCall(PVM pVM);
@@ -2388,5 +2382,4 @@
 VMMDECL(CPUMMICROARCH)      CPUMCpuIdDetermineX86MicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
                                                              uint8_t bModel, uint8_t bStepping);
-VMMDECL(const char *)       CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
 VMMR3DECL(int)              CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
 VMMR3DECL(const char *)     CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod);
Index: trunk/include/VBox/vmm/cpum.h
===================================================================
--- trunk/include/VBox/vmm/cpum.h	(revision 107389)
+++ trunk/include/VBox/vmm/cpum.h	(revision 107650)
@@ -354,12 +354,4 @@
 typedef struct CPUMFEATURESCOMMON
 {
-    /** The CPU vendor (CPUMCPUVENDOR). */
-    uint8_t         enmCpuVendor;
-    /** The CPU family. */
-    uint8_t         uFamily;
-    /** The CPU model. */
-    uint8_t         uModel;
-    /** The CPU stepping. */
-    uint8_t         uStepping;
     /** The microarchitecture. */
 #ifndef VBOX_FOR_DTRACE_LIB
@@ -368,4 +360,6 @@
     uint32_t        enmMicroarch;
 #endif
+    /** The CPU vendor (CPUMCPUVENDOR). */
+    uint8_t         enmCpuVendor;
     /** The maximum physical address width of the CPU. */
     uint8_t         cMaxPhysAddrWidth;
@@ -381,6 +375,17 @@
 typedef struct CPUMFEATURESX86
 {
+    /** The microarchitecture. */
+#ifndef VBOX_FOR_DTRACE_LIB
+    CPUMMICROARCH   enmMicroarch;
+#else
+    uint32_t        enmMicroarch;
+#endif
     /** The CPU vendor (CPUMCPUVENDOR). */
     uint8_t         enmCpuVendor;
+    /** The maximum physical address width of the CPU. */
+    uint8_t         cMaxPhysAddrWidth;
+    /** The maximum linear address width of the CPU. */
+    uint8_t         cMaxLinearAddrWidth;
+
     /** The CPU family. */
     uint8_t         uFamily;
@@ -389,14 +394,4 @@
     /** The CPU stepping. */
     uint8_t         uStepping;
-    /** The microarchitecture. */
-#ifndef VBOX_FOR_DTRACE_LIB
-    CPUMMICROARCH   enmMicroarch;
-#else
-    uint32_t        enmMicroarch;
-#endif
-    /** The maximum physical address width of the CPU. */
-    uint8_t         cMaxPhysAddrWidth;
-    /** The maximum linear address width of the CPU. */
-    uint8_t         cMaxLinearAddrWidth;
     /** Max size of the extended state (or FPU state if no XSAVE). */
     uint16_t        cbMaxExtendedState;
@@ -844,11 +839,9 @@
     /** VMX: Padding / reserved for future, making it a total of 128 bits.  */
     uint32_t        fVmxPadding1;
+    uint32_t        auPadding[4];
 } CPUMFEATURESX86;
 #ifndef VBOX_FOR_DTRACE_LIB
-AssertCompileSize(CPUMFEATURESX86, 48);
+AssertCompileSize(CPUMFEATURESX86, 64);
 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmCpuVendor,          CPUMFEATURESX86, enmCpuVendor);
-AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uFamily,               CPUMFEATURESX86, uFamily);
-AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uModel,                CPUMFEATURESX86, uModel);
-AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uStepping,             CPUMFEATURESX86, uStepping);
 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmMicroarch,          CPUMFEATURESX86, enmMicroarch);
 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxPhysAddrWidth,     CPUMFEATURESX86, cMaxPhysAddrWidth);
@@ -863,12 +856,4 @@
 typedef struct CPUMFEATURESARMV8
 {
-    /** The CPU vendor (CPUMCPUVENDOR). */
-    uint8_t         enmCpuVendor;
-    /** The CPU family. */
-    uint8_t         uFamily;
-    /** The CPU model. */
-    uint8_t         uModel;
-    /** The CPU stepping. */
-    uint8_t         uStepping;
     /** The microarchitecture. */
 #ifndef VBOX_FOR_DTRACE_LIB
@@ -877,9 +862,19 @@
     uint32_t        enmMicroarch;
 #endif
+    /** The CPU vendor (CPUMCPUVENDOR). */
+    uint8_t         enmCpuVendor;
     /** The maximum physical address width of the CPU. */
     uint8_t         cMaxPhysAddrWidth;
     /** The maximum linear address width of the CPU. */
     uint8_t         cMaxLinearAddrWidth;
-    uint16_t        uPadding;
+
+    /** The CPU implementer value (from MIDR_EL1). */
+    uint8_t         uImplementeter;
+    /** The CPU part number (from MIDR_EL1). */
+    uint16_t        uPartNum;
+    /** The CPU variant (from MIDR_EL1). */
+    uint8_t         uVariant;
+    /** The CPU revision (from MIDR_EL1). */
+    uint8_t         uRevision;
 
     /** @name Granule sizes supported.
@@ -1395,14 +1390,11 @@
     /** @} */
 
-    /** Padding to the required size to match CPUMFEATURES for x86/amd64. */
-    uint8_t         abPadding[4];
+    /** Padding to the required size to match CPUMFEATURESX86. */
+    uint32_t        auPadding[5];
 } CPUMFEATURESARMV8;
 #ifndef VBOX_FOR_DTRACE_LIB
-AssertCompileSize(CPUMFEATURESARMV8, 48);
+AssertCompileSize(CPUMFEATURESARMV8, 64);
+AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmMicroarch,          CPUMFEATURESARMV8, enmMicroarch);
 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmCpuVendor,          CPUMFEATURESARMV8, enmCpuVendor);
-AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uFamily,               CPUMFEATURESARMV8, uFamily);
-AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uModel,                CPUMFEATURESARMV8, uModel);
-AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, uStepping,             CPUMFEATURESARMV8, uStepping);
-AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, enmMicroarch,          CPUMFEATURESARMV8, enmMicroarch);
 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxPhysAddrWidth,     CPUMFEATURESARMV8, cMaxPhysAddrWidth);
 AssertCompileMembersAtSameOffset(CPUMFEATURESCOMMON, cMaxLinearAddrWidth,   CPUMFEATURESARMV8, cMaxLinearAddrWidth);
@@ -1436,4 +1428,7 @@
                     s;
 } CPUHOSTFEATURES;
+#ifndef VBOX_FOR_DTRACE_LIB
+AssertCompileSize(CPUHOSTFEATURES, 64);
+#endif
 /** Pointer to a const host CPU feature structure. */
 typedef CPUHOSTFEATURES const *PCCPUHOSTFEATURES;
@@ -1458,4 +1453,48 @@
 
 
+
+/**
+ * ARMv8 CPU ID registers.
+ */
+typedef struct CPUMARMV8IDREGS
+{
+    /** Content of the ID_AA64PFR0_EL1 register. */
+    uint64_t        u64RegIdAa64Pfr0El1;
+    /** Content of the ID_AA64PFR1_EL1 register. */
+    uint64_t        u64RegIdAa64Pfr1El1;
+    /** Content of the ID_AA64DFR0_EL1 register. */
+    uint64_t        u64RegIdAa64Dfr0El1;
+    /** Content of the ID_AA64DFR1_EL1 register. */
+    uint64_t        u64RegIdAa64Dfr1El1;
+    /** Content of the ID_AA64AFR0_EL1 register. */
+    uint64_t        u64RegIdAa64Afr0El1;
+    /** Content of the ID_AA64AFR1_EL1 register. */
+    uint64_t        u64RegIdAa64Afr1El1;
+    /** Content of the ID_AA64ISAR0_EL1 register. */
+    uint64_t        u64RegIdAa64Isar0El1;
+    /** Content of the ID_AA64ISAR1_EL1 register. */
+    uint64_t        u64RegIdAa64Isar1El1;
+    /** Content of the ID_AA64ISAR2_EL1 register. */
+    uint64_t        u64RegIdAa64Isar2El1;
+    /** Content of the ID_AA64MMFR0_EL1 register. */
+    uint64_t        u64RegIdAa64Mmfr0El1;
+    /** Content of the ID_AA64MMFR1_EL1 register. */
+    uint64_t        u64RegIdAa64Mmfr1El1;
+    /** Content of the ID_AA64MMFR2_EL1 register. */
+    uint64_t        u64RegIdAa64Mmfr2El1;
+    /** Content of the CLIDR_EL1 register. */
+    uint64_t        u64RegClidrEl1;
+    /** Content of the CTR_EL0 register. */
+    uint64_t        u64RegCtrEl0;
+    /** Content of the DCZID_EL0 register. */
+    uint64_t        u64RegDczidEl0;
+    /** @todo we need MIDR_EL1 here, possibly also MPIDR_EL1 and REVIDR_EL1. */
+} CPUMARMV8IDREGS;
+/** Pointer to CPU ID registers. */
+typedef CPUMARMV8IDREGS *PCPUMARMV8IDREGS;
+/** Pointer to a const CPU ID registers structure. */
+typedef CPUMARMV8IDREGS const *PCCPUMARMV8IDREGS;
+
+
 /*
  * Include the target specific header.
@@ -1499,4 +1538,15 @@
 VMMDECL(CPUMMICROARCH)  CPUMGetHostMicroarch(PCVM pVM);
 
+VMMDECL(const char *)   CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
+VMMDECL(const char *)   CPUMCpuVendorName(CPUMCPUVENDOR enmVendor);
+
+VMMDECL(CPUMCPUVENDOR)  CPUMCpuIdDetectX86VendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
+#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
+VMMDECL(int)            CPUMCpuIdCollectLeavesFromX86Host(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
+#endif
+#if defined(RT_ARCH_ARM64)
+VMMDECL(int)            CPUMCpuIdCollectIdRegistersFromArmV8Host(PCPUMARMV8IDREGS pIdRegs);
+#endif
+
 #ifdef IN_RING3
 /** @defgroup grp_cpum_r3    The CPUM ring-3 API
@@ -1512,6 +1562,4 @@
 VMMR3DECL(void)         CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
 VMMDECL(bool)           CPUMR3IsStateRestorePending(PVM pVM);
-VMMDECL(const char *)       CPUMMicroarchName(CPUMMICROARCH enmMicroarch);
-VMMR3DECL(const char *)     CPUMCpuVendorName(CPUMCPUVENDOR enmVendor);
 
 VMMR3DECL(uint32_t)         CPUMR3DbGetEntries(void);
Index: trunk/include/VBox/vmm/vm.h
===================================================================
--- trunk/include/VBox/vmm/vm.h	(revision 107389)
+++ trunk/include/VBox/vmm/vm.h	(revision 107650)
@@ -1360,6 +1360,4 @@
         struct
         {
-            /** Padding for hidden fields. */
-            uint8_t                 abHidden0[64 + 48];
             /** Guest CPU feature information. */
             CPUMFEATURES            GuestFeatures;
