Changeset 107650 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Jan 10, 2025 1:42:28 PM (4 months ago)
- svn:sync-xref-src-repo-rev:
- 166740
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 3 edited
-
CPUMAllCpuId.cpp (modified) (15 diffs)
-
CPUMAllRegs-armv8.cpp (modified) (3 diffs)
-
CPUMAllRegs.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp
r106061 r107650 46 46 #include <iprt/string.h> 47 47 #include <iprt/x86-helpers.h> 48 #if defined(RT_ARCH_ARM64) || defined(VBOX_VMM_TARGET_ARMV8) 49 # include <iprt/armv8.h> 50 #endif 48 51 49 52 … … 51 54 * Global Variables * 52 55 *********************************************************************************************************************************/ 56 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86) 53 57 /** 54 58 * The intel pentium family. … … 505 509 } 506 510 511 #endif /* if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86) */ 512 513 507 514 508 515 /** … … 685 692 } 686 693 694 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86) 687 695 688 696 /** … … 750 758 else 751 759 { 752 # ifdef IN_VBOX_CPU_REPORT760 # ifdef IN_VBOX_CPU_REPORT 753 761 AssertReleaseFailed(); 754 # else755 # ifdef IN_RING3762 # else 763 # ifdef IN_RING3 756 764 Assert(ppaLeaves == &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3); 757 765 Assert(*ppaLeaves == pVM->cpum.s.GuestInfo.aCpuIdLeaves); … … 761 769 { } 762 770 else 763 # endif771 # endif 764 772 { 765 773 *ppaLeaves = NULL; 766 774 LogRel(("CPUM: cpumR3CpuIdEnsureSpace: Out of CPUID space!\n")); 767 775 } 768 # endif776 # endif 769 777 } 770 778 return *ppaLeaves; … … 772 780 773 781 774 # ifdef VBOX_STRICT782 # ifdef VBOX_STRICT 775 783 /** 776 784 * Checks that we've updated the CPUID leaves array correctly. … … 796 804 } 797 805 } 798 #endif 806 # endif 807 808 #endif /* defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86) */ 799 809 800 810 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) … … 982 992 * success. 983 993 */ 984 VMMDECL(int) CPUMCpuIdCollectLeaves X86(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)994 VMMDECL(int) CPUMCpuIdCollectLeavesFromX86Host(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves) 985 995 { 986 996 *ppaLeaves = NULL; … … 1150 1160 return VINF_SUCCESS; 1151 1161 } 1162 1152 1163 #endif /* RT_ARCH_X86 || RT_ARCH_AMD64 */ 1153 1164 1154 1165 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86) 1155 1166 /** 1156 1167 * Detect the CPU vendor give n the … … 1193 1204 return CPUMCPUVENDOR_UNKNOWN; 1194 1205 } 1206 #endif /* defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86) */ 1195 1207 1196 1208 … … 1224 1236 } 1225 1237 1238 #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86) 1226 1239 1227 1240 static PCCPUMCPUIDLEAF cpumCpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf) … … 1260 1273 1261 1274 1262 static void cpumExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, PCPUMFEATURESpFeatures)1275 static void cpumExplodeVmxFeatures(PCVMXMSRS pVmxMsrs, CPUMFEATURESX86 *pFeatures) 1263 1276 { 1264 1277 Assert(pVmxMsrs); … … 1390 1403 1391 1404 1392 int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURESpFeatures)1405 int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, CPUMFEATURESX86 *pFeatures) 1393 1406 { 1394 1407 Assert(pMsrs); … … 1631 1644 } 1632 1645 1646 #endif /* defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86) */ 1647 1648 #if defined(RT_ARCH_ARM64) 1649 /** 1650 * Collects the ID registers from an ARMv8 host. 1651 * 1652 * This isn't trivial an all hosts when running in userland and there is no 1653 * support driver handy. 1654 */ 1655 VMMDECL(int) CPUMCpuIdCollectIdRegistersFromArmV8Host(PCPUMARMV8IDREGS pIdRegs) 1656 { 1657 # ifdef _MSC_VER 1658 # define READ_SYS_REG(a_u64Dst, a_SysRegName) do { \ 1659 (a_u64Dst) = (uint64_t)_ReadStatusReg(RT_CONCAT(ARMV8_AARCH64_SYSREG_,a_SysRegName) & 0x7fff); \ 1660 } while (0) 1661 # else 1662 # define READ_SYS_REG(a_u64Dst, a_SysRegName) do { \ 1663 __asm__ __volatile__ ("mrs %0, " #a_SysRegName : "=r" (a_u64Dst)); \ 1664 } while (0) 1665 # endif 1666 1667 RT_ZERO(*pIdRegs); 1668 1669 /* 1670 * CTR_EL0 can be trapped when executed in L0 (SCTLR_EL0.UCT) and macOS 1671 * & Windows does so by default. Linux OTOH typically exposes all the 1672 * feature registers to user land with some sanitizing. 1673 */ 1674 # if !defined(IN_RING3) || defined(RT_OS_LINUX) 1675 READ_SYS_REG(pIdRegs->u64RegCtrEl0, CTR_EL0); 1676 # endif 1677 READ_SYS_REG(pIdRegs->u64RegDczidEl0, DCZID_EL0); 1678 1679 # if defined(IN_RING0) || defined(RT_OS_LINUX) 1680 # ifdef IN_RING3 1681 if (getauxval(AT_HWCAP) & HWCAP_CPUID) 1682 # endif 1683 { 1684 READ_SYS_REG(pIdRegs->u64RegIdAa64Pfr0El1, ID_AA64PFR0_EL1); 1685 READ_SYS_REG(pIdRegs->u64RegIdAa64Pfr1El1, ID_AA64PFR1_EL1); 1686 READ_SYS_REG(pIdRegs->u64RegIdAa64Dfr0El1, ID_AA64DFR0_EL1); 1687 READ_SYS_REG(pIdRegs->u64RegIdAa64Dfr1El1, ID_AA64DFR1_EL1); 1688 /// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Dfr2El1, ID_AA64DFR2_EL1); 1689 READ_SYS_REG(pIdRegs->u64RegIdAa64Afr0El1, ID_AA64AFR0_EL1); 1690 READ_SYS_REG(pIdRegs->u64RegIdAa64Afr1El1, ID_AA64AFR1_EL1); 1691 READ_SYS_REG(pIdRegs->u64RegIdAa64Isar0El1, ID_AA64ISAR0_EL1); 1692 READ_SYS_REG(pIdRegs->u64RegIdAa64Isar1El1, ID_AA64ISAR1_EL1); 1693 READ_SYS_REG(pIdRegs->u64RegIdAa64Isar2El1, ID_AA64ISAR2_EL1); 1694 /// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Isar3El1, ID_AA64ISAR3_EL1); 1695 READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr0El1, ID_AA64MMFR0_EL1); 1696 READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr1El1, ID_AA64MMFR1_EL1); 1697 READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr2El1, ID_AA64MMFR2_EL1); 1698 /// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr3El1, ID_AA64MMFR3_EL1); 1699 /// @todo READ_SYS_REG(pIdRegs->u64RegIdAa64Mmfr4El1, ID_AA64MMFR4_EL1); 1700 READ_SYS_REG(pIdRegs->u64RegClidrEl1, CLIDR_EL1); 1701 1702 /// @todo READ_SYS_REG(pIdRegs->uMainIdRegEl1, MIDR_EL1); 1703 /// @todo READ_SYS_REG(pIdRegs->uMpIdRegEl1, MPIDR_EL1); 1704 /// @todo READ_SYS_REG(pIdRegs->uRevIdRegEl1, REVIDR_EL1); 1705 return VINF_SUCCESS; 1706 } 1707 # endif 1708 # ifndef IN_RING0 1709 /** @todo On darwin we should just cache the information (CPU DB) and figure 1710 * out which Apple Mx we're running on. */ 1711 /** @todo Make the info available via the support driver... */ 1712 return VINF_SUCCESS; 1713 # endif 1714 } 1715 #endif /* defined(RT_ARCH_ARM64) */ 1716 1717 #if defined(RT_ARCH_ARM64) || defined(VBOX_VMM_TARGET_ARMV8) 1718 /** 1719 * Explode the CPU features from the given ID registers. 1720 * 1721 * @returns VBox status code. 1722 * @param pIdRegs The ID registers to explode the features from. 1723 * @param pFeatures Where to store the features to. 1724 */ 1725 int cpumCpuIdExplodeFeaturesArmV8(PCCPUMARMV8IDREGS pIdRegs, CPUMFEATURESARMV8 *pFeatures) 1726 { 1727 uint64_t u64IdReg = pIdRegs->u64RegIdAa64Mmfr0El1; 1728 1729 static uint8_t s_aPaRange[] = { 32, 36, 40, 42, 44, 48, 52 }; 1730 AssertLogRelMsgReturn(RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE) < RT_ELEMENTS(s_aPaRange), 1731 ("CPUM: Invalid/Unsupported PARange value in ID_AA64MMFR0_EL1 register: %u\n", 1732 RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE)), 1733 VERR_CPUM_IPE_1); 1734 1735 pFeatures->cMaxPhysAddrWidth = s_aPaRange[RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_PARANGE)]; 1736 pFeatures->fTGran4K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN4) != ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL; 1737 pFeatures->fTGran16K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN16) != ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL; 1738 pFeatures->fTGran64K = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_TGRAN64) != ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL; 1739 1740 /* ID_AA64ISAR0_EL1 features. */ 1741 u64IdReg = pIdRegs->u64RegIdAa64Isar0El1; 1742 pFeatures->fAes = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES) >= ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED; 1743 pFeatures->fPmull = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_AES) >= ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL; 1744 pFeatures->fSha1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA1) >= ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED; 1745 pFeatures->fSha256 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2) >= ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256; 1746 pFeatures->fSha512 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA2) >= ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512; 1747 pFeatures->fCrc32 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_CRC32) >= ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED; 1748 pFeatures->fLse = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_ATOMIC) >= ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED; 1749 pFeatures->fTme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TME) >= ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED; 1750 pFeatures->fRdm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_RDM) >= ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED; 1751 pFeatures->fSha3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SHA3) >= ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED; 1752 pFeatures->fSm3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SM3) >= ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED; 1753 pFeatures->fSm4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_SM4) >= ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED; 1754 pFeatures->fDotProd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_DP) >= ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED; 1755 pFeatures->fFhm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_FHM) >= ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED; 1756 pFeatures->fFlagM = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TS) >= ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED; 1757 pFeatures->fFlagM2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TS) >= ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2; 1758 pFeatures->fTlbios = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TLB) >= ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED; 1759 pFeatures->fTlbirange = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_TLB) >= ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE; 1760 pFeatures->fRng = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR0_EL1_RNDR) >= ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED; 1761 1762 /* ID_AA64ISAR1_EL1 features. */ 1763 u64IdReg = pIdRegs->u64RegIdAa64Isar1El1; 1764 pFeatures->fDpb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DPB) >= ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED; 1765 pFeatures->fDpb2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DPB) >= ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2; 1766 1767 /* PAuth using QARMA5. */ 1768 pFeatures->fPacQarma5 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) != ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL; 1769 if (pFeatures->fPacQarma5) 1770 { 1771 pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH; 1772 pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC; 1773 pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2; 1774 pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC; 1775 pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_APA) >= ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE; 1776 } 1777 1778 /* PAuth using implementation defined algorithm. */ 1779 pFeatures->fPacImp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) != ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL; 1780 if (pFeatures->fPacQarma5) 1781 { 1782 pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH; 1783 pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC; 1784 pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2; 1785 pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC; 1786 pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_API) >= ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE; 1787 } 1788 1789 pFeatures->fJscvt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FJCVTZS) >= ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED; 1790 pFeatures->fFcma = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FCMA) >= ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED; 1791 pFeatures->fLrcpc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LRCPC) >= ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED; 1792 pFeatures->fLrcpc2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LRCPC) >= ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2; 1793 pFeatures->fFrintts = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_FRINTTS) >= ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED; 1794 pFeatures->fSb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_SB) >= ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED; 1795 pFeatures->fSpecres = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_SPECRES) >= ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED; 1796 pFeatures->fBf16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_BF16) >= ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16; 1797 pFeatures->fEbf16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_BF16) >= ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16; 1798 pFeatures->fDgh = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_DGH) >= ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED; 1799 pFeatures->fI8mm = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_I8MM) >= ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED; 1800 pFeatures->fXs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_XS) >= ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED; 1801 pFeatures->fLs64 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED; 1802 pFeatures->fLs64V = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V; 1803 pFeatures->fLs64Accdata = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR1_EL1_LS64) >= ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA; 1804 1805 /* ID_AA64ISAR2_EL1 features. */ 1806 u64IdReg = pIdRegs->u64RegIdAa64Isar2El1; 1807 pFeatures->fWfxt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_WFXT) >= ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED; 1808 pFeatures->fRpres = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_RPRES) >= ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED; 1809 1810 /* PAuth using QARMA3. */ 1811 pFeatures->fPacQarma3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_GPA3) >= ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED; 1812 pFeatures->fPacQarma3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) != ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL; 1813 if (pFeatures->fPacQarma5) 1814 { 1815 pFeatures->fPAuth = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH; 1816 pFeatures->fEpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC; 1817 pFeatures->fPAuth2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2; 1818 pFeatures->fFpac = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC; 1819 pFeatures->fFpacCombine = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_APA3) >= ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE; 1820 } 1821 1822 pFeatures->fMops = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_MOPS) >= ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED; 1823 pFeatures->fHbc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_BC) >= ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED; 1824 pFeatures->fConstPacField = RT_BF_GET(u64IdReg, ARMV8_ID_AA64ISAR2_EL1_PACFRAC) >= ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE; 1825 1826 /* ID_AA64PFR0_EL1 */ 1827 u64IdReg = pIdRegs->u64RegIdAa64Pfr0El1; 1828 /* The FP and AdvSIMD field must have the same value. */ 1829 Assert(RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) == RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD)); 1830 pFeatures->fFp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) != ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL; 1831 pFeatures->fFp16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_FP) == ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP; 1832 pFeatures->fAdvSimd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD) != ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL; 1833 pFeatures->fFp16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_ADVSIMD) == ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP; 1834 pFeatures->fRas = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RAS) >= ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED; 1835 pFeatures->fRasV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RAS) >= ARMV8_ID_AA64PFR0_EL1_RAS_V1P1; 1836 pFeatures->fSve = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_SVE) >= ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED; 1837 pFeatures->fSecEl2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_SEL2) >= ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED; 1838 pFeatures->fAmuV1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_AMU) >= ARMV8_ID_AA64PFR0_EL1_AMU_V1; 1839 pFeatures->fAmuV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_AMU) >= ARMV8_ID_AA64PFR0_EL1_AMU_V1P1; 1840 pFeatures->fDit = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_DIT) >= ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED; 1841 pFeatures->fRme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_RME) >= ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED; 1842 pFeatures->fCsv2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_CSV2) >= ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED; 1843 pFeatures->fCsv2v3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR0_EL1_CSV2) >= ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED; 1844 1845 /* ID_AA64PFR1_EL1 */ 1846 u64IdReg = pIdRegs->u64RegIdAa64Pfr1El1; 1847 pFeatures->fBti = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_BT) >= ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED; 1848 pFeatures->fSsbs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SSBS) >= ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED; 1849 pFeatures->fSsbs2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SSBS) >= ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS; 1850 pFeatures->fMte = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY; 1851 pFeatures->fMte2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_FULL; 1852 pFeatures->fMte3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_MTE) >= ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK; 1853 /** @todo RAS_frac, MPAM_frac, CSV2_frac. */ 1854 pFeatures->fSme = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SME) >= ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED; 1855 pFeatures->fSme2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_SME) >= ARMV8_ID_AA64PFR1_EL1_SME_SME2; 1856 pFeatures->fRngTrap = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_RNDRTRAP) >= ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED; 1857 pFeatures->fNmi = RT_BF_GET(u64IdReg, ARMV8_ID_AA64PFR1_EL1_NMI) >= ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED; 1858 1859 /* ID_AA64MMFR0_EL1 */ 1860 u64IdReg = pIdRegs->u64RegIdAa64Mmfr0El1; 1861 pFeatures->fExs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_EXS) >= ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED; 1862 pFeatures->fFgt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_FGT) >= ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED; 1863 pFeatures->fEcv = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR0_EL1_ECV) >= ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED; 1864 1865 /* ID_AA64MMFR1_EL1 */ 1866 u64IdReg = pIdRegs->u64RegIdAa64Mmfr1El1; 1867 pFeatures->fHafdbs = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HAFDBS) >= ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED; 1868 pFeatures->fVmid16 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_VMIDBITS) >= ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16; 1869 pFeatures->fVhe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_VHE) >= ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED; 1870 pFeatures->fHpds = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HPDS) >= ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED; 1871 pFeatures->fHpds2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HPDS) >= ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2; 1872 pFeatures->fLor = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_LO) >= ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED; 1873 pFeatures->fPan = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED; 1874 pFeatures->fPan2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2; 1875 pFeatures->fPan3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_PAN) >= ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3; 1876 pFeatures->fXnx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_XNX) >= ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED; 1877 pFeatures->fTwed = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_TWED) >= ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED; 1878 pFeatures->fEts2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_ETS) >= ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED; 1879 pFeatures->fHcx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_HCX) >= ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED; 1880 pFeatures->fAfp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_AFP) >= ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED; 1881 pFeatures->fNTlbpa = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_NTLBPA) >= ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY; 1882 pFeatures->fTidcp1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_TIDCP1) >= ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED; 1883 pFeatures->fCmow = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR1_EL1_CMOW) >= ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED; 1884 1885 /* ID_AA64MMFR2_EL1 */ 1886 u64IdReg = pIdRegs->u64RegIdAa64Mmfr2El1; 1887 pFeatures->fTtcnp = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_CNP) >= ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED; 1888 pFeatures->fUao = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_UAO) >= ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED; 1889 pFeatures->fLsmaoc = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_LSM) >= ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED; 1890 pFeatures->fIesb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_IESB) >= ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED; 1891 pFeatures->fLva = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_VARANGE) >= ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN; 1892 pFeatures->fCcidx = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_CCIDX) >= ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT; 1893 pFeatures->fNv = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_NV) >= ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED; 1894 pFeatures->fNv2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_NV) >= ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2; 1895 pFeatures->fTtst = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_ST) >= ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED; 1896 pFeatures->fLse2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_AT) >= ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED; 1897 pFeatures->fIdst = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_IDS) >= ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H; 1898 pFeatures->fS2Fwb = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_FWB) >= ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED; 1899 pFeatures->fTtl = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_TTL) >= ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED; 1900 pFeatures->fEvt = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_EVT) >= ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED; 1901 pFeatures->fE0Pd = RT_BF_GET(u64IdReg, ARMV8_ID_AA64MMFR2_EL1_E0PD) >= ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED; 1902 1903 /* ID_AA64DFR0_EL1 */ 1904 u64IdReg = pIdRegs->u64RegIdAa64Dfr0El1; 1905 pFeatures->fDebugV8p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE; 1906 pFeatures->fDebugV8p2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2; 1907 pFeatures->fDebugV8p4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4; 1908 pFeatures->fDebugV8p8 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DEBUGVER) >= ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8; 1909 pFeatures->fPmuV3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3; 1910 pFeatures->fPmuV3p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1; 1911 pFeatures->fPmuV3p4 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4; 1912 pFeatures->fPmuV3p5 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5; 1913 pFeatures->fPmuV3p7 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7; 1914 pFeatures->fPmuV3p8 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMUVER) >= ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8; 1915 pFeatures->fSpe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED; 1916 pFeatures->fSpeV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1; 1917 pFeatures->fSpeV1p2 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2; 1918 pFeatures->fSpeV1p3 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_PMSVER) >= ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3; 1919 pFeatures->fDoubleLock = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK) == ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED; 1920 pFeatures->fTrf = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_TRACEFILT) >= ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED; 1921 pFeatures->fTrbe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER) >= ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED; 1922 pFeatures->fMtPmu = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_MTPMU) == ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED; 1923 pFeatures->fBrbe = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_BRBE) >= ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED; 1924 pFeatures->fBrbeV1p1 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_BRBE) >= ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1; 1925 pFeatures->fHpmn0 = RT_BF_GET(u64IdReg, ARMV8_ID_AA64DFR0_EL1_HPMN0) >= ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED; 1926 1927 return VINF_SUCCESS; 1928 } 1929 #endif /* defined(RT_ARCH_ARM64) || defined(VBOX_VMM_TARGET_ARMV8) */ 1930 -
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs-armv8.cpp
r107113 r107650 268 268 } 269 269 270 #if 0 /* unused atm */ 270 271 271 272 /** … … 306 307 } 307 308 309 #endif 308 310 309 311 /** … … 491 493 } 492 494 493 494 /**495 * Translates a microarchitecture enum value to the corresponding string496 * constant.497 *498 * @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns499 * NULL if the value is invalid.500 *501 * @param enmMicroarch The enum value to convert.502 *503 * @todo Doesn't really belong here but for now there is no other Armv8 CPUM source file.504 */505 VMMDECL(const char *) CPUMMicroarchName(CPUMMICROARCH enmMicroarch)506 {507 switch (enmMicroarch)508 {509 #define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)510 CASE_RET_STR(kCpumMicroarch_Apple_M1);511 #undef CASE_RET_STR512 default:513 break;514 }515 516 return NULL;517 } -
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
r107113 r107650 1075 1075 VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM) 1076 1076 { 1077 return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures. enmCpuVendor;1077 return (CPUMCPUVENDOR)pVM->cpum.s.HostFeatures.Common.enmCpuVendor; 1078 1078 } 1079 1079 … … 1087 1087 VMMDECL(CPUMMICROARCH) CPUMGetHostMicroarch(PCVM pVM) 1088 1088 { 1089 return pVM->cpum.s.HostFeatures. enmMicroarch;1089 return pVM->cpum.s.HostFeatures.Common.enmMicroarch; 1090 1090 } 1091 1091 … … 1631 1631 { 1632 1632 pVCpu->cpum.s.fChanged |= fChangedAdd; 1633 }1634 1635 1636 /**1637 * Checks if the CPU supports the XSAVE and XRSTOR instruction.1638 *1639 * @returns true if supported.1640 * @returns false if not supported.1641 * @param pVM The cross context VM structure.1642 */1643 VMMDECL(bool) CPUMSupportsXSave(PVM pVM)1644 {1645 return pVM->cpum.s.HostFeatures.fXSaveRstor != 0;1646 1633 } 1647 1634
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