Changeset 107749 in vbox
- Timestamp:
- Jan 14, 2025 10:28:53 AM (2 months ago)
- svn:sync-xref-src-repo-rev:
- 166860
- Location:
- trunk
- Files:
-
- 3 edited
-
include/VBox/vmm/cpum.h (modified) (2 diffs)
-
src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp (modified) (1 diff)
-
src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp (modified) (8 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/cpum.h
r107729 r107749 470 470 /** Supports IA32_SPEC_CTRL.STIBP. */ 471 471 uint32_t fStibp : 1; 472 /** Supports IA32_SPEC_CTRL.SSBD. */ 473 uint32_t fSsbd : 1; 474 /** Supports IA32_SPEC_CTRL.PSFD. */ 475 uint32_t fPsfd : 1; 476 /** Supports IA32_SPEC_CTRL.IPRED_DIS_U/S. */ 477 uint32_t fIpredCtrl : 1; 478 /** Supports IA32_SPEC_CTRL.RRSBA_DIS_U/S. */ 479 uint32_t fRrsbaCtrl : 1; 480 /** Supports IA32_SPEC_CTRL.DDPD_DIS_U. */ 481 uint32_t fDdpdU : 1; 482 /** Supports IA32_SPEC_CTRL.BHI_S. */ 483 uint32_t fBhiCtrl : 1; 472 484 /** Supports IA32_FLUSH_CMD. */ 473 485 uint32_t fFlushCmd : 1; 474 486 /** Supports IA32_ARCH_CAP. */ 475 487 uint32_t fArchCap : 1; 488 /** Supports IA32_CORE_CAP. */ 489 uint32_t fCoreCap : 1; 476 490 /** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */ 477 491 uint32_t fMdsClear : 1; 492 /** Whether susceptible to MXCSR configuration dependent timing (MCDT) behaviour. */ 493 uint32_t fMcdtNo : 1; 494 /** Whether susceptible MONITOR/UMONITOR internal table capacity issues. */ 495 uint32_t fMonitorMitgNo : 1; 496 /** Supports the UC-lock disable feature. */ 497 uint32_t fUcLockDis : 1; 478 498 /** Supports PCID. */ 479 499 uint32_t fPcid : 1; … … 620 640 621 641 /** Alignment padding / reserved for future use. */ 622 uint32_t fPadding0 : 28;642 uint32_t fPadding0 : 18; 623 643 uint32_t auPadding[3]; 624 644 -
trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp
r107731 r107749 1505 1505 pFeatures->fIbrs = pFeatures->fIbpb; 1506 1506 pFeatures->fStibp = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP); 1507 pFeatures->fSsbd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_SSBD); 1507 1508 pFeatures->fFlushCmd = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD); 1508 1509 pFeatures->fArchCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP); 1510 pFeatures->fCoreCap = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_CORECAP); 1509 1511 pFeatures->fMdsClear = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR); 1512 } 1513 PCCPUMCPUIDLEAF const pSxfLeaf2 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 7, 2); 1514 if (pSxfLeaf2) 1515 { 1516 pFeatures->fPsfd = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_PSFD); 1517 pFeatures->fIpredCtrl = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL); 1518 pFeatures->fRrsbaCtrl = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL); 1519 pFeatures->fDdpdU = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U); 1520 pFeatures->fBhiCtrl = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL); 1521 pFeatures->fMcdtNo = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO); 1522 pFeatures->fUcLockDis = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_UC_LOCK_DIS); 1523 pFeatures->fMonitorMitgNo = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO); 1510 1524 } 1511 1525 -
trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
r107731 r107749 1066 1066 CPUMISAEXTCFG enmFma; 1067 1067 CPUMISAEXTCFG enmF16c; 1068 CPUMISAEXTCFG enmMcdtNo; 1069 CPUMISAEXTCFG enmMonitorMitgNo; 1068 1070 1069 1071 CPUMISAEXTCFG enmAbm; … … 1860 1862 case 0: 1861 1863 { 1862 pCurLeaf->uEax = 0; /* Max ECX input is 0. */1864 pCurLeaf->uEax = RT_MIN(pCurLeaf->uEax, 2); /* Max ECX input is 2. */ 1863 1865 pCurLeaf->uEbx &= 0 1864 1866 | PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE) … … 1899 1901 ; 1900 1902 pCurLeaf->uEdx &= 0 1903 //| X86_CPUID_STEXT_FEATURE_EDX_SRBDS_CTRL RT_BIT(9) 1901 1904 | PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR) 1905 //| X86_CPUID_STEXT_FEATURE_EDX_TSX_FORCE_ABORT RT_BIT_32(11) 1906 //| X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT(20) 1902 1907 //| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26) 1903 1908 //| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27) 1904 1909 | PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD) 1905 1910 | PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP) 1911 //| X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30) 1912 //| X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31) 1906 1913 ; 1907 1914 … … 1962 1969 if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS) 1963 1970 pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP; 1971 break; 1972 } 1973 1974 case 2: 1975 { 1976 pCurLeaf->uEax = 0; 1977 pCurLeaf->uEbx = 0; 1978 pCurLeaf->uEcx = 0; 1979 pCurLeaf->uEdx &= 0 1980 //| X86_CPUID_STEXT_FEATURE_2_EDX_PSFD RT_BIT_32(0) 1981 //| X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL RT_BIT_32(1) 1982 //| X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL RT_BIT_32(2) 1983 //| X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U RT_BIT_32(3) 1984 //| X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL RT_BIT_32(4) 1985 | PASSTHRU_FEATURE(pConfig->enmMcdtNo, pHstFeat->fMcdtNo, X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO) 1986 //| X86_CPUID_STEXT_FEATURE_2_EDX_UC_LOCK_DIS RT_BIT_32(6) 1987 //| Bit 7 - MONITOR_MITG_NO - No need for MONITOR/UMONITOR power mitigrations. */ 1988 | PASSTHRU_FEATURE(pConfig->enmMonitorMitgNo, pHstFeat->fMonitorMitgNo, X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO) 1989 ; 1990 1991 /* Force standard feature bits. */ 1992 if (pConfig->enmMcdtNo == CPUMISAEXTCFG_ENABLED_ALWAYS) 1993 pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO; 1994 if (pConfig->enmMonitorMitgNo == CPUMISAEXTCFG_ENABLED_ALWAYS) 1995 pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO; 1964 1996 break; 1965 1997 } … … 2864 2896 "|FMA" 2865 2897 "|F16C" 2898 "|McdtNo" 2899 "|MonitorMitgNo" 2866 2900 "|ABM" 2867 2901 "|SSE4A" … … 3071 3105 rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "F16C", &pConfig->enmF16c, fNestedPagingAndFullGuestExec /* temporarily */, 3072 3106 fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /*fAllowed*/); 3107 AssertLogRelRCReturn(rc, rc); 3108 3109 /** @cfgm{/CPUM/IsaExts/McdtNo, isaextcfg, true} 3110 * Whether the CPU is not susceptible to the MXCSR configuration dependent 3111 * timing (MCDT) behaviour. 3112 */ 3113 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "McdtNo", &pConfig->enmMcdtNo, CPUMISAEXTCFG_ENABLED_SUPPORTED); 3114 AssertLogRelRCReturn(rc, rc); 3115 3116 /** @cfgm{/CPUM/IsaExts/MonitorMitgNo, isaextcfg, true} 3117 * Whether the CPU is not susceptible MONITOR/UMONITOR internal table capacity 3118 * issues. 3119 */ 3120 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MonitorMitgNo", &pConfig->enmMonitorMitgNo, CPUMISAEXTCFG_ENABLED_SUPPORTED); 3073 3121 AssertLogRelRCReturn(rc, rc); 3074 3122 … … 3934 3982 #endif 3935 3983 { 3984 /** @todo make this more configurable? */ 3936 3985 pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB; 3937 3986 pVM->cpum.s.GuestFeatures.fIbrs = 1; … … 3942 3991 pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_STIBP; 3943 3992 pVM->cpum.s.GuestFeatures.fStibp = 1; 3993 } 3994 3995 #ifdef RT_ARCH_AMD64 3996 if (pVM->cpum.s.HostFeatures.s.fSsbd) 3997 #endif 3998 { 3999 pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_SSBD; 4000 pVM->cpum.s.GuestFeatures.fSsbd = 1; 4001 } 4002 4003 PCPUMCPUIDLEAF const pSubLeaf2 = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 2); 4004 if (pSubLeaf2) 4005 { 4006 #ifdef RT_ARCH_AMD64 4007 if (pVM->cpum.s.HostFeatures.s.fPsfd) 4008 #endif 4009 { 4010 pSubLeaf2->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_PSFD; 4011 pVM->cpum.s.GuestFeatures.fPsfd = 1; 4012 } 4013 4014 #ifdef RT_ARCH_AMD64 4015 if (pVM->cpum.s.HostFeatures.s.fIpredCtrl) 4016 #endif 4017 { 4018 pSubLeaf2->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL; 4019 pVM->cpum.s.GuestFeatures.fIpredCtrl = 1; 4020 } 4021 4022 #ifdef RT_ARCH_AMD64 4023 if (pVM->cpum.s.HostFeatures.s.fRrsbaCtrl) 4024 #endif 4025 { 4026 pSubLeaf2->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL; 4027 pVM->cpum.s.GuestFeatures.fRrsbaCtrl = 1; 4028 } 4029 4030 #ifdef RT_ARCH_AMD64 4031 if (pVM->cpum.s.HostFeatures.s.fDdpdU) 4032 #endif 4033 { 4034 pSubLeaf2->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U; 4035 pVM->cpum.s.GuestFeatures.fDdpdU = 1; 4036 } 4037 4038 #ifdef RT_ARCH_AMD64 4039 if (pVM->cpum.s.HostFeatures.s.fBhiCtrl) 4040 #endif 4041 { 4042 pSubLeaf2->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL; 4043 pVM->cpum.s.GuestFeatures.fBhiCtrl = 1; 4044 } 3944 4045 } 3945 4046
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