Index: /trunk/include/VBox/vmm/cpum.h
===================================================================
--- /trunk/include/VBox/vmm/cpum.h	(revision 107748)
+++ /trunk/include/VBox/vmm/cpum.h	(revision 107749)
@@ -470,10 +470,30 @@
     /** Supports IA32_SPEC_CTRL.STIBP. */
     uint32_t        fStibp : 1;
+    /** Supports IA32_SPEC_CTRL.SSBD. */
+    uint32_t        fSsbd : 1;
+    /** Supports IA32_SPEC_CTRL.PSFD. */
+    uint32_t        fPsfd : 1;
+    /** Supports IA32_SPEC_CTRL.IPRED_DIS_U/S. */
+    uint32_t        fIpredCtrl : 1;
+    /** Supports IA32_SPEC_CTRL.RRSBA_DIS_U/S. */
+    uint32_t        fRrsbaCtrl : 1;
+    /** Supports IA32_SPEC_CTRL.DDPD_DIS_U. */
+    uint32_t        fDdpdU : 1;
+    /** Supports IA32_SPEC_CTRL.BHI_S. */
+    uint32_t        fBhiCtrl : 1;
     /** Supports IA32_FLUSH_CMD. */
     uint32_t        fFlushCmd : 1;
     /** Supports IA32_ARCH_CAP. */
     uint32_t        fArchCap : 1;
+    /** Supports IA32_CORE_CAP. */
+    uint32_t        fCoreCap : 1;
     /** Supports MD_CLEAR functionality (VERW, IA32_FLUSH_CMD). */
     uint32_t        fMdsClear : 1;
+    /** Whether susceptible to MXCSR configuration dependent timing (MCDT) behaviour. */
+    uint32_t        fMcdtNo : 1;
+    /** Whether susceptible MONITOR/UMONITOR internal table capacity issues. */
+    uint32_t        fMonitorMitgNo : 1;
+    /** Supports the UC-lock disable feature. */
+    uint32_t        fUcLockDis : 1;
     /** Supports PCID. */
     uint32_t        fPcid : 1;
@@ -620,5 +640,5 @@
 
     /** Alignment padding / reserved for future use. */
-    uint32_t        fPadding0 : 28;
+    uint32_t        fPadding0 : 18;
     uint32_t        auPadding[3];
 
Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp	(revision 107748)
+++ /trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp	(revision 107749)
@@ -1505,7 +1505,21 @@
             pFeatures->fIbrs                = pFeatures->fIbpb;
             pFeatures->fStibp               = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
+            pFeatures->fSsbd                = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_SSBD);
             pFeatures->fFlushCmd            = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
             pFeatures->fArchCap             = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
+            pFeatures->fCoreCap             = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_CORECAP);
             pFeatures->fMdsClear            = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
+        }
+        PCCPUMCPUIDLEAF const pSxfLeaf2 = cpumCpuIdFindLeafEx(paLeaves, cLeaves, 7, 2);
+        if (pSxfLeaf2)
+        {
+            pFeatures->fPsfd                = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_PSFD);
+            pFeatures->fIpredCtrl           = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL);
+            pFeatures->fRrsbaCtrl           = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL);
+            pFeatures->fDdpdU               = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U);
+            pFeatures->fBhiCtrl             = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL);
+            pFeatures->fMcdtNo              = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO);
+            pFeatures->fUcLockDis           = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_UC_LOCK_DIS);
+            pFeatures->fMonitorMitgNo       = RT_BOOL(pSxfLeaf2->uEdx & X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO);
         }
 
Index: /trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp	(revision 107748)
+++ /trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp	(revision 107749)
@@ -1066,4 +1066,6 @@
     CPUMISAEXTCFG   enmFma;
     CPUMISAEXTCFG   enmF16c;
+    CPUMISAEXTCFG   enmMcdtNo;
+    CPUMISAEXTCFG   enmMonitorMitgNo;
 
     CPUMISAEXTCFG   enmAbm;
@@ -1860,5 +1862,5 @@
             case 0:
             {
-                pCurLeaf->uEax  = 0;    /* Max ECX input is 0. */
+                pCurLeaf->uEax  = RT_MIN(pCurLeaf->uEax, 2); /* Max ECX input is 2. */
                 pCurLeaf->uEbx &= 0
                                | PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
@@ -1899,9 +1901,14 @@
                                ;
                 pCurLeaf->uEdx &= 0
+                               //| X86_CPUID_STEXT_FEATURE_EDX_SRBDS_CTRL        RT_BIT(9)
                                | PASSTHRU_FEATURE(pConfig->enmMdsClear,   pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
+                               //| X86_CPUID_STEXT_FEATURE_EDX_TSX_FORCE_ABORT   RT_BIT_32(11)
+                               //| X86_CPUID_STEXT_FEATURE_EDX_CET_IBT           RT_BIT(20)
                                //| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB         RT_BIT(26)
                                //| X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT(27)
                                | PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
                                | PASSTHRU_FEATURE(pConfig->enmArchCapMsr,  pHstFeat->fArchCap,  X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
+                               //| X86_CPUID_STEXT_FEATURE_EDX_CORECAP           RT_BIT_32(30)
+                               //| X86_CPUID_STEXT_FEATURE_EDX_SSBD              RT_BIT_32(31)
                                ;
 
@@ -1962,4 +1969,29 @@
                 if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
                     pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
+                break;
+            }
+
+            case 2:
+            {
+                pCurLeaf->uEax  = 0;
+                pCurLeaf->uEbx  = 0;
+                pCurLeaf->uEcx  = 0;
+                pCurLeaf->uEdx &= 0
+                               //| X86_CPUID_STEXT_FEATURE_2_EDX_PSFD              RT_BIT_32(0)
+                               //| X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL        RT_BIT_32(1)
+                               //| X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL        RT_BIT_32(2)
+                               //| X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U            RT_BIT_32(3)
+                               //| X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL          RT_BIT_32(4)
+                               | PASSTHRU_FEATURE(pConfig->enmMcdtNo, pHstFeat->fMcdtNo, X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO)
+                               //| X86_CPUID_STEXT_FEATURE_2_EDX_UC_LOCK_DIS       RT_BIT_32(6)
+                               //| Bit 7 - MONITOR_MITG_NO - No need for MONITOR/UMONITOR power mitigrations. */
+                               | PASSTHRU_FEATURE(pConfig->enmMonitorMitgNo, pHstFeat->fMonitorMitgNo, X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO)
+                               ;
+
+                /* Force standard feature bits. */
+                if (pConfig->enmMcdtNo == CPUMISAEXTCFG_ENABLED_ALWAYS)
+                    pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_MCDT_NO;
+                if (pConfig->enmMonitorMitgNo == CPUMISAEXTCFG_ENABLED_ALWAYS)
+                    pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_MONITOR_MITG_NO;
                 break;
             }
@@ -2864,4 +2896,6 @@
                                   "|FMA"
                                   "|F16C"
+                                  "|McdtNo"
+                                  "|MonitorMitgNo"
                                   "|ABM"
                                   "|SSE4A"
@@ -3071,4 +3105,18 @@
     rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "F16C", &pConfig->enmF16c, fNestedPagingAndFullGuestExec /* temporarily */,
                                     fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /*fAllowed*/);
+    AssertLogRelRCReturn(rc, rc);
+
+    /** @cfgm{/CPUM/IsaExts/McdtNo, isaextcfg, true}
+     * Whether the CPU is not susceptible to the MXCSR configuration dependent
+     * timing (MCDT) behaviour.
+     */
+    rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "McdtNo", &pConfig->enmMcdtNo, CPUMISAEXTCFG_ENABLED_SUPPORTED);
+    AssertLogRelRCReturn(rc, rc);
+
+    /** @cfgm{/CPUM/IsaExts/MonitorMitgNo, isaextcfg, true}
+     * Whether the CPU is not susceptible MONITOR/UMONITOR internal table capacity
+     * issues.
+     */
+    rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MonitorMitgNo", &pConfig->enmMonitorMitgNo, CPUMISAEXTCFG_ENABLED_SUPPORTED);
     AssertLogRelRCReturn(rc, rc);
 
@@ -3934,4 +3982,5 @@
 #endif
                 {
+/** @todo make this more configurable? */
                     pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
                     pVM->cpum.s.GuestFeatures.fIbrs = 1;
@@ -3942,4 +3991,56 @@
                         pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
                         pVM->cpum.s.GuestFeatures.fStibp = 1;
+                    }
+
+#ifdef RT_ARCH_AMD64
+                    if (pVM->cpum.s.HostFeatures.s.fSsbd)
+#endif
+                    {
+                        pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_SSBD;
+                        pVM->cpum.s.GuestFeatures.fSsbd = 1;
+                    }
+
+                    PCPUMCPUIDLEAF const pSubLeaf2 = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 2);
+                    if (pSubLeaf2)
+                    {
+#ifdef RT_ARCH_AMD64
+                        if (pVM->cpum.s.HostFeatures.s.fPsfd)
+#endif
+                        {
+                            pSubLeaf2->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_PSFD;
+                            pVM->cpum.s.GuestFeatures.fPsfd = 1;
+                        }
+
+#ifdef RT_ARCH_AMD64
+                        if (pVM->cpum.s.HostFeatures.s.fIpredCtrl)
+#endif
+                        {
+                            pSubLeaf2->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_IPRED_CTRL;
+                            pVM->cpum.s.GuestFeatures.fIpredCtrl = 1;
+                        }
+
+#ifdef RT_ARCH_AMD64
+                        if (pVM->cpum.s.HostFeatures.s.fRrsbaCtrl)
+#endif
+                        {
+                            pSubLeaf2->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_RRSBA_CTRL;
+                            pVM->cpum.s.GuestFeatures.fRrsbaCtrl = 1;
+                        }
+
+#ifdef RT_ARCH_AMD64
+                        if (pVM->cpum.s.HostFeatures.s.fDdpdU)
+#endif
+                        {
+                            pSubLeaf2->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_DDPD_U;
+                            pVM->cpum.s.GuestFeatures.fDdpdU = 1;
+                        }
+
+#ifdef RT_ARCH_AMD64
+                        if (pVM->cpum.s.HostFeatures.s.fBhiCtrl)
+#endif
+                        {
+                            pSubLeaf2->uEdx |= X86_CPUID_STEXT_FEATURE_2_EDX_BHI_CTRL;
+                            pVM->cpum.s.GuestFeatures.fBhiCtrl = 1;
+                        }
                     }
 
