Changeset 107763 in vbox for trunk/src/VBox/VMM

Timestamp:

Jan 14, 2025 4:12:57 PM (3 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

166876

Message:

VMM/CPUM,DBGF: Register IA32_ARCH_CAPABILITIES and IA32_SPEC_CTRL as CPU registers with DBGF. jiraref:VBP-947

Location:

trunk/src/VBox/VMM/VMMR3

Files:

• CPUMDbg.cpp (modified) (2 diffs)
• DBGFReg.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp

@@ -1092 +1092 @@
 };
 #endif
+
+/** Sub-fields for the IA32_ARCH_CAP MSR. */
+static DBGFREGSUBFIELD const g_aCpumRegFields_msr_ia32_arch_cap[] =
+{
+    DBGFREGSUBFIELD_RW("rdcl_no",                   0, 1, 0),
+    DBGFREGSUBFIELD_RW("ibrs_all",                  1, 1, 0),
+    DBGFREGSUBFIELD_RW("rsbo",                      2, 1, 0),
+    DBGFREGSUBFIELD_RW("vmm_need_not_flush_l1d",    3, 1, 0),
+    DBGFREGSUBFIELD_RW("ssb_no",                    4, 1, 0),
+    DBGFREGSUBFIELD_RW("mds_no",                    5, 1, 0),
+    DBGFREGSUBFIELD_RW("if_pschange_mc_no",         6, 1, 0),
+    DBGFREGSUBFIELD_RW("tsx_ctrl",                  7, 1, 0),
+    DBGFREGSUBFIELD_RW("taa_no",                    8, 1, 0),
+    DBGFREGSUBFIELD_RW("misc_package_ctrls",       10, 1, 0),
+    DBGFREGSUBFIELD_RW("energy_filtering_ctl",     11, 1, 0),
+    DBGFREGSUBFIELD_RW("doitm",                    12, 1, 0),
+    DBGFREGSUBFIELD_RW("sbdr_ssdp_no",             13, 1, 0),
+    DBGFREGSUBFIELD_RW("fbsdp_no",                 14, 1, 0),
+    DBGFREGSUBFIELD_RW("psdp_no",                  15, 1, 0),
+    DBGFREGSUBFIELD_RW("fb_clear",                 17, 1, 0),
+    DBGFREGSUBFIELD_RW("fb_clear_ctrl",            18, 1, 0),
+    DBGFREGSUBFIELD_RW("rrsba",                    19, 1, 0),
+    DBGFREGSUBFIELD_RW("bhi_no",                   20, 1, 0),
+    DBGFREGSUBFIELD_RW("xapic_disable_status",     21, 1, 0),
+    DBGFREGSUBFIELD_RW("overclocking_status",      23, 1, 0),
+    DBGFREGSUBFIELD_RW("pbrsb_no",                 24, 1, 0),
+    DBGFREGSUBFIELD_RW("gds_ctrl",                 25, 1, 0),
+    DBGFREGSUBFIELD_RW("gds_no",                   26, 1, 0),
+    DBGFREGSUBFIELD_RW("rfds_no",                  27, 1, 0),
+    DBGFREGSUBFIELD_RW("rfds_clear",               28, 1, 0),
+    DBGFREGSUBFIELD_RW("ign_umonitor_support",     29, 1, 0),
+    DBGFREGSUBFIELD_RW("mon_umon_mitig_support",   30, 1, 0),
+    DBGFREGSUBFIELD_TERMINATOR()
+};
+
+/** Sub-fields for the IA32_SPEC_CTRL MSR. */
+static DBGFREGSUBFIELD const g_aCpumRegFields_msr_ia32_spec_ctrl[] =
+{
+    DBGFREGSUBFIELD_RW("ibrs",          0, 1, 0),
+    DBGFREGSUBFIELD_RW("stibp",         1, 1, 0),
+    DBGFREGSUBFIELD_RW("ssbd",          2, 1, 0),
+    DBGFREGSUBFIELD_RW("ipred_dis_u",   3, 1, 0),
+    DBGFREGSUBFIELD_RW("ipred_dis_s",   4, 1, 0),
+    DBGFREGSUBFIELD_RW("rrsba_dis_u",   5, 1, 0),
+    DBGFREGSUBFIELD_RW("rrsba_dis_s",   6, 1, 0),
+    DBGFREGSUBFIELD_RW("psfd",          7, 1, 0),
+    DBGFREGSUBFIELD_RW("ddpd_u",        8, 1, 0),
+    DBGFREGSUBFIELD_RW("bhi_dis_s",    10, 1, 0),
+    DBGFREGSUBFIELD_TERMINATOR()
+};
 
 
@@ -1244 +1294 @@
     CPU_REG_MSR("sysenter_esp",  IA32_SYSENTER_ESP, U64, NULL                        ),
     CPU_REG_MSR("tsc",           IA32_TSC,          U32, NULL                        ),
+    CPU_REG_MSR("msr_ia32_arch_cap",  IA32_ARCH_CAPABILITIES,   U64, g_aCpumRegFields_msr_ia32_arch_cap),
+    CPU_REG_MSR("msr_ia32_spec_ctrl", IA32_SPEC_CTRL,           U64, g_aCpumRegFields_msr_ia32_spec_ctrl),
     CPU_REG_MSR("efer",          K6_EFER,           U32, g_aCpumRegFields_efer       ),
     CPU_REG_MSR("star",          K6_STAR,           U64, g_aCpumRegFields_star       ),

trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp

@@ -2216 +2216 @@
         dbgfR3RegValClear(&paRegs[iReg].Val);
         int rc2 = pSet->paDescs[iReg].pfnGet(pSet->uUserArg.pv, &pSet->paDescs[iReg], &paRegs[iReg].Val);
+        AssertMsg(rc2 == VINF_SUCCESS || rc2 == VERR_CPUM_RAISE_GP_0, ("rc2=%Rrc iReg=%u %s\n", rc2, iReg, paRegs[iReg].pszName));
         AssertRCSuccess(rc2);
         if (RT_FAILURE(rc2))