Changeset 107853 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Jan 18, 2025 4:36:25 PM (8 weeks ago)
- svn:sync-xref-src-repo-rev:
- 167052
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Network/DevDP8390.cpp
r107841 r107853 2378 2378 2379 2379 2380 static int dp8390CoreWriteCR(PPDMDEVINS pDevIns, PDPNICSTATE pThis, uint 32_t val)2380 static int dp8390CoreWriteCR(PPDMDEVINS pDevIns, PDPNICSTATE pThis, uint8_t val) 2381 2381 { 2382 2382 union { … … 2469 2469 } 2470 2470 2471 static int dp8390CoreWrite(PPDMDEVINS pDevIns, PDPNICSTATE pThis, int ofs, uint 32_t val)2471 static int dp8390CoreWrite(PPDMDEVINS pDevIns, PDPNICSTATE pThis, int ofs, uint8_t val) 2472 2472 { 2473 2473 int rc = VINF_SUCCESS; … … 2826 2826 2827 2827 2828 static int dpNeIoWrite(PPDMDEVINS pDevIns, PDPNICSTATE pThis, uint32_t addr, uint32_t val)2828 static int dpNeIoWrite(PPDMDEVINS pDevIns, PDPNICSTATE pThis, int addr, uint16_t val) 2829 2829 { 2830 2830 int reg = addr & 0x0f; 2831 2831 int rc = VINF_SUCCESS; 2832 2832 2833 Log2Func(("#%d: addr=%#06x val=%#04x\n", pThis->iInstance, addr, val & 0xff));2833 Log2Func(("#%d: addr=%#06x val=%#04x\n", pThis->iInstance, addr, val)); 2834 2834 2835 2835 /* The NE2000 has 8 bytes of data port followed by 8 bytes of reset port. … … 2848 2848 2849 2849 2850 static uint 32_t neIoRead(PPDMDEVINS pDevIns, PDPNICSTATE pThis, uint32_t addr)2851 { 2852 uint 32_t val = UINT32_MAX;2850 static uint16_t neIoRead(PPDMDEVINS pDevIns, PDPNICSTATE pThis, int addr) 2851 { 2852 uint16_t val = UINT16_MAX; 2853 2853 int reg = addr & 0x0f; 2854 2854 … … 2864 2864 val = neDataPortRead(pDevIns, pThis); 2865 2865 2866 Log2Func(("#%d: addr=%#06x val=%#04x\n", pThis->iInstance, addr, val & 0xff));2866 Log2Func(("#%d: addr=%#06x val=%#04x\n", pThis->iInstance, addr, val)); 2867 2867 return val; 2868 2868 } 2869 2869 2870 2870 2871 static int wdIoWrite(PPDMDEVINS pDevIns, PDPNICSTATE pThis, uint32_t addr, uint32_t val)2871 static int wdIoWrite(PPDMDEVINS pDevIns, PDPNICSTATE pThis, int addr, uint8_t val) 2872 2872 { 2873 2873 int reg = addr & 0xf; … … 2882 2882 }; 2883 2883 2884 Log2Func(("#%d: addr=%#06x val=%#0 4x\n", pThis->iInstance, addr, val & 0xff));2884 Log2Func(("#%d: addr=%#06x val=%#02x\n", pThis->iInstance, addr, val)); 2885 2885 2886 2886 switch (reg) … … 2917 2917 2918 2918 2919 static uint 32_t wdIoRead(PDPNICSTATE pThis, uint32_t addr)2920 { 2921 uint 32_t val = UINT32_MAX;2919 static uint8_t wdIoRead(PDPNICSTATE pThis, int addr) 2920 { 2921 uint8_t val = UINT8_MAX; 2922 2922 int reg = addr & 0x0f; 2923 2923 … … 2973 2973 } 2974 2974 2975 Log2Func(("#%d: addr=%#0 6x val=%#04x\n", pThis->iInstance, addr, val & 0xff));2975 Log2Func(("#%d: addr=%#04x val=%#04x\n", pThis->iInstance, addr, val)); 2976 2976 return val; 2977 2977 } … … 3178 3178 } 3179 3179 3180 3181 static int elGaDataWrite(PDPNICSTATE pThis, PEL_GA pGa, uint16_t val) 3180 /* The Register File LSB (GAR_RFLSB) port supports 16-bit I/O access, but 3181 * we internally split everything up into 8-bit access anyway. 3182 * That goes for both reading and writing. 3183 */ 3184 static void elGaDataWrite(PDPNICSTATE pThis, PEL_GA pGa, uint8_t val) 3182 3185 { 3183 3186 /* Data write; ignored if not started and in "download" mode. */ … … 3202 3205 } 3203 3206 } 3204 return VINF_SUCCESS;3205 3207 } 3206 3208 … … 3234 3236 3235 3237 3236 static int elGaIoWrite(PPDMDEVINS pDevIns, PDPNICSTATE pThis, uint32_t addr, uint32_t val)3238 static int elGaIoWrite(PPDMDEVINS pDevIns, PDPNICSTATE pThis, int addr, uint8_t val) 3237 3239 { 3238 3240 int reg = addr & 0xf; … … 3240 3242 PEL_GA pGa = &pThis->ga; 3241 3243 3242 Log2Func(("#%d: addr=%#0 6x val=%#04x\n", pThis->iInstance, addr, val & 0xff));3244 Log2Func(("#%d: addr=%#04x val=%#02x\n", pThis->iInstance, addr, val)); 3243 3245 3244 3246 switch (reg) … … 3300 3302 3301 3303 3302 static uint 32_t elGaIoRead(PDPNICSTATE pThis, uint32_t addr)3303 { 3304 uint 32_t val = UINT32_MAX;3304 static uint8_t elGaIoRead(PDPNICSTATE pThis, int addr) 3305 { 3306 uint8_t val = UINT8_MAX; 3305 3307 int reg = addr & 0x0f; 3306 3308 PEL_GA pGa = &pThis->ga; … … 3359 3361 } 3360 3362 3361 Log2Func(("#%d: addr=%#06x val=%#04x\n", pThis->iInstance, addr, val & 0xff));3363 Log2Func(("#%d: addr=%#06x val=%#04x\n", pThis->iInstance, addr, val)); 3362 3364 return val; 3363 3365 } … … 3372 3374 PDPNICSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDPNICSTATE); 3373 3375 int rc = VINF_SUCCESS; 3374 intreg = Port & 0xf;3376 RTIOPORT reg = Port & 0xf; 3375 3377 uint8_t u8Lo, u8Hi = 0; 3376 3378 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a); … … 3381 3383 { 3382 3384 case 1: 3383 *pu32 = neIoRead(pDevIns, pThis, reg);3385 *pu32 = neIoRead(pDevIns, pThis, Port); 3384 3386 break; 3385 3387 case 2: … … 3462 3464 { 3463 3465 case 1: 3464 *pu32 = elGaIoRead(pThis, reg);3466 *pu32 = elGaIoRead(pThis, Port); 3465 3467 break; 3466 3468 case 2: … … 3550 3552 else 3551 3553 { 3552 rc = dpNeIoWrite(pDevIns, pThis, reg + 0, RT_LOBYTE( u32));3554 rc = dpNeIoWrite(pDevIns, pThis, reg + 0, RT_LOBYTE(RT_LOWORD(u32))); 3553 3555 if (RT_SUCCESS(rc) && (reg < 0xf)) 3554 rc = dpNeIoWrite(pDevIns, pThis, reg + 1, RT_HIBYTE( u32));3556 rc = dpNeIoWrite(pDevIns, pThis, reg + 1, RT_HIBYTE(RT_LOWORD(u32))); 3555 3557 } 3556 3558 break; … … 3587 3589 case 2: 3588 3590 /* Manually split word access. */ 3589 rc = wdIoWrite(pDevIns, pThis, reg + 0, RT_LOBYTE( u32));3591 rc = wdIoWrite(pDevIns, pThis, reg + 0, RT_LOBYTE(RT_LOWORD(u32))); 3590 3592 if (RT_SUCCESS(rc) && (reg < 0xf)) 3591 rc = wdIoWrite(pDevIns, pThis, reg + 1, RT_HIBYTE( u32));3593 rc = wdIoWrite(pDevIns, pThis, reg + 1, RT_HIBYTE(RT_LOWORD(u32))); 3592 3594 break; 3593 3595 default: … … 3623 3625 case 2: 3624 3626 /* Manually split word access. */ 3625 rc = elGaIoWrite(pDevIns, pThis, reg + 0, RT_LOBYTE( u32));3627 rc = elGaIoWrite(pDevIns, pThis, reg + 0, RT_LOBYTE(RT_LOWORD(u32))); 3626 3628 if (RT_SUCCESS(rc) && (reg < 0xf)) 3627 rc = elGaIoWrite(pDevIns, pThis, reg + 1, RT_HIBYTE( u32));3629 rc = elGaIoWrite(pDevIns, pThis, reg + 1, RT_HIBYTE(RT_LOWORD(u32))); 3628 3630 break; 3629 3631 default: … … 3659 3661 case 2: 3660 3662 /* Manually split word access. */ 3661 rc = dp8390CoreWrite(pDevIns, pThis, reg + 0, RT_LOBYTE( u32));3663 rc = dp8390CoreWrite(pDevIns, pThis, reg + 0, RT_LOBYTE(RT_LOWORD(u32))); 3662 3664 if (!RT_SUCCESS(rc)) 3663 3665 break; 3664 rc = dp8390CoreWrite(pDevIns, pThis, reg + 1, RT_HIBYTE( u32));3666 rc = dp8390CoreWrite(pDevIns, pThis, reg + 1, RT_HIBYTE(RT_LOWORD(u32))); 3665 3667 break; 3666 3668 default: … … 5074 5076 * Default resource assignments depend on the device type. 5075 5077 */ 5076 unsigneduDefIoPort = 0; /* To be overridden. */5077 u nsigneduDefIrq = 0;5078 u nsigneduDefDma = 0; /* Default to no DMA. */5078 RTIOPORT uDefIoPort = 0; /* To be overridden. */ 5079 uint8_t uDefIrq = 0; 5080 uint8_t uDefDma = 0; /* Default to no DMA. */ 5079 5081 unsigned uDefMemBase = 0; /* Default to no shared memory. */ 5080 5082
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