Changeset 107854 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Jan 18, 2025 11:59:26 PM (4 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

167053

Message:

x86.h,VMM: More AMD CPUID bits; addressed some old todos related to these; fixed bugs in svn & vmx world switcher (sanity checks, ++). jiraref:VBP-947 bugref:10738

File:

• trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp

@@ -1403 +1403 @@
 
 
+void cpumCpuIdExplodeFeaturesX86SetSummaryBits(CPUMFEATURESX86 *pFeatures)
+{
+    /* Summary or all bits indicating the presence of the IA32_SPEC_CTRL MSR. */
+    pFeatures->fSpecCtrlMsr = pFeatures->fIbrs
+                            | pFeatures->fStibp
+                            | pFeatures->fSsbd
+                            | pFeatures->fPsfd
+                            | pFeatures->fIpredCtrl
+                            | pFeatures->fRrsbaCtrl
+                            | pFeatures->fDdpdU
+                            | pFeatures->fBhiCtrl
+                            ;
+}
+
+
 int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, CPUMFEATURESX86 *pFeatures)
 {
@@ -1565 +1580 @@
             pFeatures->fMmx            |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MMX);
             pFeatures->fTsc            |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_TSC);
-            pFeatures->fIbpb           |= pExtLeaf8 && (pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
             pFeatures->fAmdMmxExts      = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_AXMMX);
             pFeatures->fXop             = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_XOP);
             pFeatures->fTbm             = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_TBM);
             pFeatures->fSvm             = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM);
+
+            if (pExtLeaf8)
+            {
+                pFeatures->fIbpb      |= RT_BOOL(pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBPB);
+                pFeatures->fIbrs      |= RT_BOOL(pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_IBRS);
+                pFeatures->fStibp     |= RT_BOOL(pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_STIBP);
+                pFeatures->fSsbd      |= RT_BOOL(pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD);
+                pFeatures->fPsfd      |= RT_BOOL(pExtLeaf8->uEbx & X86_CPUID_AMD_EFEID_EBX_PSFD);
+            }
+
+            PCCPUMCPUIDLEAF pExtLeaf21 = cpumCpuIdFindLeaf(paLeaves, cLeaves, 0x80000021);
+            if (pExtLeaf21)
+            {
+                /** @todo IBPB_BRTYPE is implied on Zen 1 & 2.
+                 *  https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf */
+            }
+
             if (pFeatures->fSvm)
             {
@@ -1655 +1686 @@
     else
         AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
+
+    cpumCpuIdExplodeFeaturesX86SetSummaryBits(pFeatures);
     return VINF_SUCCESS;
 }
@@ -1662 +1695 @@
  * Helper for extracting feature bits from IA32_ARCH_CAPABILITIES.
  */
-static void cpumCpuIdExplodeArchCapabilities(CPUMFEATURESX86 *pFeatures, bool fHasArchCap, uint64_t fArchVal)
+void cpumCpuIdExplodeArchCapabilities(CPUMFEATURESX86 *pFeatures, bool fHasArchCap, uint64_t fArchVal)
 {
     Assert(fHasArchCap || fArchVal == 0);