Changeset 10820 in vbox for trunk/include/VBox
- Timestamp:
- Jul 23, 2008 7:18:14 AM (16 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/hwacc_vmx.h
r10818 r10820 325 325 * @{ 326 326 */ 327 #define MSR VAL_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0)328 #define MSR VAL_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1)329 #define MSR VAL_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2)330 #define MSR VAL_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3)331 #define MSR VAL_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4)332 #define MSR VAL_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5)333 #define MSR VAL_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6)334 #define MSR VAL_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7)335 #define MSR VAL_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8)336 #define MSR VAL_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9)337 #define MSR VAL_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12)338 #define MSR VAL_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13)339 #define MSR VAL_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14)340 #define MSR VAL_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16)341 #define MSR VAL_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17)342 #define MSR VAL_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18)343 #define MSR VAL_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19)344 #define MSR VAL_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20)345 #define MSR VAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24)346 #define MSR VAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25)347 #define MSR VAL_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26)348 #define MSR VAL_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32)349 #define MSR VAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40)350 #define MSR VAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41)351 #define MSR VAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42)352 #define MSR VAL_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43)327 #define MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY RT_BIT_64(0) 328 #define MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY RT_BIT_64(1) 329 #define MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY RT_BIT_64(2) 330 #define MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS RT_BIT_64(3) 331 #define MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS RT_BIT_64(4) 332 #define MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS RT_BIT_64(5) 333 #define MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS RT_BIT_64(6) 334 #define MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS RT_BIT_64(7) 335 #define MSR_IA32_VMX_EPT_CAPS_EMT_UC RT_BIT_64(8) 336 #define MSR_IA32_VMX_EPT_CAPS_EMT_WC RT_BIT_64(9) 337 #define MSR_IA32_VMX_EPT_CAPS_EMT_WT RT_BIT_64(12) 338 #define MSR_IA32_VMX_EPT_CAPS_EMT_WP RT_BIT_64(13) 339 #define MSR_IA32_VMX_EPT_CAPS_EMT_WB RT_BIT_64(14) 340 #define MSR_IA32_VMX_EPT_CAPS_SP_21_BITS RT_BIT_64(16) 341 #define MSR_IA32_VMX_EPT_CAPS_SP_30_BITS RT_BIT_64(17) 342 #define MSR_IA32_VMX_EPT_CAPS_SP_39_BITS RT_BIT_64(18) 343 #define MSR_IA32_VMX_EPT_CAPS_SP_48_BITS RT_BIT_64(19) 344 #define MSR_IA32_VMX_EPT_CAPS_INVEPT RT_BIT_64(20) 345 #define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV RT_BIT_64(24) 346 #define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT RT_BIT_64(25) 347 #define MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL RT_BIT_64(26) 348 #define MSR_IA32_VMX_EPT_CAPS_INVVPID RT_BIT_64(32) 349 #define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV RT_BIT_64(40) 350 #define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT RT_BIT_64(41) 351 #define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL RT_BIT_64(42) 352 #define MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL RT_BIT_64(43) 353 353 354 354 /** @} */
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