Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllOpHlp-x86.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllOpHlp-x86.cpp	(revision 108260)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllOpHlp-x86.cpp	(revision 108278)
@@ -59,301 +59,4 @@
  * Meant to be used via IEM_MC_CALC_RM_EFF_ADDR.
  *
- * @return  Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   bRm                 The ModRM byte.
- * @param   cbImmAndRspOffset   - First byte: The size of any immediate
- *                                following the effective address opcode bytes
- *                                (only for RIP relative addressing).
- *                              - Second byte: RSP displacement (for POP [ESP]).
- * @param   pGCPtrEff           Where to return the effective address.
- */
-VBOXSTRICTRC iemOpHlpCalcRmEffAddr(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, PRTGCPTR pGCPtrEff) RT_NOEXCEPT
-{
-    Log5(("iemOpHlpCalcRmEffAddr: bRm=%#x\n", bRm));
-# define SET_SS_DEF() \
-    do \
-    { \
-        if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SEG_MASK)) \
-            pVCpu->iem.s.iEffSeg = X86_SREG_SS; \
-    } while (0)
-
-    if (!IEM_IS_64BIT_CODE(pVCpu))
-    {
-/** @todo Check the effective address size crap! */
-        if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
-        {
-            uint16_t u16EffAddr;
-
-            /* Handle the disp16 form with no registers first. */
-            if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
-                IEM_OPCODE_GET_NEXT_U16(&u16EffAddr);
-            else
-            {
-                /* Get the displacment. */
-                switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-                {
-                    case 0:  u16EffAddr = 0;                             break;
-                    case 1:  IEM_OPCODE_GET_NEXT_S8_SX_U16(&u16EffAddr); break;
-                    case 2:  IEM_OPCODE_GET_NEXT_U16(&u16EffAddr);       break;
-                    default: AssertFailedReturn(VERR_IEM_IPE_1); /* (caller checked for these) */
-                }
-
-                /* Add the base and index registers to the disp. */
-                switch (bRm & X86_MODRM_RM_MASK)
-                {
-                    case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
-                    case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
-                    case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; SET_SS_DEF(); break;
-                    case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; SET_SS_DEF(); break;
-                    case 4: u16EffAddr += pVCpu->cpum.GstCtx.si;            break;
-                    case 5: u16EffAddr += pVCpu->cpum.GstCtx.di;            break;
-                    case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp;            SET_SS_DEF(); break;
-                    case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx;            break;
-                }
-            }
-
-            *pGCPtrEff = u16EffAddr;
-        }
-        else
-        {
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            uint32_t u32EffAddr;
-
-            /* Handle the disp32 form with no registers first. */
-            if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
-                IEM_OPCODE_GET_NEXT_U32(&u32EffAddr);
-            else
-            {
-                /* Get the register (or SIB) value. */
-                switch ((bRm & X86_MODRM_RM_MASK))
-                {
-                    case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
-                    case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
-                    case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
-                    case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
-                    case 4: /* SIB */
-                    {
-                        uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
-
-                        /* Get the index and scale it. */
-                        switch ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
-                        {
-                            case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
-                            case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
-                            case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
-                            case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
-                            case 4: u32EffAddr = 0; /*none */ break;
-                            case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
-                            case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
-                            case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
-                            IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                        }
-                        u32EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
-
-                        /* add base */
-                        switch (bSib & X86_SIB_BASE_MASK)
-                        {
-                            case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
-                            case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
-                            case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
-                            case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
-                            case 4: u32EffAddr += pVCpu->cpum.GstCtx.esp + (cbImmAndRspOffset >> 8); SET_SS_DEF(); break;
-                            case 5:
-                                if ((bRm & X86_MODRM_MOD_MASK) != 0)
-                                {
-                                    u32EffAddr += pVCpu->cpum.GstCtx.ebp;
-                                    SET_SS_DEF();
-                                }
-                                else
-                                {
-                                    uint32_t u32Disp;
-                                    IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                                    u32EffAddr += u32Disp;
-                                }
-                                break;
-                            case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
-                            case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
-                            IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                        }
-                        break;
-                    }
-                    case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; SET_SS_DEF(); break;
-                    case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
-                    case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
-                    IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                }
-
-                /* Get and add the displacement. */
-                switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-                {
-                    case 0:
-                        break;
-                    case 1:
-                    {
-                        int8_t i8Disp; IEM_OPCODE_GET_NEXT_S8(&i8Disp);
-                        u32EffAddr += i8Disp;
-                        break;
-                    }
-                    case 2:
-                    {
-                        uint32_t u32Disp; IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                        u32EffAddr += u32Disp;
-                        break;
-                    }
-                    default:
-                        AssertFailedReturn(VERR_IEM_IPE_2); /* (caller checked for these) */
-                }
-
-            }
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            *pGCPtrEff = u32EffAddr;
-        }
-    }
-    else
-    {
-        uint64_t u64EffAddr;
-
-        /* Handle the rip+disp32 form with no registers first. */
-        if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
-        {
-            IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64EffAddr);
-            u64EffAddr += pVCpu->cpum.GstCtx.rip + IEM_GET_INSTR_LEN(pVCpu) + (cbImmAndRspOffset & UINT32_C(0xff));
-        }
-        else
-        {
-            /* Get the register (or SIB) value. */
-            switch ((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB)
-            {
-                case  0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
-                case  1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
-                case  2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
-                case  3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
-                case  5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; SET_SS_DEF(); break;
-                case  6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
-                case  7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
-                case  8: u64EffAddr = pVCpu->cpum.GstCtx.r8;  break;
-                case  9: u64EffAddr = pVCpu->cpum.GstCtx.r9;  break;
-                case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
-                case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
-                case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
-                case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
-                case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
-                /* SIB */
-                case 4:
-                case 12:
-                {
-                    uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
-
-                    /* Get the index and scale it. */
-                    switch (((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex)
-                    {
-                        case  0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
-                        case  1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
-                        case  2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
-                        case  3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
-                        case  4: u64EffAddr = 0; /*none */ break;
-                        case  5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
-                        case  6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
-                        case  7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
-                        case  8: u64EffAddr = pVCpu->cpum.GstCtx.r8;  break;
-                        case  9: u64EffAddr = pVCpu->cpum.GstCtx.r9;  break;
-                        case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
-                        case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
-                        case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
-                        case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
-                        case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
-                        case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
-                        IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                    }
-                    u64EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
-
-                    /* add base */
-                    switch ((bSib & X86_SIB_BASE_MASK) | pVCpu->iem.s.uRexB)
-                    {
-                        case  0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
-                        case  1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
-                        case  2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
-                        case  3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
-                        case  4: u64EffAddr += pVCpu->cpum.GstCtx.rsp + (cbImmAndRspOffset >> 8); SET_SS_DEF(); break;
-                        case  6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
-                        case  7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
-                        case  8: u64EffAddr += pVCpu->cpum.GstCtx.r8;  break;
-                        case  9: u64EffAddr += pVCpu->cpum.GstCtx.r9;  break;
-                        case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
-                        case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
-                        case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
-                        case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
-                        case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
-                        /* complicated encodings */
-                        case 5:
-                        case 13:
-                            if ((bRm & X86_MODRM_MOD_MASK) != 0)
-                            {
-                                if (!pVCpu->iem.s.uRexB)
-                                {
-                                    u64EffAddr += pVCpu->cpum.GstCtx.rbp;
-                                    SET_SS_DEF();
-                                }
-                                else
-                                    u64EffAddr += pVCpu->cpum.GstCtx.r13;
-                            }
-                            else
-                            {
-                                uint32_t u32Disp;
-                                IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                                u64EffAddr += (int32_t)u32Disp;
-                            }
-                            break;
-                        IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                    }
-                    break;
-                }
-                IEM_NOT_REACHED_DEFAULT_CASE_RET();
-            }
-
-            /* Get and add the displacement. */
-            switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-            {
-                case 0:
-                    break;
-                case 1:
-                {
-                    int8_t i8Disp;
-                    IEM_OPCODE_GET_NEXT_S8(&i8Disp);
-                    u64EffAddr += i8Disp;
-                    break;
-                }
-                case 2:
-                {
-                    uint32_t u32Disp;
-                    IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                    u64EffAddr += (int32_t)u32Disp;
-                    break;
-                }
-                IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* (caller checked for these) */
-            }
-
-        }
-
-        if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
-            *pGCPtrEff = u64EffAddr;
-        else
-        {
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            *pGCPtrEff = u64EffAddr & UINT32_MAX;
-        }
-    }
-
-    Log5(("iemOpHlpCalcRmEffAddr: EffAddr=%#010RGv\n", *pGCPtrEff));
-    return VINF_SUCCESS;
-}
-
-
-#ifdef IEM_WITH_SETJMP
-/**
- * Calculates the effective address of a ModR/M memory operand.
- *
- * Meant to be used via IEM_MC_CALC_RM_EFF_ADDR.
- *
  * May longjmp on internal error.
  *
@@ -369,5 +72,5 @@
 {
     Log5(("iemOpHlpCalcRmEffAddrJmp: bRm=%#x\n", bRm));
-# define SET_SS_DEF() \
+#define SET_SS_DEF() \
     do \
     { \
@@ -642,324 +345,4 @@
     return u64EffAddr & UINT32_MAX;
 }
-#endif /* IEM_WITH_SETJMP */
-
-
-/**
- * Calculates the effective address of a ModR/M memory operand, extended version
- * for use in the recompilers.
- *
- * Meant to be used via IEM_MC_CALC_RM_EFF_ADDR.
- *
- * @return  Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   bRm                 The ModRM byte.
- * @param   cbImmAndRspOffset   - First byte: The size of any immediate
- *                                following the effective address opcode bytes
- *                                (only for RIP relative addressing).
- *                              - Second byte: RSP displacement (for POP [ESP]).
- * @param   pGCPtrEff           Where to return the effective address.
- * @param   puInfo              Extra info: 32-bit displacement (bits 31:0) and
- *                              SIB byte (bits 39:32).
- */
-VBOXSTRICTRC iemOpHlpCalcRmEffAddrEx(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, PRTGCPTR pGCPtrEff, uint64_t *puInfo) RT_NOEXCEPT
-{
-    Log5(("iemOpHlpCalcRmEffAddr: bRm=%#x\n", bRm));
-# define SET_SS_DEF() \
-    do \
-    { \
-        if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SEG_MASK)) \
-            pVCpu->iem.s.iEffSeg = X86_SREG_SS; \
-    } while (0)
-
-    uint64_t uInfo;
-    if (!IEM_IS_64BIT_CODE(pVCpu))
-    {
-/** @todo Check the effective address size crap! */
-        if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
-        {
-            uint16_t u16EffAddr;
-
-            /* Handle the disp16 form with no registers first. */
-            if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
-            {
-                IEM_OPCODE_GET_NEXT_U16(&u16EffAddr);
-                uInfo = u16EffAddr;
-            }
-            else
-            {
-                /* Get the displacment. */
-                switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-                {
-                    case 0:  u16EffAddr = 0;                             break;
-                    case 1:  IEM_OPCODE_GET_NEXT_S8_SX_U16(&u16EffAddr); break;
-                    case 2:  IEM_OPCODE_GET_NEXT_U16(&u16EffAddr);       break;
-                    default: AssertFailedReturn(VERR_IEM_IPE_1); /* (caller checked for these) */
-                }
-                uInfo = u16EffAddr;
-
-                /* Add the base and index registers to the disp. */
-                switch (bRm & X86_MODRM_RM_MASK)
-                {
-                    case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
-                    case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
-                    case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; SET_SS_DEF(); break;
-                    case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; SET_SS_DEF(); break;
-                    case 4: u16EffAddr += pVCpu->cpum.GstCtx.si;            break;
-                    case 5: u16EffAddr += pVCpu->cpum.GstCtx.di;            break;
-                    case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp;            SET_SS_DEF(); break;
-                    case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx;            break;
-                }
-            }
-
-            *pGCPtrEff = u16EffAddr;
-        }
-        else
-        {
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            uint32_t u32EffAddr;
-
-            /* Handle the disp32 form with no registers first. */
-            if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
-            {
-                IEM_OPCODE_GET_NEXT_U32(&u32EffAddr);
-                uInfo = u32EffAddr;
-            }
-            else
-            {
-                /* Get the register (or SIB) value. */
-                uInfo = 0;
-                switch ((bRm & X86_MODRM_RM_MASK))
-                {
-                    case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
-                    case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
-                    case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
-                    case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
-                    case 4: /* SIB */
-                    {
-                        uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
-                        uInfo = (uint64_t)bSib << 32;
-
-                        /* Get the index and scale it. */
-                        switch ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
-                        {
-                            case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
-                            case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
-                            case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
-                            case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
-                            case 4: u32EffAddr = 0; /*none */ break;
-                            case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
-                            case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
-                            case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
-                            IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                        }
-                        u32EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
-
-                        /* add base */
-                        switch (bSib & X86_SIB_BASE_MASK)
-                        {
-                            case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
-                            case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
-                            case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
-                            case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
-                            case 4: u32EffAddr += pVCpu->cpum.GstCtx.esp + (cbImmAndRspOffset >> 8); SET_SS_DEF(); break;
-                            case 5:
-                                if ((bRm & X86_MODRM_MOD_MASK) != 0)
-                                {
-                                    u32EffAddr += pVCpu->cpum.GstCtx.ebp;
-                                    SET_SS_DEF();
-                                }
-                                else
-                                {
-                                    uint32_t u32Disp;
-                                    IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                                    u32EffAddr += u32Disp;
-                                    uInfo      |= u32Disp;
-                                }
-                                break;
-                            case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
-                            case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
-                            IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                        }
-                        break;
-                    }
-                    case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; SET_SS_DEF(); break;
-                    case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
-                    case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
-                    IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                }
-
-                /* Get and add the displacement. */
-                switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-                {
-                    case 0:
-                        break;
-                    case 1:
-                    {
-                        int8_t i8Disp; IEM_OPCODE_GET_NEXT_S8(&i8Disp);
-                        u32EffAddr += i8Disp;
-                        uInfo |= (uint32_t)(int32_t)i8Disp;
-                        break;
-                    }
-                    case 2:
-                    {
-                        uint32_t u32Disp; IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                        u32EffAddr += u32Disp;
-                        uInfo      |= (uint32_t)u32Disp;
-                        break;
-                    }
-                    default:
-                        AssertFailedReturn(VERR_IEM_IPE_2); /* (caller checked for these) */
-                }
-
-            }
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            *pGCPtrEff = u32EffAddr;
-        }
-    }
-    else
-    {
-        uint64_t u64EffAddr;
-
-        /* Handle the rip+disp32 form with no registers first. */
-        if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
-        {
-            IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64EffAddr);
-            uInfo = (uint32_t)u64EffAddr;
-            u64EffAddr += pVCpu->cpum.GstCtx.rip + IEM_GET_INSTR_LEN(pVCpu) + (cbImmAndRspOffset & UINT32_C(0xff));
-        }
-        else
-        {
-            /* Get the register (or SIB) value. */
-            uInfo = 0;
-            switch ((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB)
-            {
-                case  0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
-                case  1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
-                case  2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
-                case  3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
-                case  5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; SET_SS_DEF(); break;
-                case  6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
-                case  7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
-                case  8: u64EffAddr = pVCpu->cpum.GstCtx.r8;  break;
-                case  9: u64EffAddr = pVCpu->cpum.GstCtx.r9;  break;
-                case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
-                case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
-                case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
-                case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
-                case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
-                /* SIB */
-                case 4:
-                case 12:
-                {
-                    uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
-                    uInfo = (uint64_t)bSib << 32;
-
-                    /* Get the index and scale it. */
-                    switch (((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex)
-                    {
-                        case  0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
-                        case  1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
-                        case  2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
-                        case  3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
-                        case  4: u64EffAddr = 0; /*none */ break;
-                        case  5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
-                        case  6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
-                        case  7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
-                        case  8: u64EffAddr = pVCpu->cpum.GstCtx.r8;  break;
-                        case  9: u64EffAddr = pVCpu->cpum.GstCtx.r9;  break;
-                        case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
-                        case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
-                        case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
-                        case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
-                        case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
-                        case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
-                        IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                    }
-                    u64EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
-
-                    /* add base */
-                    switch ((bSib & X86_SIB_BASE_MASK) | pVCpu->iem.s.uRexB)
-                    {
-                        case  0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
-                        case  1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
-                        case  2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
-                        case  3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
-                        case  4: u64EffAddr += pVCpu->cpum.GstCtx.rsp + (cbImmAndRspOffset >> 8); SET_SS_DEF(); break;
-                        case  6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
-                        case  7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
-                        case  8: u64EffAddr += pVCpu->cpum.GstCtx.r8;  break;
-                        case  9: u64EffAddr += pVCpu->cpum.GstCtx.r9;  break;
-                        case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
-                        case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
-                        case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
-                        case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
-                        case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
-                        /* complicated encodings */
-                        case 5:
-                        case 13:
-                            if ((bRm & X86_MODRM_MOD_MASK) != 0)
-                            {
-                                if (!pVCpu->iem.s.uRexB)
-                                {
-                                    u64EffAddr += pVCpu->cpum.GstCtx.rbp;
-                                    SET_SS_DEF();
-                                }
-                                else
-                                    u64EffAddr += pVCpu->cpum.GstCtx.r13;
-                            }
-                            else
-                            {
-                                uint32_t u32Disp;
-                                IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                                u64EffAddr += (int32_t)u32Disp;
-                                uInfo      |= u32Disp;
-                            }
-                            break;
-                        IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                    }
-                    break;
-                }
-                IEM_NOT_REACHED_DEFAULT_CASE_RET();
-            }
-
-            /* Get and add the displacement. */
-            switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-            {
-                case 0:
-                    break;
-                case 1:
-                {
-                    int8_t i8Disp;
-                    IEM_OPCODE_GET_NEXT_S8(&i8Disp);
-                    u64EffAddr += i8Disp;
-                    uInfo      |= (uint32_t)(int32_t)i8Disp;
-                    break;
-                }
-                case 2:
-                {
-                    uint32_t u32Disp;
-                    IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                    u64EffAddr += (int32_t)u32Disp;
-                    uInfo      |= u32Disp;
-                    break;
-                }
-                IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* (caller checked for these) */
-            }
-
-        }
-
-        if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
-            *pGCPtrEff = u64EffAddr;
-        else
-        {
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            *pGCPtrEff = u64EffAddr & UINT32_MAX;
-        }
-    }
-    *puInfo = uInfo;
-
-    Log5(("iemOpHlpCalcRmEffAddrEx: EffAddr=%#010RGv uInfo=%RX64\n", *pGCPtrEff, uInfo));
-    return VINF_SUCCESS;
-}
 
 /** @}  */
