Index: trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 108278)
@@ -543,5 +543,4 @@
     RT_NOREF_PV(pszFunction);
 
-#ifdef IEM_WITH_SETJMP
     VBOXSTRICTRC rcStrict;
     IEM_TRY_SETJMP(pVCpu, rcStrict)
@@ -555,8 +554,4 @@
     }
     IEM_CATCH_LONGJMP_END(pVCpu);
-#else
-    uint8_t b; IEM_OPCODE_GET_FIRST_U8(&b);
-    VBOXSTRICTRC rcStrict = FNIEMOP_CALL(g_apfnIemInterpretOnlyOneByteMap[b]);
-#endif
     if (rcStrict == VINF_SUCCESS)
         pVCpu->iem.s.cInstructions++;
@@ -604,5 +599,4 @@
             iemLogCurInstr(pVCpu, false, pszFunction);
 #endif
-#ifdef IEM_WITH_SETJMP
             IEM_TRY_SETJMP_AGAIN(pVCpu, rcStrict)
             {
@@ -615,8 +609,4 @@
             }
             IEM_CATCH_LONGJMP_END(pVCpu);
-#else
-            IEM_OPCODE_GET_FIRST_U8(&b);
-            rcStrict = FNIEMOP_CALL(g_apfnIemInterpretOnlyOneByteMap[b]);
-#endif
             if (rcStrict == VINF_SUCCESS)
             {
@@ -874,8 +864,6 @@
     if (rcStrict == VINF_SUCCESS)
     {
-#ifdef IEM_WITH_SETJMP
         pVCpu->iem.s.cActiveMappings = 0; /** @todo wtf? */
         IEM_TRY_SETJMP(pVCpu, rcStrict)
-#endif
         {
             /*
@@ -960,16 +948,14 @@
             }
         }
-#ifdef IEM_WITH_SETJMP
         IEM_CATCH_LONGJMP_BEGIN(pVCpu, rcStrict);
         {
             if (pVCpu->iem.s.cActiveMappings > 0)
                 iemMemRollback(pVCpu);
-# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
+#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
             rcStrict = iemExecStatusCodeFiddling(pVCpu, rcStrict);
-# endif
+#endif
             pVCpu->iem.s.cLongJumps++;
         }
         IEM_CATCH_LONGJMP_END(pVCpu);
-#endif
 
         /*
@@ -1037,8 +1023,6 @@
     if (rcStrict == VINF_SUCCESS)
     {
-#ifdef IEM_WITH_SETJMP
         pVCpu->iem.s.cActiveMappings     = 0; /** @todo wtf?!? */
         IEM_TRY_SETJMP(pVCpu, rcStrict)
-#endif
         {
 #ifdef IN_RING0
@@ -1147,5 +1131,4 @@
             }
         }
-#ifdef IEM_WITH_SETJMP
         IEM_CATCH_LONGJMP_BEGIN(pVCpu, rcStrict);
         {
@@ -1155,5 +1138,4 @@
         }
         IEM_CATCH_LONGJMP_END(pVCpu);
-#endif
 
         /*
Index: trunk/src/VBox/VMM/VMMAll/IEMAllMem.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllMem.cpp	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllMem.cpp	(revision 108278)
@@ -600,5 +600,4 @@
 }
 
-#ifdef IEM_WITH_SETJMP
 
 /**
@@ -679,5 +678,4 @@
 }
 
-#endif /* IEM_WITH_SETJMP */
 
 #ifndef IN_RING3
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp	(revision 108278)
@@ -93,8 +93,4 @@
 #ifndef IEM_WITH_DATA_TLB
 # error The data TLB must be enabled for the recompiler.
-#endif
-
-#ifndef IEM_WITH_SETJMP
-# error The setjmp approach must be enabled for the recompiler.
 #endif
 
Index: trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp	(revision 108278)
@@ -99,9 +99,4 @@
 # error The data TLB must be enabled for the recompiler.
 #endif
-
-#ifndef IEM_WITH_SETJMP
-# error The setjmp approach must be enabled for the recompiler.
-#endif
-
 
 
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllMem-x86.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllMem-x86.cpp	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllMem-x86.cpp	(revision 108278)
@@ -662,5 +662,4 @@
 }
 
-#ifdef IEM_WITH_SETJMP
 
 /**
@@ -1102,5 +1101,4 @@
 }
 
-#endif /* IEM_WITH_SETJMP */
 
 
@@ -1374,5 +1372,4 @@
 
 
-#ifdef IEM_WITH_SETJMP
 /**
  * Stores a data dqword, SSE aligned.
@@ -1397,5 +1394,4 @@
     Log5(("IEM WR dqword %d|%RGv: %.16Rhxs\n", iSegReg, GCPtrMem, pu128Dst));
 }
-#endif
 
 
@@ -1430,5 +1426,4 @@
 
 
-#ifdef IEM_WITH_SETJMP
 /**
  * Stores a data dqword, longjmp on error.
@@ -1453,5 +1448,4 @@
     Log5(("IEM WR qqword %d|%RGv: %.32Rhxs\n", iSegReg, GCPtrMem, pu256Dst));
 }
-#endif
 
 
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllMemRWTmpl-x86.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllMemRWTmpl-x86.cpp.h	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllMemRWTmpl-x86.cpp.h	(revision 108278)
@@ -51,6 +51,5 @@
  * Standard fetch function.
  *
- * This is used by CImpl code, so it needs to be kept even when IEM_WITH_SETJMP
- * is defined.
+ * This is used by CImpl code.
  */
 VBOXSTRICTRC RT_CONCAT(iemMemFetchData,TMPL_MEM_FN_SUFF)(PVMCPUCC pVCpu, TMPL_MEM_TYPE *puDst,
@@ -72,15 +71,14 @@
 
 
-#ifdef IEM_WITH_SETJMP
 /**
  * Safe/fallback fetch function that longjmps on error.
  */
-# ifdef TMPL_MEM_BY_REF
+#ifdef TMPL_MEM_BY_REF
 void
 RT_CONCAT3(iemMemFetchData,TMPL_MEM_FN_SUFF,SafeJmp)(PVMCPUCC pVCpu, TMPL_MEM_TYPE *pDst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
     pVCpu->iem.s.DataTlb.cTlbSafeReadPath++;
-#  endif
+# endif
     uint8_t              bUnmapInfo;
     TMPL_MEM_TYPE const *pSrc = (TMPL_MEM_TYPE const *)iemMemMapSafeJmp(pVCpu, &bUnmapInfo, sizeof(*pSrc), iSegReg, GCPtrMem,
@@ -90,11 +88,11 @@
     Log2(("IEM RD " TMPL_MEM_FMT_DESC " %d|%RGv: " TMPL_MEM_FMT_TYPE "\n", iSegReg, GCPtrMem, pDst));
 }
-# else /* !TMPL_MEM_BY_REF */
+#else /* !TMPL_MEM_BY_REF */
 TMPL_MEM_TYPE
 RT_CONCAT3(iemMemFetchData,TMPL_MEM_FN_SUFF,SafeJmp)(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
     pVCpu->iem.s.DataTlb.cTlbSafeReadPath++;
-#  endif
+# endif
     uint8_t              bUnmapInfo;
     TMPL_MEM_TYPE const *puSrc = (TMPL_MEM_TYPE const *)iemMemMapSafeJmp(pVCpu, &bUnmapInfo, sizeof(*puSrc), iSegReg, GCPtrMem,
@@ -105,6 +103,5 @@
     return uRet;
 }
-# endif /* !TMPL_MEM_BY_REF */
-#endif /* IEM_WITH_SETJMP */
+#endif /* !TMPL_MEM_BY_REF */
 
 
@@ -113,6 +110,5 @@
  * Standard store function.
  *
- * This is used by CImpl code, so it needs to be kept even when IEM_WITH_SETJMP
- * is defined.
+ * This is used by CImpl code.
  */
 VBOXSTRICTRC RT_CONCAT(iemMemStoreData,TMPL_MEM_FN_SUFF)(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem,
@@ -146,5 +142,4 @@
 
 
-#ifdef IEM_WITH_SETJMP
 /**
  * Stores a data byte, longjmp on error.
@@ -163,7 +158,7 @@
 #endif
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
-    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
-# endif
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
+#endif
 #ifdef TMPL_MEM_BY_REF
     Log6(("IEM WR " TMPL_MEM_FMT_DESC " %d|%RGv: " TMPL_MEM_FMT_TYPE "\n", iSegReg, GCPtrMem, pValue));
@@ -181,8 +176,5 @@
     iemMemCommitAndUnmapJmp(pVCpu, bUnmapInfo);
 }
-#endif /* IEM_WITH_SETJMP */
-
-
-#ifdef IEM_WITH_SETJMP
+
 
 /**
@@ -200,7 +192,7 @@
                                                      uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
-    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
-# endif
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
+#endif
     Log8(("IEM AT/map " TMPL_MEM_FMT_DESC " %d|%RGv\n", iSegReg, GCPtrMem));
     *pbUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ  | IEM_ACCESS_TYPE_WRITE) << 4); /* zero is for the TLB hit */
@@ -224,7 +216,7 @@
                                                      uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
-    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
-# endif
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
+#endif
     Log8(("IEM RW/map " TMPL_MEM_FMT_DESC " %d|%RGv\n", iSegReg, GCPtrMem));
     *pbUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ  | IEM_ACCESS_TYPE_WRITE) << 4); /* zero is for the TLB hit */
@@ -248,7 +240,7 @@
                                                      uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
-    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
-# endif
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
+#endif
     Log8(("IEM WO/map " TMPL_MEM_FMT_DESC " %d|%RGv\n", iSegReg, GCPtrMem));
     *pbUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); /* zero is for the TLB hit */
@@ -272,7 +264,7 @@
                                                      uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
-    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
-# endif
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
+#endif
     Log4(("IEM RO/map " TMPL_MEM_FMT_DESC " %d|%RGv\n", iSegReg, GCPtrMem));
     *pbUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); /* zero is for the TLB hit */
@@ -280,6 +272,4 @@
                                              IEM_ACCESS_DATA_R, TMPL_MEM_TYPE_ALIGN | TMPL_MEM_MAP_FLAGS_ADD);
 }
-
-#endif /* IEM_WITH_SETJMP */
 
 
@@ -483,6 +473,4 @@
 
 
-# ifdef IEM_WITH_SETJMP
-
 /**
  * Safe/fallback stack store function that longjmps on error.
@@ -491,7 +479,7 @@
                                                            TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
-    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
-#  endif
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
+# endif
 
     uint8_t        bUnmapInfo;
@@ -505,5 +493,5 @@
 
 
-#  ifdef TMPL_WITH_PUSH_SREG
+# ifdef TMPL_WITH_PUSH_SREG
 /**
  * Safe/fallback stack SREG store function that longjmps on error.
@@ -512,7 +500,7 @@
                                                                TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
-    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
-# endif
+#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
+#  endif
 
     /* bs3-cpu-weird-1 explores this instruction. AMD 3990X does it by the book,
@@ -558,5 +546,5 @@
     }
 }
-#  endif /* TMPL_WITH_PUSH_SREG */
+# endif /* TMPL_WITH_PUSH_SREG */
 
 
@@ -640,5 +628,5 @@
 }
 
-#  ifdef TMPL_WITH_PUSH_SREG
+# ifdef TMPL_WITH_PUSH_SREG
 /**
  * Safe/fallback stack push function that longjmps on error.
@@ -646,7 +634,7 @@
 void RT_CONCAT3(iemMemStackPush,TMPL_MEM_FN_SUFF,SRegSafeJmp)(PVMCPUCC pVCpu, TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
-    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
-# endif
+#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+    pVCpu->iem.s.DataTlb.cTlbSafeWritePath++;
+#  endif
 
     /* Decrement the stack pointer (prep). */
@@ -676,7 +664,5 @@
     pVCpu->cpum.GstCtx.rsp = uNewRsp;
 }
-#  endif /* TMPL_WITH_PUSH_SREG */
-
-# endif /* IEM_WITH_SETJMP */
+# endif /* TMPL_WITH_PUSH_SREG */
 
 #endif /* TMPL_MEM_WITH_STACK */
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllMemRWTmplInline-x86.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllMemRWTmplInline-x86.cpp.h	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllMemRWTmplInline-x86.cpp.h	(revision 108278)
@@ -78,7 +78,4 @@
 
 
-#ifdef IEM_WITH_SETJMP
-
-
 /*********************************************************************************************************************************
 *   Fetches                                                                                                                      *
@@ -99,12 +96,12 @@
 {
     AssertCompile(sizeof(TMPL_MEM_TYPE) == TMPL_MEM_TYPE_SIZE);
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Convert from segmented to flat address and check that it doesn't cross a page boundrary.
      */
     RTGCPTR GCPtrEff = iemMemApplySegmentToReadJmp(pVCpu, iSegReg, sizeof(TMPL_MEM_TYPE), GCPtrMem);
-#  if TMPL_MEM_TYPE_SIZE > 1
+# if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(GCPtrEff)))
-#  endif
+# endif
     {
         /*
@@ -128,20 +125,20 @@
                  * Fetch and return the data.
                  */
-#  ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#  endif
-                Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
-                Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
-#  ifdef TMPL_MEM_BY_REF
+# ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+# endif
+                Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
+                Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
+# ifdef TMPL_MEM_BY_REF
                 *pValue = *(TMPL_MEM_TYPE const *)&pTlbe->pbMappingR3[GCPtrEff & GUEST_PAGE_OFFSET_MASK];
                 LogEx(LOG_GROUP_IEM_MEM,("IEM RD " TMPL_MEM_FMT_DESC " %d|%RGv=%RGv: %." RT_XSTR(TMPL_MEM_TYPE_SIZE) "Rhxs\n",
                                          iSegReg, GCPtrMem, GCPtrEff, pValue));
                 return;
-#  else
+# else
                 TMPL_MEM_TYPE const uRet = *(TMPL_MEM_TYPE const *)&pTlbe->pbMappingR3[GCPtrEff & GUEST_PAGE_OFFSET_MASK];
                 LogEx(LOG_GROUP_IEM_MEM,("IEM RD " TMPL_MEM_FMT_DESC " %d|%RGv=%RGv: " TMPL_MEM_FMT_TYPE "\n",
                                          iSegReg, GCPtrMem, GCPtrEff, uRet));
                 return uRet;
-#  endif
+# endif
             }
         }
@@ -151,10 +148,10 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     LogEx(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %u:%RGv falling back\n", LOG_FN_NAME, iSegReg, GCPtrMem));
-# endif
-# ifdef TMPL_MEM_BY_REF
+#endif
+#ifdef TMPL_MEM_BY_REF
     RT_CONCAT3(iemMemFetchData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, pValue, iSegReg, GCPtrMem);
-# else
+#else
     return RT_CONCAT3(iemMemFetchData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, iSegReg, GCPtrMem);
-# endif
+#endif
 }
 
@@ -163,10 +160,162 @@
  * Inlined flat addressing fetch function that longjumps on error.
  */
-# ifdef TMPL_MEM_BY_REF
+#ifdef TMPL_MEM_BY_REF
 DECL_INLINE_THROW(void)
 RT_CONCAT3(iemMemFlatFetchData,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, TMPL_MEM_TYPE *pValue, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
-# else
+#else
 DECL_INLINE_THROW(TMPL_MEM_TYPE)
 RT_CONCAT3(iemMemFlatFetchData,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
+#endif
+{
+    AssertMsg(   (pVCpu->iem.s.fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT
+              || (pVCpu->iem.s.fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT
+              || (pVCpu->iem.s.fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT, ("%#x\n", pVCpu->iem.s.fExec));
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+    /*
+     * Check that it doesn't cross a page boundrary.
+     */
+# if TMPL_MEM_TYPE_SIZE > 1
+    if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(GCPtrMem)))
+# endif
+    {
+        /*
+         * TLB lookup.
+         */
+        uint64_t const uTagNoRev = IEMTLB_CALC_TAG_NO_REV(GCPtrMem);
+        PCIEMTLBENTRY  pTlbe     = IEMTLB_TAG_TO_EVEN_ENTRY(&pVCpu->iem.s.DataTlb, uTagNoRev);
+        if (RT_LIKELY(   pTlbe->uTag               == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevision)
+                      || (pTlbe = pTlbe + 1)->uTag == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevisionGlobal)))
+        {
+            /*
+             * Check TLB page table level access flags.
+             */
+            AssertCompile(IEMTLBE_F_PT_NO_USER == 4);
+            uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER;
+            if (RT_LIKELY(   (pTlbe->fFlagsAndPhysRev & (  IEMTLBE_F_PHYS_REV       | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_READ
+                                                         | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_NO_MAPPINGR3  | fNoUser))
+                          == pVCpu->iem.s.DataTlb.uTlbPhysRev))
+            {
+                /*
+                 * Fetch and return the dword
+                 */
+# ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+# endif
+                Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
+                Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
+# ifdef TMPL_MEM_BY_REF
+                *pValue = *(TMPL_MEM_TYPE const *)&pTlbe->pbMappingR3[GCPtrMem & GUEST_PAGE_OFFSET_MASK];
+                LogEx(LOG_GROUP_IEM_MEM,("IEM RD " TMPL_MEM_FMT_DESC " %RGv: %." RT_XSTR(TMPL_MEM_TYPE_SIZE) "Rhxs\n",
+                                         GCPtrMem, pValue));
+                return;
+# else
+                TMPL_MEM_TYPE const uRet = *(TMPL_MEM_TYPE const *)&pTlbe->pbMappingR3[GCPtrMem & GUEST_PAGE_OFFSET_MASK];
+                LogEx(LOG_GROUP_IEM_MEM,("IEM RD " TMPL_MEM_FMT_DESC " %RGv: " TMPL_MEM_FMT_TYPE "\n", GCPtrMem, uRet));
+                return uRet;
+# endif
+            }
+        }
+    }
+
+    /* Fall back on the slow careful approach in case of TLB miss, MMIO, exception
+       outdated page pointer, or other troubles.  (This will do a TLB load.) */
+    LogEx(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrMem));
+#endif
+#ifdef TMPL_MEM_BY_REF
+    RT_CONCAT3(iemMemFetchData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, pValue, UINT8_MAX, GCPtrMem);
+#else
+    return RT_CONCAT3(iemMemFetchData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, UINT8_MAX, GCPtrMem);
+#endif
+}
+
+
+/*********************************************************************************************************************************
+*   Stores                                                                                                                       *
+*********************************************************************************************************************************/
+#ifndef TMPL_MEM_NO_STORE
+
+/**
+ * Inlined store function that longjumps on error.
+ *
+ * @note The @a iSegRef is not allowed to be UINT8_MAX!
+ */
+DECL_INLINE_THROW(void)
+RT_CONCAT3(iemMemStoreData,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem,
+# ifdef TMPL_MEM_BY_REF
+                                                 TMPL_MEM_TYPE const *pValue) IEM_NOEXCEPT_MAY_LONGJMP
+# else
+                                                 TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
+# endif
+{
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+    /*
+     * Convert from segmented to flat address and check that it doesn't cross a page boundrary.
+     */
+    RTGCPTR GCPtrEff = iemMemApplySegmentToWriteJmp(pVCpu, iSegReg, sizeof(TMPL_MEM_TYPE), GCPtrMem);
+# if TMPL_MEM_TYPE_SIZE > 1
+    if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(GCPtrEff)))
+# endif
+    {
+        /*
+         * TLB lookup.
+         */
+        uint64_t const uTagNoRev = IEMTLB_CALC_TAG_NO_REV(GCPtrEff);
+        PCIEMTLBENTRY  pTlbe     = IEMTLB_TAG_TO_EVEN_ENTRY(&pVCpu->iem.s.DataTlb, uTagNoRev);
+        if (RT_LIKELY(   pTlbe->uTag               == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevision)
+                      || (pTlbe = pTlbe + 1)->uTag == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevisionGlobal)))
+        {
+            /*
+             * Check TLB page table level access flags.
+             */
+            AssertCompile(IEMTLBE_F_PT_NO_USER == 4);
+            uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER;
+            if (RT_LIKELY(   (pTlbe->fFlagsAndPhysRev & (  IEMTLBE_F_PHYS_REV       | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE
+                                                         | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY   | IEMTLBE_F_PT_NO_WRITE
+                                                         | IEMTLBE_F_NO_MAPPINGR3   | fNoUser))
+                          == pVCpu->iem.s.DataTlb.uTlbPhysRev))
+            {
+                /*
+                 * Store the value and return.
+                 */
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
+                Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
+                Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
+#  ifdef TMPL_MEM_BY_REF
+                *(TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrEff & GUEST_PAGE_OFFSET_MASK] = *pValue;
+                Log5Ex(LOG_GROUP_IEM_MEM,("IEM WR " TMPL_MEM_FMT_DESC " %d|%RGv=%RGv: %." RT_XSTR(TMPL_MEM_TYPE_SIZE) "Rhxs (%04x:%RX64)\n",
+                                          iSegReg, GCPtrMem, GCPtrEff, pValue, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
+#  else
+                *(TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrEff & GUEST_PAGE_OFFSET_MASK] = uValue;
+                Log5Ex(LOG_GROUP_IEM_MEM,("IEM WR " TMPL_MEM_FMT_DESC " %d|%RGv=%RGv: " TMPL_MEM_FMT_TYPE " (%04x:%RX64)\n",
+                                          iSegReg, GCPtrMem, GCPtrEff, uValue, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
+#  endif
+                return;
+            }
+        }
+    }
+
+    /* Fall back on the slow careful approach in case of TLB miss, MMIO, exception
+       outdated page pointer, or other troubles.  (This will do a TLB load.) */
+    Log6Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %u:%RGv falling back\n", LOG_FN_NAME, iSegReg, GCPtrMem));
+# endif
+# ifdef TMPL_MEM_BY_REF
+    RT_CONCAT3(iemMemStoreData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, iSegReg, GCPtrMem, pValue);
+# else
+    RT_CONCAT3(iemMemStoreData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, iSegReg, GCPtrMem, uValue);
+# endif
+}
+
+
+/**
+ * Inlined flat addressing store function that longjumps on error.
+ */
+DECL_INLINE_THROW(void)
+RT_CONCAT3(iemMemFlatStoreData,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, RTGCPTR GCPtrMem,
+# ifdef TMPL_MEM_BY_REF
+                                                    TMPL_MEM_TYPE const *pValue) IEM_NOEXCEPT_MAY_LONGJMP
+# else
+                                                    TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 # endif
 {
@@ -195,82 +344,4 @@
             AssertCompile(IEMTLBE_F_PT_NO_USER == 4);
             uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER;
-            if (RT_LIKELY(   (pTlbe->fFlagsAndPhysRev & (  IEMTLBE_F_PHYS_REV       | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_READ
-                                                         | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_NO_MAPPINGR3  | fNoUser))
-                          == pVCpu->iem.s.DataTlb.uTlbPhysRev))
-            {
-                /*
-                 * Fetch and return the dword
-                 */
-#  ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#  endif
-                Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
-                Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
-#  ifdef TMPL_MEM_BY_REF
-                *pValue = *(TMPL_MEM_TYPE const *)&pTlbe->pbMappingR3[GCPtrMem & GUEST_PAGE_OFFSET_MASK];
-                LogEx(LOG_GROUP_IEM_MEM,("IEM RD " TMPL_MEM_FMT_DESC " %RGv: %." RT_XSTR(TMPL_MEM_TYPE_SIZE) "Rhxs\n",
-                                         GCPtrMem, pValue));
-                return;
-#  else
-                TMPL_MEM_TYPE const uRet = *(TMPL_MEM_TYPE const *)&pTlbe->pbMappingR3[GCPtrMem & GUEST_PAGE_OFFSET_MASK];
-                LogEx(LOG_GROUP_IEM_MEM,("IEM RD " TMPL_MEM_FMT_DESC " %RGv: " TMPL_MEM_FMT_TYPE "\n", GCPtrMem, uRet));
-                return uRet;
-#  endif
-            }
-        }
-    }
-
-    /* Fall back on the slow careful approach in case of TLB miss, MMIO, exception
-       outdated page pointer, or other troubles.  (This will do a TLB load.) */
-    LogEx(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrMem));
-# endif
-# ifdef TMPL_MEM_BY_REF
-    RT_CONCAT3(iemMemFetchData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, pValue, UINT8_MAX, GCPtrMem);
-# else
-    return RT_CONCAT3(iemMemFetchData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, UINT8_MAX, GCPtrMem);
-# endif
-}
-
-
-/*********************************************************************************************************************************
-*   Stores                                                                                                                       *
-*********************************************************************************************************************************/
-# ifndef TMPL_MEM_NO_STORE
-
-/**
- * Inlined store function that longjumps on error.
- *
- * @note The @a iSegRef is not allowed to be UINT8_MAX!
- */
-DECL_INLINE_THROW(void)
-RT_CONCAT3(iemMemStoreData,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem,
-#  ifdef TMPL_MEM_BY_REF
-                                                 TMPL_MEM_TYPE const *pValue) IEM_NOEXCEPT_MAY_LONGJMP
-#  else
-                                                 TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
-#  endif
-{
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
-    /*
-     * Convert from segmented to flat address and check that it doesn't cross a page boundrary.
-     */
-    RTGCPTR GCPtrEff = iemMemApplySegmentToWriteJmp(pVCpu, iSegReg, sizeof(TMPL_MEM_TYPE), GCPtrMem);
-#  if TMPL_MEM_TYPE_SIZE > 1
-    if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(GCPtrEff)))
-#  endif
-    {
-        /*
-         * TLB lookup.
-         */
-        uint64_t const uTagNoRev = IEMTLB_CALC_TAG_NO_REV(GCPtrEff);
-        PCIEMTLBENTRY  pTlbe     = IEMTLB_TAG_TO_EVEN_ENTRY(&pVCpu->iem.s.DataTlb, uTagNoRev);
-        if (RT_LIKELY(   pTlbe->uTag               == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevision)
-                      || (pTlbe = pTlbe + 1)->uTag == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevisionGlobal)))
-        {
-            /*
-             * Check TLB page table level access flags.
-             */
-            AssertCompile(IEMTLBE_F_PT_NO_USER == 4);
-            uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER;
             if (RT_LIKELY(   (pTlbe->fFlagsAndPhysRev & (  IEMTLBE_F_PHYS_REV       | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE
                                                          | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY   | IEMTLBE_F_PT_NO_WRITE
@@ -281,91 +352,17 @@
                  * Store the value and return.
                  */
-#   ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#   endif
-                Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
-                Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
-#   ifdef TMPL_MEM_BY_REF
-                *(TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrEff & GUEST_PAGE_OFFSET_MASK] = *pValue;
-                Log5Ex(LOG_GROUP_IEM_MEM,("IEM WR " TMPL_MEM_FMT_DESC " %d|%RGv=%RGv: %." RT_XSTR(TMPL_MEM_TYPE_SIZE) "Rhxs (%04x:%RX64)\n",
-                                          iSegReg, GCPtrMem, GCPtrEff, pValue, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
-#   else
-                *(TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrEff & GUEST_PAGE_OFFSET_MASK] = uValue;
-                Log5Ex(LOG_GROUP_IEM_MEM,("IEM WR " TMPL_MEM_FMT_DESC " %d|%RGv=%RGv: " TMPL_MEM_FMT_TYPE " (%04x:%RX64)\n",
-                                          iSegReg, GCPtrMem, GCPtrEff, uValue, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
-#   endif
-                return;
-            }
-        }
-    }
-
-    /* Fall back on the slow careful approach in case of TLB miss, MMIO, exception
-       outdated page pointer, or other troubles.  (This will do a TLB load.) */
-    Log6Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %u:%RGv falling back\n", LOG_FN_NAME, iSegReg, GCPtrMem));
-#  endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
+                Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
+                Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
 #  ifdef TMPL_MEM_BY_REF
-    RT_CONCAT3(iemMemStoreData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, iSegReg, GCPtrMem, pValue);
-#  else
-    RT_CONCAT3(iemMemStoreData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, iSegReg, GCPtrMem, uValue);
-#  endif
-}
-
-
-/**
- * Inlined flat addressing store function that longjumps on error.
- */
-DECL_INLINE_THROW(void)
-RT_CONCAT3(iemMemFlatStoreData,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, RTGCPTR GCPtrMem,
-#  ifdef TMPL_MEM_BY_REF
-                                                    TMPL_MEM_TYPE const *pValue) IEM_NOEXCEPT_MAY_LONGJMP
-#  else
-                                                    TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
-#  endif
-{
-    AssertMsg(   (pVCpu->iem.s.fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT
-              || (pVCpu->iem.s.fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT
-              || (pVCpu->iem.s.fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT, ("%#x\n", pVCpu->iem.s.fExec));
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
-    /*
-     * Check that it doesn't cross a page boundrary.
-     */
-#  if TMPL_MEM_TYPE_SIZE > 1
-    if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(GCPtrMem)))
-#  endif
-    {
-        /*
-         * TLB lookup.
-         */
-        uint64_t const uTagNoRev = IEMTLB_CALC_TAG_NO_REV(GCPtrMem);
-        PCIEMTLBENTRY  pTlbe     = IEMTLB_TAG_TO_EVEN_ENTRY(&pVCpu->iem.s.DataTlb, uTagNoRev);
-        if (RT_LIKELY(   pTlbe->uTag               == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevision)
-                      || (pTlbe = pTlbe + 1)->uTag == (uTagNoRev | pVCpu->iem.s.DataTlb.uTlbRevisionGlobal)))
-        {
-            /*
-             * Check TLB page table level access flags.
-             */
-            AssertCompile(IEMTLBE_F_PT_NO_USER == 4);
-            uint64_t const fNoUser = (IEM_GET_CPL(pVCpu) + 1) & IEMTLBE_F_PT_NO_USER;
-            if (RT_LIKELY(   (pTlbe->fFlagsAndPhysRev & (  IEMTLBE_F_PHYS_REV       | IEMTLBE_F_PG_UNASSIGNED | IEMTLBE_F_PG_NO_WRITE
-                                                         | IEMTLBE_F_PT_NO_ACCESSED | IEMTLBE_F_PT_NO_DIRTY   | IEMTLBE_F_PT_NO_WRITE
-                                                         | IEMTLBE_F_NO_MAPPINGR3   | fNoUser))
-                          == pVCpu->iem.s.DataTlb.uTlbPhysRev))
-            {
-                /*
-                 * Store the value and return.
-                 */
-#   ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#   endif
-                Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
-                Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
-#   ifdef TMPL_MEM_BY_REF
                 *(TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrMem & GUEST_PAGE_OFFSET_MASK] = *pValue;
                 Log5Ex(LOG_GROUP_IEM_MEM,("IEM WR " TMPL_MEM_FMT_DESC " %RGv: %." RT_XSTR(TMPL_MEM_TYPE_SIZE) "Rhxs\n",
                                           GCPtrMem, pValue));
-#   else
+#  else
                 *(TMPL_MEM_TYPE *)&pTlbe->pbMappingR3[GCPtrMem & GUEST_PAGE_OFFSET_MASK] = uValue;
                 Log5Ex(LOG_GROUP_IEM_MEM,("IEM WR " TMPL_MEM_FMT_DESC " %RGv: " TMPL_MEM_FMT_TYPE "\n", GCPtrMem, uValue));
-#   endif
+#  endif
                 return;
             }
@@ -376,13 +373,13 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log6Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrMem));
-#  endif
-#  ifdef TMPL_MEM_BY_REF
+# endif
+# ifdef TMPL_MEM_BY_REF
     RT_CONCAT3(iemMemStoreData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, UINT8_MAX, GCPtrMem, pValue);
-#  else
+# else
     RT_CONCAT3(iemMemStoreData,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, UINT8_MAX, GCPtrMem, uValue);
-#  endif
-}
-
-# endif /* !TMPL_MEM_NO_STORE */
+# endif
+}
+
+#endif /* !TMPL_MEM_NO_STORE */
 
 
@@ -390,5 +387,5 @@
 *   Mapping / Direct Memory Access                                                                                               *
 *********************************************************************************************************************************/
-# ifndef TMPL_MEM_NO_MAPPING
+#ifndef TMPL_MEM_NO_MAPPING
 
 /**
@@ -401,5 +398,5 @@
                                                  uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Convert from segmented to flat address and check that it doesn't cross a page boundrary.
@@ -432,7 +429,7 @@
                  * Return the address.
                  */
-#   ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#   endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -448,5 +445,5 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log8Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %u:%RGv falling back\n", LOG_FN_NAME, iSegReg, GCPtrMem));
-#  endif
+# endif
     return RT_CONCAT3(iemMemMapData,TMPL_MEM_FN_SUFF,RwSafeJmp)(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
 }
@@ -462,5 +459,5 @@
                                                      RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Check that the address doesn't cross a page boundrary.
@@ -492,7 +489,7 @@
                  * Return the address.
                  */
-#   ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#   endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -508,9 +505,9 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log8Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrMem));
-#  endif
+# endif
     return RT_CONCAT3(iemMemMapData,TMPL_MEM_FN_SUFF,RwSafeJmp)(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
 }
 
-#  ifdef TMPL_MEM_WITH_ATOMIC_MAPPING
+# ifdef TMPL_MEM_WITH_ATOMIC_MAPPING
 
 /**
@@ -528,7 +525,7 @@
      */
     RTGCPTR const GCPtrEff = iemMemApplySegmentToWriteJmp(pVCpu, iSegReg, sizeof(TMPL_MEM_TYPE), GCPtrMem);
-#  if TMPL_MEM_TYPE_SIZE > 1
+#   if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(!(GCPtrEff & TMPL_MEM_TYPE_ALIGN))) /* strictly aligned, otherwise do fall back which knows th details. */
-#  endif
+#   endif
     {
         /*
@@ -588,7 +585,7 @@
      * Check that the address doesn't cross a page boundrary.
      */
-#  if TMPL_MEM_TYPE_SIZE > 1
+#   if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(!(GCPtrMem & TMPL_MEM_TYPE_ALIGN))) /* strictly aligned, otherwise do fall back which knows th details. */
-#  endif
+#   endif
     {
         /*
@@ -634,5 +631,5 @@
 }
 
-#  endif /* TMPL_MEM_WITH_ATOMIC_MAPPING */
+# endif /* TMPL_MEM_WITH_ATOMIC_MAPPING */
 
 /**
@@ -643,5 +640,5 @@
                                                  uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Convert from segmented to flat address and check that it doesn't cross a page boundrary.
@@ -674,7 +671,7 @@
                  * Return the address.
                  */
-#   ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#   endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -690,5 +687,5 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log8Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %u:%RGv falling back\n", LOG_FN_NAME, iSegReg, GCPtrMem));
-#  endif
+# endif
     return RT_CONCAT3(iemMemMapData,TMPL_MEM_FN_SUFF,WoSafeJmp)(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
 }
@@ -702,5 +699,5 @@
                                                      RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Check that the address doesn't cross a page boundrary.
@@ -732,7 +729,7 @@
                  * Return the address.
                  */
-#   ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#   endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -748,5 +745,5 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log8Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrMem));
-#  endif
+# endif
     return RT_CONCAT3(iemMemMapData,TMPL_MEM_FN_SUFF,WoSafeJmp)(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
 }
@@ -760,5 +757,5 @@
                                                  uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Convert from segmented to flat address and check that it doesn't cross a page boundrary.
@@ -767,5 +764,5 @@
 #  if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(GCPtrEff)))
-#endif
+#  endif
     {
         /*
@@ -790,7 +787,7 @@
                  * Return the address.
                  */
-#   ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#   endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -806,5 +803,5 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log4Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %u:%RGv falling back\n", LOG_FN_NAME, iSegReg, GCPtrMem));
-#  endif
+# endif
     return RT_CONCAT3(iemMemMapData,TMPL_MEM_FN_SUFF,RoSafeJmp)(pVCpu, pbUnmapInfo, iSegReg, GCPtrMem);
 }
@@ -818,5 +815,5 @@
                                                      RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Check that the address doesn't cross a page boundrary.
@@ -863,9 +860,9 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log4Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrMem));
-#  endif
+# endif
     return RT_CONCAT3(iemMemMapData,TMPL_MEM_FN_SUFF,RoSafeJmp)(pVCpu, pbUnmapInfo, UINT8_MAX, GCPtrMem);
 }
 
-# endif /* !TMPL_MEM_NO_MAPPING */
+#endif /* !TMPL_MEM_NO_MAPPING */
 
 
@@ -873,12 +870,11 @@
 *   Stack Access                                                                                                                 *
 *********************************************************************************************************************************/
-# ifdef TMPL_MEM_WITH_STACK
-#  if TMPL_MEM_TYPE_SIZE > 8
-#   error "Stack not supported for this type size - please #undef TMPL_MEM_WITH_STACK"
-#  endif
-#  if TMPL_MEM_TYPE_SIZE > 1 && TMPL_MEM_TYPE_ALIGN + 1 < TMPL_MEM_TYPE_SIZE
-#   error "Stack not supported for this alignment size - please #undef TMPL_MEM_WITH_STACK"
-#  endif
-#  ifdef IEM_WITH_SETJMP
+#ifdef TMPL_MEM_WITH_STACK
+# if TMPL_MEM_TYPE_SIZE > 8
+#  error "Stack not supported for this type size - please #undef TMPL_MEM_WITH_STACK"
+# endif
+# if TMPL_MEM_TYPE_SIZE > 1 && TMPL_MEM_TYPE_ALIGN + 1 < TMPL_MEM_TYPE_SIZE
+#  error "Stack not supported for this alignment size - please #undef TMPL_MEM_WITH_STACK"
+# endif
 
 /**
@@ -888,12 +884,12 @@
 RT_CONCAT3(iemMemStoreStack,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#   if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Apply segmentation and check that the item doesn't cross a page boundrary.
      */
     RTGCPTR const GCPtrEff = iemMemApplySegmentToWriteJmp(pVCpu, X86_SREG_SS, sizeof(TMPL_MEM_TYPE), GCPtrMem);
-#    if TMPL_MEM_TYPE_SIZE > 1
+#  if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(GCPtrEff)))
-#    endif
+#  endif
     {
         /*
@@ -919,7 +915,7 @@
                  * Do the store and return.
                  */
-#   ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#   endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -934,10 +930,10 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log12Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrEff));
-#   endif
+# endif
     RT_CONCAT3(iemMemStoreStack,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, GCPtrMem, uValue);
 }
 
 
-#   ifdef TMPL_WITH_PUSH_SREG
+# ifdef TMPL_WITH_PUSH_SREG
 /**
  * Stack segment store function that longjmps on error.
@@ -950,5 +946,5 @@
                                                       TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#    if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Apply segmentation to the address and check that the item doesn't cross
@@ -956,8 +952,8 @@
      */
     RTGCPTR const GCPtrEff = iemMemApplySegmentToWriteJmp(pVCpu, X86_SREG_SS, sizeof(TMPL_MEM_TYPE), GCPtrMem);
-#     if TMPL_MEM_TYPE_SIZE > 1
+#   if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(   !(GCPtrEff & (sizeof(uint16_t) - 1U))
                   || TMPL_MEM_CHECK_UNALIGNED_WITHIN_PAGE_OK(pVCpu, GCPtrEff, uint16_t) ))
-#     endif
+#   endif
     {
         /*
@@ -983,7 +979,7 @@
                  * Do the push and return.
                  */
-#      ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#      endif
+#   ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#   endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -998,8 +994,8 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log12Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrEff));
-#     endif
+#  endif
     RT_CONCAT3(iemMemStoreStack,TMPL_MEM_FN_SUFF,SRegSafeJmp)(pVCpu, GCPtrMem, uValue);
 }
-#   endif /* TMPL_WITH_PUSH_SREG */
+# endif /* TMPL_WITH_PUSH_SREG */
 
 
@@ -1017,11 +1013,11 @@
                 && pVCpu->cpum.GstCtx.ss.u64Base == 0));
 
-#   if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Check that the item doesn't cross a page boundrary.
      */
-#    if TMPL_MEM_TYPE_SIZE > 1
+#  if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(GCPtrMem)))
-#    endif
+#  endif
     {
         /*
@@ -1047,7 +1043,7 @@
                  * Do the push and return.
                  */
-#    ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#    endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -1063,9 +1059,9 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log12Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrMem));
-#   endif
+# endif
     RT_CONCAT3(iemMemStoreStack,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, GCPtrMem, uValue);
 }
 
-#   ifdef TMPL_WITH_PUSH_SREG
+# ifdef TMPL_WITH_PUSH_SREG
 /**
  * Flat stack segment store function that longjmps on error.
@@ -1078,5 +1074,5 @@
                                                           TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#    if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Check that the item doesn't cross a page boundrary.
@@ -1107,7 +1103,7 @@
                  * Do the push and return.
                  */
-#     ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#     endif
+#   ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#   endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -1123,8 +1119,8 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log12Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrMem));
-#    endif
+#  endif
     RT_CONCAT3(iemMemStoreStack,TMPL_MEM_FN_SUFF,SRegSafeJmp)(pVCpu, GCPtrMem, uValue);
 }
-#   endif /* TMPL_WITH_PUSH_SREG */
+# endif /* TMPL_WITH_PUSH_SREG */
 
 
@@ -1135,5 +1131,5 @@
 RT_CONCAT3(iemMemFetchStack,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#   if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Apply segmentation to the address and check that the item doesn't cross
@@ -1141,7 +1137,7 @@
      */
     RTGCPTR const GCPtrEff = iemMemApplySegmentToWriteJmp(pVCpu, X86_SREG_SS, sizeof(TMPL_MEM_TYPE), GCPtrMem);
-#    if TMPL_MEM_TYPE_SIZE > 1
+#  if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(GCPtrEff)))
-#    endif
+#  endif
     {
         /*
@@ -1166,7 +1162,7 @@
                  * Do the pop.
                  */
-#   ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#   endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -1181,5 +1177,5 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log10Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrEff));
-#   endif
+# endif
     return RT_CONCAT3(iemMemFetchStack,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, GCPtrMem);
 }
@@ -1192,11 +1188,11 @@
 RT_CONCAT3(iemMemFlatFetchStack,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#   if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Check that the item doesn't cross a page boundrary.
      */
-#    if TMPL_MEM_TYPE_SIZE > 1
+#  if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(GCPtrMem)))
-#    endif
+#  endif
     {
         /*
@@ -1221,7 +1217,7 @@
                  * Do the pop.
                  */
-#    ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#    endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -1236,5 +1232,5 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log10Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrMem));
-#   endif
+# endif
     return RT_CONCAT3(iemMemFetchStack,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, GCPtrMem);
 }
@@ -1247,5 +1243,5 @@
 RT_CONCAT3(iemMemStackPush,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Decrement the stack pointer (prep), apply segmentation and check that
@@ -1281,7 +1277,7 @@
                  * Do the push and return.
                  */
-#   ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#   endif
+#  ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#  endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -1298,5 +1294,5 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log12Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrEff));
-#  endif
+# endif
     RT_CONCAT3(iemMemStackPush,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, uValue);
 }
@@ -1311,5 +1307,5 @@
     Assert(iGReg < 16);
 
-#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Increment the stack pointer (prep), apply segmentation and check that
@@ -1368,9 +1364,9 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log10Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrEff));
-#  endif
+# endif
     RT_CONCAT3(iemMemStackPopGReg,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, iGReg);
 }
 
-#   ifdef TMPL_WITH_PUSH_SREG
+# ifdef TMPL_WITH_PUSH_SREG
 /**
  * Stack segment push function that longjmps on error.
@@ -1382,5 +1378,5 @@
 RT_CONCAT3(iemMemStackPush,TMPL_MEM_FN_SUFF,SRegJmp)(PVMCPUCC pVCpu, TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#    if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /* See fallback for details on this weirdness: */
     bool const    fIsIntel = IEM_IS_GUEST_CPU_INTEL(pVCpu);
@@ -1394,10 +1390,10 @@
     RTGCPTR const GCPtrTop = iemRegGetRspForPush(pVCpu, sizeof(TMPL_MEM_TYPE), &uNewRsp);
     RTGCPTR const GCPtrEff = iemMemApplySegmentToWriteJmp(pVCpu, X86_SREG_SS, cbAccess, GCPtrTop);
-#     if TMPL_MEM_TYPE_SIZE > 1
+#   if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(   !(GCPtrEff & (cbAccess - 1U))
                   || (   cbAccess == sizeof(uint16_t)
                       ? TMPL_MEM_CHECK_UNALIGNED_WITHIN_PAGE_OK(pVCpu, GCPtrEff, uint16_t)
                       : TMPL_MEM_CHECK_UNALIGNED_WITHIN_PAGE_OK(pVCpu, GCPtrEff, TMPL_MEM_TYPE) ) ))
-#    endif
+#   endif
     {
         /*
@@ -1423,7 +1419,7 @@
                  * Do the push and return.
                  */
-#    ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#    endif
+#   ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#   endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -1458,10 +1454,10 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log12Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RGv falling back\n", LOG_FN_NAME, GCPtrEff));
-#    endif
+#  endif
     RT_CONCAT3(iemMemStackPush,TMPL_MEM_FN_SUFF,SRegSafeJmp)(pVCpu, uValue);
 }
-#   endif /* TMPL_WITH_PUSH_SREG */
-
-#   if TMPL_MEM_TYPE_SIZE != 8
+# endif /* TMPL_WITH_PUSH_SREG */
+
+# if TMPL_MEM_TYPE_SIZE != 8
 
 /**
@@ -1475,12 +1471,12 @@
            && pVCpu->cpum.GstCtx.ss.u32Limit == UINT32_MAX
            && pVCpu->cpum.GstCtx.ss.u64Base == 0);
-#    if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Calculate the new stack pointer and check that the item doesn't cross a page boundrary.
      */
     uint32_t const uNewEsp = pVCpu->cpum.GstCtx.esp - sizeof(TMPL_MEM_TYPE);
-#     if TMPL_MEM_TYPE_SIZE > 1
+#   if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(uNewEsp)))
-#     endif
+#   endif
     {
         /*
@@ -1506,7 +1502,7 @@
                  * Do the push and return.
                  */
-#     ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#     endif
+#   ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#   endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -1523,5 +1519,5 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log12Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RX32 falling back\n", LOG_FN_NAME, uNewEsp));
-#    endif
+#  endif
     RT_CONCAT3(iemMemStackPush,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, uValue);
 }
@@ -1535,12 +1531,12 @@
 {
     Assert(iGReg < 16);
-#    if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Calculate the new stack pointer and check that the item doesn't cross a page boundrary.
      */
     uint32_t const uOldEsp = pVCpu->cpum.GstCtx.esp;
-#     if TMPL_MEM_TYPE_SIZE > 1
+#   if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(uOldEsp)))
-#     endif
+#   endif
     {
         /*
@@ -1565,18 +1561,18 @@
                  * Do the pop and update the register values.
                  */
-#     ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#     endif
+#   ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#   endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
                 TMPL_MEM_TYPE const uValue = *(TMPL_MEM_TYPE const *)&pTlbe->pbMappingR3[uOldEsp & GUEST_PAGE_OFFSET_MASK];
                 pVCpu->cpum.GstCtx.rsp = uOldEsp + sizeof(TMPL_MEM_TYPE); /* must be first for 16-bit */
-#     if TMPL_MEM_TYPE_SIZE == 2
+#   if TMPL_MEM_TYPE_SIZE == 2
                 pVCpu->cpum.GstCtx.aGRegs[iGReg].u16 = uValue;
-#     elif TMPL_MEM_TYPE_SIZE == 4
+#   elif TMPL_MEM_TYPE_SIZE == 4
                 pVCpu->cpum.GstCtx.aGRegs[iGReg].u   = uValue;
-#     else
-#      error "TMPL_MEM_TYPE_SIZE"
-#     endif
+#   else
+#    error "TMPL_MEM_TYPE_SIZE"
+#   endif
                 Log9Ex(LOG_GROUP_IEM_MEM,("IEM RD " TMPL_MEM_FMT_DESC " SS|%RX32 (->%RX32): " TMPL_MEM_FMT_TYPE " (r%u)\n",
                                           uOldEsp, uOldEsp + sizeof(TMPL_MEM_TYPE), uValue, iGReg));
@@ -1589,11 +1585,11 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log10Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RX32 falling back\n", LOG_FN_NAME, uOldEsp));
-#    endif
+#  endif
     RT_CONCAT3(iemMemStackPopGReg,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, iGReg);
 }
 
-#   endif /* TMPL_MEM_TYPE_SIZE != 8*/
-
-#   ifdef TMPL_WITH_PUSH_SREG
+# endif /* TMPL_MEM_TYPE_SIZE != 8*/
+
+# ifdef TMPL_WITH_PUSH_SREG
 /**
  * 32-bit flat stack segment push function that longjmps on error.
@@ -1605,5 +1601,5 @@
 RT_CONCAT3(iemMemFlat32StackPush,TMPL_MEM_FN_SUFF,SRegJmp)(PVMCPUCC pVCpu, TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#    if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /* See fallback for details on this weirdness: */
     bool const    fIsIntel = IEM_IS_GUEST_CPU_INTEL(pVCpu);
@@ -1641,7 +1637,7 @@
                  * Do the push and return.
                  */
-#     ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#     endif
+#   ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#   endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -1676,10 +1672,10 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log12Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RX32 falling back\n", LOG_FN_NAME, uNewEsp));
-#    endif
+#  endif
     RT_CONCAT3(iemMemStackPush,TMPL_MEM_FN_SUFF,SRegSafeJmp)(pVCpu, uValue);
 }
-#   endif /* TMPL_WITH_PUSH_SREG */
-
-#   if TMPL_MEM_TYPE_SIZE != 4
+# endif /* TMPL_WITH_PUSH_SREG */
+
+# if TMPL_MEM_TYPE_SIZE != 4
 
 /**
@@ -1689,12 +1685,12 @@
 RT_CONCAT3(iemMemFlat64StackPush,TMPL_MEM_FN_SUFF,Jmp)(PVMCPUCC pVCpu, TMPL_MEM_TYPE uValue) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#    if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Calculate the new stack pointer and check that the item doesn't cross a page boundrary.
      */
     uint64_t const uNewRsp = pVCpu->cpum.GstCtx.rsp - sizeof(TMPL_MEM_TYPE);
-#     if TMPL_MEM_TYPE_SIZE > 1
+#   if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(uNewRsp)))
-#     endif
+#   endif
     {
         /*
@@ -1720,7 +1716,7 @@
                  * Do the push and return.
                  */
-#     ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#     endif
+#   ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#   endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
@@ -1737,5 +1733,5 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log12Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RX64 falling back\n", LOG_FN_NAME, uNewRsp));
-#    endif
+#  endif
     RT_CONCAT3(iemMemStackPush,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, uValue);
 }
@@ -1749,12 +1745,12 @@
 {
     Assert(iGReg < 16);
-#    if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
+#  if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3) && !defined(TMPL_MEM_NO_INLINE)
     /*
      * Calculate the new stack pointer and check that the item doesn't cross a page boundrary.
      */
     uint64_t const uOldRsp = pVCpu->cpum.GstCtx.rsp;
-#     if TMPL_MEM_TYPE_SIZE > 1
+#   if TMPL_MEM_TYPE_SIZE > 1
     if (RT_LIKELY(TMPL_MEM_ALIGN_CHECK(uOldRsp)))
-#     endif
+#   endif
     {
         /*
@@ -1779,18 +1775,18 @@
                  * Do the push and return.
                  */
-#     ifdef IEM_WITH_TLB_STATISTICS
-                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
-#     endif
+#   ifdef IEM_WITH_TLB_STATISTICS
+                pVCpu->iem.s.DataTlb.cTlbInlineCodeHits++;
+#   endif
                 Assert(pTlbe->pbMappingR3); /* (Only ever cleared by the owning EMT.) */
                 Assert(!((uintptr_t)pTlbe->pbMappingR3 & GUEST_PAGE_OFFSET_MASK));
                 TMPL_MEM_TYPE const uValue = *(TMPL_MEM_TYPE const *)&pTlbe->pbMappingR3[uOldRsp & GUEST_PAGE_OFFSET_MASK];
                 pVCpu->cpum.GstCtx.rsp = uOldRsp + sizeof(TMPL_MEM_TYPE);  /* must be first for 16-bit */
-#     if TMPL_MEM_TYPE_SIZE == 2
+#   if TMPL_MEM_TYPE_SIZE == 2
                 pVCpu->cpum.GstCtx.aGRegs[iGReg].u16 = uValue;
-#     elif TMPL_MEM_TYPE_SIZE == 8
+#   elif TMPL_MEM_TYPE_SIZE == 8
                 pVCpu->cpum.GstCtx.aGRegs[iGReg].u   = uValue;
-#     else
-#      error "TMPL_MEM_TYPE_SIZE"
-#     endif
+#   else
+#    error "TMPL_MEM_TYPE_SIZE"
+#   endif
                 Log9Ex(LOG_GROUP_IEM_MEM,("IEM RD " TMPL_MEM_FMT_DESC " SS|%RX64 (->%RX64): " TMPL_MEM_FMT_TYPE " (r%u)\n",
                                           uOldRsp, uOldRsp + sizeof(TMPL_MEM_TYPE), uValue, iGReg));
@@ -1803,15 +1799,12 @@
        outdated page pointer, or other troubles.  (This will do a TLB load.) */
     Log10Ex(LOG_GROUP_IEM_MEM,(LOG_FN_FMT ": %RX64 falling back\n", LOG_FN_NAME, uOldRsp));
-#   endif
+#  endif
     RT_CONCAT3(iemMemStackPopGReg,TMPL_MEM_FN_SUFF,SafeJmp)(pVCpu, iGReg);
 }
 
-#   endif /* TMPL_MEM_TYPE_SIZE != 4 */
-
-#  endif /* IEM_WITH_SETJMP */
-# endif /* TMPL_MEM_WITH_STACK */
-
-
-#endif /* IEM_WITH_SETJMP */
+# endif /* TMPL_MEM_TYPE_SIZE != 4 */
+
+#endif /* TMPL_MEM_WITH_STACK */
+
 
 #undef TMPL_MEM_TYPE
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veRecompFuncs-x86.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veRecompFuncs-x86.h	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veRecompFuncs-x86.h	(revision 108278)
@@ -77,8 +77,4 @@
 #ifndef IEM_WITH_DATA_TLB
 # error The data TLB must be enabled for the recompiler.
-#endif
-
-#ifndef IEM_WITH_SETJMP
-# error The setjmp approach must be enabled for the recompiler.
 #endif
 
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllOpHlp-x86.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllOpHlp-x86.cpp	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllOpHlp-x86.cpp	(revision 108278)
@@ -59,301 +59,4 @@
  * Meant to be used via IEM_MC_CALC_RM_EFF_ADDR.
  *
- * @return  Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   bRm                 The ModRM byte.
- * @param   cbImmAndRspOffset   - First byte: The size of any immediate
- *                                following the effective address opcode bytes
- *                                (only for RIP relative addressing).
- *                              - Second byte: RSP displacement (for POP [ESP]).
- * @param   pGCPtrEff           Where to return the effective address.
- */
-VBOXSTRICTRC iemOpHlpCalcRmEffAddr(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, PRTGCPTR pGCPtrEff) RT_NOEXCEPT
-{
-    Log5(("iemOpHlpCalcRmEffAddr: bRm=%#x\n", bRm));
-# define SET_SS_DEF() \
-    do \
-    { \
-        if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SEG_MASK)) \
-            pVCpu->iem.s.iEffSeg = X86_SREG_SS; \
-    } while (0)
-
-    if (!IEM_IS_64BIT_CODE(pVCpu))
-    {
-/** @todo Check the effective address size crap! */
-        if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
-        {
-            uint16_t u16EffAddr;
-
-            /* Handle the disp16 form with no registers first. */
-            if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
-                IEM_OPCODE_GET_NEXT_U16(&u16EffAddr);
-            else
-            {
-                /* Get the displacment. */
-                switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-                {
-                    case 0:  u16EffAddr = 0;                             break;
-                    case 1:  IEM_OPCODE_GET_NEXT_S8_SX_U16(&u16EffAddr); break;
-                    case 2:  IEM_OPCODE_GET_NEXT_U16(&u16EffAddr);       break;
-                    default: AssertFailedReturn(VERR_IEM_IPE_1); /* (caller checked for these) */
-                }
-
-                /* Add the base and index registers to the disp. */
-                switch (bRm & X86_MODRM_RM_MASK)
-                {
-                    case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
-                    case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
-                    case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; SET_SS_DEF(); break;
-                    case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; SET_SS_DEF(); break;
-                    case 4: u16EffAddr += pVCpu->cpum.GstCtx.si;            break;
-                    case 5: u16EffAddr += pVCpu->cpum.GstCtx.di;            break;
-                    case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp;            SET_SS_DEF(); break;
-                    case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx;            break;
-                }
-            }
-
-            *pGCPtrEff = u16EffAddr;
-        }
-        else
-        {
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            uint32_t u32EffAddr;
-
-            /* Handle the disp32 form with no registers first. */
-            if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
-                IEM_OPCODE_GET_NEXT_U32(&u32EffAddr);
-            else
-            {
-                /* Get the register (or SIB) value. */
-                switch ((bRm & X86_MODRM_RM_MASK))
-                {
-                    case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
-                    case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
-                    case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
-                    case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
-                    case 4: /* SIB */
-                    {
-                        uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
-
-                        /* Get the index and scale it. */
-                        switch ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
-                        {
-                            case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
-                            case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
-                            case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
-                            case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
-                            case 4: u32EffAddr = 0; /*none */ break;
-                            case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
-                            case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
-                            case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
-                            IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                        }
-                        u32EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
-
-                        /* add base */
-                        switch (bSib & X86_SIB_BASE_MASK)
-                        {
-                            case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
-                            case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
-                            case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
-                            case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
-                            case 4: u32EffAddr += pVCpu->cpum.GstCtx.esp + (cbImmAndRspOffset >> 8); SET_SS_DEF(); break;
-                            case 5:
-                                if ((bRm & X86_MODRM_MOD_MASK) != 0)
-                                {
-                                    u32EffAddr += pVCpu->cpum.GstCtx.ebp;
-                                    SET_SS_DEF();
-                                }
-                                else
-                                {
-                                    uint32_t u32Disp;
-                                    IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                                    u32EffAddr += u32Disp;
-                                }
-                                break;
-                            case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
-                            case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
-                            IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                        }
-                        break;
-                    }
-                    case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; SET_SS_DEF(); break;
-                    case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
-                    case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
-                    IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                }
-
-                /* Get and add the displacement. */
-                switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-                {
-                    case 0:
-                        break;
-                    case 1:
-                    {
-                        int8_t i8Disp; IEM_OPCODE_GET_NEXT_S8(&i8Disp);
-                        u32EffAddr += i8Disp;
-                        break;
-                    }
-                    case 2:
-                    {
-                        uint32_t u32Disp; IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                        u32EffAddr += u32Disp;
-                        break;
-                    }
-                    default:
-                        AssertFailedReturn(VERR_IEM_IPE_2); /* (caller checked for these) */
-                }
-
-            }
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            *pGCPtrEff = u32EffAddr;
-        }
-    }
-    else
-    {
-        uint64_t u64EffAddr;
-
-        /* Handle the rip+disp32 form with no registers first. */
-        if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
-        {
-            IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64EffAddr);
-            u64EffAddr += pVCpu->cpum.GstCtx.rip + IEM_GET_INSTR_LEN(pVCpu) + (cbImmAndRspOffset & UINT32_C(0xff));
-        }
-        else
-        {
-            /* Get the register (or SIB) value. */
-            switch ((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB)
-            {
-                case  0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
-                case  1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
-                case  2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
-                case  3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
-                case  5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; SET_SS_DEF(); break;
-                case  6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
-                case  7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
-                case  8: u64EffAddr = pVCpu->cpum.GstCtx.r8;  break;
-                case  9: u64EffAddr = pVCpu->cpum.GstCtx.r9;  break;
-                case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
-                case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
-                case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
-                case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
-                case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
-                /* SIB */
-                case 4:
-                case 12:
-                {
-                    uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
-
-                    /* Get the index and scale it. */
-                    switch (((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex)
-                    {
-                        case  0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
-                        case  1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
-                        case  2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
-                        case  3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
-                        case  4: u64EffAddr = 0; /*none */ break;
-                        case  5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
-                        case  6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
-                        case  7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
-                        case  8: u64EffAddr = pVCpu->cpum.GstCtx.r8;  break;
-                        case  9: u64EffAddr = pVCpu->cpum.GstCtx.r9;  break;
-                        case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
-                        case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
-                        case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
-                        case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
-                        case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
-                        case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
-                        IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                    }
-                    u64EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
-
-                    /* add base */
-                    switch ((bSib & X86_SIB_BASE_MASK) | pVCpu->iem.s.uRexB)
-                    {
-                        case  0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
-                        case  1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
-                        case  2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
-                        case  3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
-                        case  4: u64EffAddr += pVCpu->cpum.GstCtx.rsp + (cbImmAndRspOffset >> 8); SET_SS_DEF(); break;
-                        case  6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
-                        case  7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
-                        case  8: u64EffAddr += pVCpu->cpum.GstCtx.r8;  break;
-                        case  9: u64EffAddr += pVCpu->cpum.GstCtx.r9;  break;
-                        case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
-                        case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
-                        case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
-                        case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
-                        case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
-                        /* complicated encodings */
-                        case 5:
-                        case 13:
-                            if ((bRm & X86_MODRM_MOD_MASK) != 0)
-                            {
-                                if (!pVCpu->iem.s.uRexB)
-                                {
-                                    u64EffAddr += pVCpu->cpum.GstCtx.rbp;
-                                    SET_SS_DEF();
-                                }
-                                else
-                                    u64EffAddr += pVCpu->cpum.GstCtx.r13;
-                            }
-                            else
-                            {
-                                uint32_t u32Disp;
-                                IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                                u64EffAddr += (int32_t)u32Disp;
-                            }
-                            break;
-                        IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                    }
-                    break;
-                }
-                IEM_NOT_REACHED_DEFAULT_CASE_RET();
-            }
-
-            /* Get and add the displacement. */
-            switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-            {
-                case 0:
-                    break;
-                case 1:
-                {
-                    int8_t i8Disp;
-                    IEM_OPCODE_GET_NEXT_S8(&i8Disp);
-                    u64EffAddr += i8Disp;
-                    break;
-                }
-                case 2:
-                {
-                    uint32_t u32Disp;
-                    IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                    u64EffAddr += (int32_t)u32Disp;
-                    break;
-                }
-                IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* (caller checked for these) */
-            }
-
-        }
-
-        if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
-            *pGCPtrEff = u64EffAddr;
-        else
-        {
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            *pGCPtrEff = u64EffAddr & UINT32_MAX;
-        }
-    }
-
-    Log5(("iemOpHlpCalcRmEffAddr: EffAddr=%#010RGv\n", *pGCPtrEff));
-    return VINF_SUCCESS;
-}
-
-
-#ifdef IEM_WITH_SETJMP
-/**
- * Calculates the effective address of a ModR/M memory operand.
- *
- * Meant to be used via IEM_MC_CALC_RM_EFF_ADDR.
- *
  * May longjmp on internal error.
  *
@@ -369,5 +72,5 @@
 {
     Log5(("iemOpHlpCalcRmEffAddrJmp: bRm=%#x\n", bRm));
-# define SET_SS_DEF() \
+#define SET_SS_DEF() \
     do \
     { \
@@ -642,324 +345,4 @@
     return u64EffAddr & UINT32_MAX;
 }
-#endif /* IEM_WITH_SETJMP */
-
-
-/**
- * Calculates the effective address of a ModR/M memory operand, extended version
- * for use in the recompilers.
- *
- * Meant to be used via IEM_MC_CALC_RM_EFF_ADDR.
- *
- * @return  Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   bRm                 The ModRM byte.
- * @param   cbImmAndRspOffset   - First byte: The size of any immediate
- *                                following the effective address opcode bytes
- *                                (only for RIP relative addressing).
- *                              - Second byte: RSP displacement (for POP [ESP]).
- * @param   pGCPtrEff           Where to return the effective address.
- * @param   puInfo              Extra info: 32-bit displacement (bits 31:0) and
- *                              SIB byte (bits 39:32).
- */
-VBOXSTRICTRC iemOpHlpCalcRmEffAddrEx(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, PRTGCPTR pGCPtrEff, uint64_t *puInfo) RT_NOEXCEPT
-{
-    Log5(("iemOpHlpCalcRmEffAddr: bRm=%#x\n", bRm));
-# define SET_SS_DEF() \
-    do \
-    { \
-        if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SEG_MASK)) \
-            pVCpu->iem.s.iEffSeg = X86_SREG_SS; \
-    } while (0)
-
-    uint64_t uInfo;
-    if (!IEM_IS_64BIT_CODE(pVCpu))
-    {
-/** @todo Check the effective address size crap! */
-        if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_16BIT)
-        {
-            uint16_t u16EffAddr;
-
-            /* Handle the disp16 form with no registers first. */
-            if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 6)
-            {
-                IEM_OPCODE_GET_NEXT_U16(&u16EffAddr);
-                uInfo = u16EffAddr;
-            }
-            else
-            {
-                /* Get the displacment. */
-                switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-                {
-                    case 0:  u16EffAddr = 0;                             break;
-                    case 1:  IEM_OPCODE_GET_NEXT_S8_SX_U16(&u16EffAddr); break;
-                    case 2:  IEM_OPCODE_GET_NEXT_U16(&u16EffAddr);       break;
-                    default: AssertFailedReturn(VERR_IEM_IPE_1); /* (caller checked for these) */
-                }
-                uInfo = u16EffAddr;
-
-                /* Add the base and index registers to the disp. */
-                switch (bRm & X86_MODRM_RM_MASK)
-                {
-                    case 0: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.si; break;
-                    case 1: u16EffAddr += pVCpu->cpum.GstCtx.bx + pVCpu->cpum.GstCtx.di; break;
-                    case 2: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.si; SET_SS_DEF(); break;
-                    case 3: u16EffAddr += pVCpu->cpum.GstCtx.bp + pVCpu->cpum.GstCtx.di; SET_SS_DEF(); break;
-                    case 4: u16EffAddr += pVCpu->cpum.GstCtx.si;            break;
-                    case 5: u16EffAddr += pVCpu->cpum.GstCtx.di;            break;
-                    case 6: u16EffAddr += pVCpu->cpum.GstCtx.bp;            SET_SS_DEF(); break;
-                    case 7: u16EffAddr += pVCpu->cpum.GstCtx.bx;            break;
-                }
-            }
-
-            *pGCPtrEff = u16EffAddr;
-        }
-        else
-        {
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            uint32_t u32EffAddr;
-
-            /* Handle the disp32 form with no registers first. */
-            if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
-            {
-                IEM_OPCODE_GET_NEXT_U32(&u32EffAddr);
-                uInfo = u32EffAddr;
-            }
-            else
-            {
-                /* Get the register (or SIB) value. */
-                uInfo = 0;
-                switch ((bRm & X86_MODRM_RM_MASK))
-                {
-                    case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
-                    case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
-                    case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
-                    case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
-                    case 4: /* SIB */
-                    {
-                        uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
-                        uInfo = (uint64_t)bSib << 32;
-
-                        /* Get the index and scale it. */
-                        switch ((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK)
-                        {
-                            case 0: u32EffAddr = pVCpu->cpum.GstCtx.eax; break;
-                            case 1: u32EffAddr = pVCpu->cpum.GstCtx.ecx; break;
-                            case 2: u32EffAddr = pVCpu->cpum.GstCtx.edx; break;
-                            case 3: u32EffAddr = pVCpu->cpum.GstCtx.ebx; break;
-                            case 4: u32EffAddr = 0; /*none */ break;
-                            case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; break;
-                            case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
-                            case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
-                            IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                        }
-                        u32EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
-
-                        /* add base */
-                        switch (bSib & X86_SIB_BASE_MASK)
-                        {
-                            case 0: u32EffAddr += pVCpu->cpum.GstCtx.eax; break;
-                            case 1: u32EffAddr += pVCpu->cpum.GstCtx.ecx; break;
-                            case 2: u32EffAddr += pVCpu->cpum.GstCtx.edx; break;
-                            case 3: u32EffAddr += pVCpu->cpum.GstCtx.ebx; break;
-                            case 4: u32EffAddr += pVCpu->cpum.GstCtx.esp + (cbImmAndRspOffset >> 8); SET_SS_DEF(); break;
-                            case 5:
-                                if ((bRm & X86_MODRM_MOD_MASK) != 0)
-                                {
-                                    u32EffAddr += pVCpu->cpum.GstCtx.ebp;
-                                    SET_SS_DEF();
-                                }
-                                else
-                                {
-                                    uint32_t u32Disp;
-                                    IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                                    u32EffAddr += u32Disp;
-                                    uInfo      |= u32Disp;
-                                }
-                                break;
-                            case 6: u32EffAddr += pVCpu->cpum.GstCtx.esi; break;
-                            case 7: u32EffAddr += pVCpu->cpum.GstCtx.edi; break;
-                            IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                        }
-                        break;
-                    }
-                    case 5: u32EffAddr = pVCpu->cpum.GstCtx.ebp; SET_SS_DEF(); break;
-                    case 6: u32EffAddr = pVCpu->cpum.GstCtx.esi; break;
-                    case 7: u32EffAddr = pVCpu->cpum.GstCtx.edi; break;
-                    IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                }
-
-                /* Get and add the displacement. */
-                switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-                {
-                    case 0:
-                        break;
-                    case 1:
-                    {
-                        int8_t i8Disp; IEM_OPCODE_GET_NEXT_S8(&i8Disp);
-                        u32EffAddr += i8Disp;
-                        uInfo |= (uint32_t)(int32_t)i8Disp;
-                        break;
-                    }
-                    case 2:
-                    {
-                        uint32_t u32Disp; IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                        u32EffAddr += u32Disp;
-                        uInfo      |= (uint32_t)u32Disp;
-                        break;
-                    }
-                    default:
-                        AssertFailedReturn(VERR_IEM_IPE_2); /* (caller checked for these) */
-                }
-
-            }
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            *pGCPtrEff = u32EffAddr;
-        }
-    }
-    else
-    {
-        uint64_t u64EffAddr;
-
-        /* Handle the rip+disp32 form with no registers first. */
-        if ((bRm & (X86_MODRM_MOD_MASK | X86_MODRM_RM_MASK)) == 5)
-        {
-            IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64EffAddr);
-            uInfo = (uint32_t)u64EffAddr;
-            u64EffAddr += pVCpu->cpum.GstCtx.rip + IEM_GET_INSTR_LEN(pVCpu) + (cbImmAndRspOffset & UINT32_C(0xff));
-        }
-        else
-        {
-            /* Get the register (or SIB) value. */
-            uInfo = 0;
-            switch ((bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB)
-            {
-                case  0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
-                case  1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
-                case  2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
-                case  3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
-                case  5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; SET_SS_DEF(); break;
-                case  6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
-                case  7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
-                case  8: u64EffAddr = pVCpu->cpum.GstCtx.r8;  break;
-                case  9: u64EffAddr = pVCpu->cpum.GstCtx.r9;  break;
-                case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
-                case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
-                case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
-                case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
-                case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
-                /* SIB */
-                case 4:
-                case 12:
-                {
-                    uint8_t bSib; IEM_OPCODE_GET_NEXT_U8(&bSib);
-                    uInfo = (uint64_t)bSib << 32;
-
-                    /* Get the index and scale it. */
-                    switch (((bSib >> X86_SIB_INDEX_SHIFT) & X86_SIB_INDEX_SMASK) | pVCpu->iem.s.uRexIndex)
-                    {
-                        case  0: u64EffAddr = pVCpu->cpum.GstCtx.rax; break;
-                        case  1: u64EffAddr = pVCpu->cpum.GstCtx.rcx; break;
-                        case  2: u64EffAddr = pVCpu->cpum.GstCtx.rdx; break;
-                        case  3: u64EffAddr = pVCpu->cpum.GstCtx.rbx; break;
-                        case  4: u64EffAddr = 0; /*none */ break;
-                        case  5: u64EffAddr = pVCpu->cpum.GstCtx.rbp; break;
-                        case  6: u64EffAddr = pVCpu->cpum.GstCtx.rsi; break;
-                        case  7: u64EffAddr = pVCpu->cpum.GstCtx.rdi; break;
-                        case  8: u64EffAddr = pVCpu->cpum.GstCtx.r8;  break;
-                        case  9: u64EffAddr = pVCpu->cpum.GstCtx.r9;  break;
-                        case 10: u64EffAddr = pVCpu->cpum.GstCtx.r10; break;
-                        case 11: u64EffAddr = pVCpu->cpum.GstCtx.r11; break;
-                        case 12: u64EffAddr = pVCpu->cpum.GstCtx.r12; break;
-                        case 13: u64EffAddr = pVCpu->cpum.GstCtx.r13; break;
-                        case 14: u64EffAddr = pVCpu->cpum.GstCtx.r14; break;
-                        case 15: u64EffAddr = pVCpu->cpum.GstCtx.r15; break;
-                        IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                    }
-                    u64EffAddr <<= (bSib >> X86_SIB_SCALE_SHIFT) & X86_SIB_SCALE_SMASK;
-
-                    /* add base */
-                    switch ((bSib & X86_SIB_BASE_MASK) | pVCpu->iem.s.uRexB)
-                    {
-                        case  0: u64EffAddr += pVCpu->cpum.GstCtx.rax; break;
-                        case  1: u64EffAddr += pVCpu->cpum.GstCtx.rcx; break;
-                        case  2: u64EffAddr += pVCpu->cpum.GstCtx.rdx; break;
-                        case  3: u64EffAddr += pVCpu->cpum.GstCtx.rbx; break;
-                        case  4: u64EffAddr += pVCpu->cpum.GstCtx.rsp + (cbImmAndRspOffset >> 8); SET_SS_DEF(); break;
-                        case  6: u64EffAddr += pVCpu->cpum.GstCtx.rsi; break;
-                        case  7: u64EffAddr += pVCpu->cpum.GstCtx.rdi; break;
-                        case  8: u64EffAddr += pVCpu->cpum.GstCtx.r8;  break;
-                        case  9: u64EffAddr += pVCpu->cpum.GstCtx.r9;  break;
-                        case 10: u64EffAddr += pVCpu->cpum.GstCtx.r10; break;
-                        case 11: u64EffAddr += pVCpu->cpum.GstCtx.r11; break;
-                        case 12: u64EffAddr += pVCpu->cpum.GstCtx.r12; break;
-                        case 14: u64EffAddr += pVCpu->cpum.GstCtx.r14; break;
-                        case 15: u64EffAddr += pVCpu->cpum.GstCtx.r15; break;
-                        /* complicated encodings */
-                        case 5:
-                        case 13:
-                            if ((bRm & X86_MODRM_MOD_MASK) != 0)
-                            {
-                                if (!pVCpu->iem.s.uRexB)
-                                {
-                                    u64EffAddr += pVCpu->cpum.GstCtx.rbp;
-                                    SET_SS_DEF();
-                                }
-                                else
-                                    u64EffAddr += pVCpu->cpum.GstCtx.r13;
-                            }
-                            else
-                            {
-                                uint32_t u32Disp;
-                                IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                                u64EffAddr += (int32_t)u32Disp;
-                                uInfo      |= u32Disp;
-                            }
-                            break;
-                        IEM_NOT_REACHED_DEFAULT_CASE_RET();
-                    }
-                    break;
-                }
-                IEM_NOT_REACHED_DEFAULT_CASE_RET();
-            }
-
-            /* Get and add the displacement. */
-            switch ((bRm >> X86_MODRM_MOD_SHIFT) & X86_MODRM_MOD_SMASK)
-            {
-                case 0:
-                    break;
-                case 1:
-                {
-                    int8_t i8Disp;
-                    IEM_OPCODE_GET_NEXT_S8(&i8Disp);
-                    u64EffAddr += i8Disp;
-                    uInfo      |= (uint32_t)(int32_t)i8Disp;
-                    break;
-                }
-                case 2:
-                {
-                    uint32_t u32Disp;
-                    IEM_OPCODE_GET_NEXT_U32(&u32Disp);
-                    u64EffAddr += (int32_t)u32Disp;
-                    uInfo      |= u32Disp;
-                    break;
-                }
-                IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* (caller checked for these) */
-            }
-
-        }
-
-        if (pVCpu->iem.s.enmEffAddrMode == IEMMODE_64BIT)
-            *pGCPtrEff = u64EffAddr;
-        else
-        {
-            Assert(pVCpu->iem.s.enmEffAddrMode == IEMMODE_32BIT);
-            *pGCPtrEff = u64EffAddr & UINT32_MAX;
-        }
-    }
-    *puInfo = uInfo;
-
-    Log5(("iemOpHlpCalcRmEffAddrEx: EffAddr=%#010RGv uInfo=%RX64\n", *pGCPtrEff, uInfo));
-    return VINF_SUCCESS;
-}
 
 /** @}  */
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllOpcodeFetch-x86.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllOpcodeFetch-x86.cpp	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllOpcodeFetch-x86.cpp	(revision 108278)
@@ -736,29 +736,4 @@
 
 #endif /* !IEM_WITH_CODE_TLB */
-#ifndef IEM_WITH_SETJMP
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextU8 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the
- *                              calling thread.
- * @param   pb                  Where to return the opcode byte.
- */
-VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT
-{
-    VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 1);
-    if (rcStrict == VINF_SUCCESS)
-    {
-        uint8_t offOpcode = pVCpu->iem.s.offOpcode;
-        *pb = pVCpu->iem.s.abOpcode[offOpcode];
-        pVCpu->iem.s.offOpcode = offOpcode + 1;
-    }
-    else
-        *pb = 0;
-    return rcStrict;
-}
-
-#else  /* IEM_WITH_SETJMP */
 
 /**
@@ -770,101 +745,16 @@
 uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# ifdef IEM_WITH_CODE_TLB
+#ifdef IEM_WITH_CODE_TLB
     uint8_t u8;
     iemOpcodeFetchBytesJmp(pVCpu, sizeof(u8), &u8);
     return u8;
-# else
+#else
     VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 1);
     if (rcStrict == VINF_SUCCESS)
         return pVCpu->iem.s.abOpcode[pVCpu->iem.s.offOpcode++];
     IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(rcStrict));
-# endif
+#endif
 }
 
-#endif /* IEM_WITH_SETJMP */
-
-#ifndef IEM_WITH_SETJMP
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextS8SxU16 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu16                Where to return the opcode dword.
- */
-VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT
-{
-    uint8_t      u8;
-    VBOXSTRICTRC rcStrict = iemOpcodeGetNextU8Slow(pVCpu, &u8);
-    if (rcStrict == VINF_SUCCESS)
-        *pu16 = (int8_t)u8;
-    return rcStrict;
-}
-
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextS8SxU32 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu32                Where to return the opcode dword.
- */
-VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
-{
-    uint8_t      u8;
-    VBOXSTRICTRC rcStrict = iemOpcodeGetNextU8Slow(pVCpu, &u8);
-    if (rcStrict == VINF_SUCCESS)
-        *pu32 = (int8_t)u8;
-    return rcStrict;
-}
-
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextS8SxU64 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu64                Where to return the opcode qword.
- */
-VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
-{
-    uint8_t      u8;
-    VBOXSTRICTRC rcStrict = iemOpcodeGetNextU8Slow(pVCpu, &u8);
-    if (rcStrict == VINF_SUCCESS)
-        *pu64 = (int8_t)u8;
-    return rcStrict;
-}
-
-#endif /* !IEM_WITH_SETJMP */
-
-
-#ifndef IEM_WITH_SETJMP
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextU16 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu16                Where to return the opcode word.
- */
-VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT
-{
-    VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 2);
-    if (rcStrict == VINF_SUCCESS)
-    {
-        uint8_t offOpcode = pVCpu->iem.s.offOpcode;
-# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
-        *pu16 = *(uint16_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-# else
-        *pu16 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
-# endif
-        pVCpu->iem.s.offOpcode = offOpcode + 2;
-    }
-    else
-        *pu16 = 0;
-    return rcStrict;
-}
-
-#else  /* IEM_WITH_SETJMP */
 
 /**
@@ -876,9 +766,9 @@
 uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# ifdef IEM_WITH_CODE_TLB
+#ifdef IEM_WITH_CODE_TLB
     uint16_t u16;
     iemOpcodeFetchBytesJmp(pVCpu, sizeof(u16), &u16);
     return u16;
-# else
+#else
     VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 2);
     if (rcStrict == VINF_SUCCESS)
@@ -886,94 +776,14 @@
         uint8_t offOpcode = pVCpu->iem.s.offOpcode;
         pVCpu->iem.s.offOpcode += 2;
-#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
         return *(uint16_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-#  else
+# else
         return RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
-#  endif
+# endif
     }
     IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(rcStrict));
-# endif
+#endif
 }
 
-#endif /* IEM_WITH_SETJMP */
-
-#ifndef IEM_WITH_SETJMP
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextU16ZxU32 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu32                Where to return the opcode double word.
- */
-VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
-{
-    VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 2);
-    if (rcStrict == VINF_SUCCESS)
-    {
-        uint8_t offOpcode = pVCpu->iem.s.offOpcode;
-        *pu32 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
-        pVCpu->iem.s.offOpcode = offOpcode + 2;
-    }
-    else
-        *pu32 = 0;
-    return rcStrict;
-}
-
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextU16ZxU64 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu64                Where to return the opcode quad word.
- */
-VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
-{
-    VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 2);
-    if (rcStrict == VINF_SUCCESS)
-    {
-        uint8_t offOpcode = pVCpu->iem.s.offOpcode;
-        *pu64 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
-        pVCpu->iem.s.offOpcode = offOpcode + 2;
-    }
-    else
-        *pu64 = 0;
-    return rcStrict;
-}
-
-#endif /* !IEM_WITH_SETJMP */
-
-#ifndef IEM_WITH_SETJMP
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextU32 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu32                Where to return the opcode dword.
- */
-VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
-{
-    VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 4);
-    if (rcStrict == VINF_SUCCESS)
-    {
-        uint8_t offOpcode = pVCpu->iem.s.offOpcode;
-# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
-        *pu32 = *(uint32_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-# else
-        *pu32 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 1],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 2],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 3]);
-# endif
-        pVCpu->iem.s.offOpcode = offOpcode + 4;
-    }
-    else
-        *pu32 = 0;
-    return rcStrict;
-}
-
-#else  /* IEM_WITH_SETJMP */
 
 /**
@@ -985,9 +795,9 @@
 uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# ifdef IEM_WITH_CODE_TLB
+#ifdef IEM_WITH_CODE_TLB
     uint32_t u32;
     iemOpcodeFetchBytesJmp(pVCpu, sizeof(u32), &u32);
     return u32;
-# else
+#else
     VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 4);
     if (rcStrict == VINF_SUCCESS)
@@ -995,107 +805,17 @@
         uint8_t offOpcode = pVCpu->iem.s.offOpcode;
         pVCpu->iem.s.offOpcode = offOpcode + 4;
-#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
         return *(uint32_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-#  else
+# else
         return RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
                                    pVCpu->iem.s.abOpcode[offOpcode + 1],
                                    pVCpu->iem.s.abOpcode[offOpcode + 2],
                                    pVCpu->iem.s.abOpcode[offOpcode + 3]);
-#  endif
+# endif
     }
     IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(rcStrict));
-# endif
+#endif
 }
 
-#endif /* IEM_WITH_SETJMP */
-
-#ifndef IEM_WITH_SETJMP
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextU32ZxU64 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu64                Where to return the opcode dword.
- */
-VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
-{
-    VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 4);
-    if (rcStrict == VINF_SUCCESS)
-    {
-        uint8_t offOpcode = pVCpu->iem.s.offOpcode;
-        *pu64 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 1],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 2],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 3]);
-        pVCpu->iem.s.offOpcode = offOpcode + 4;
-    }
-    else
-        *pu64 = 0;
-    return rcStrict;
-}
-
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextS32SxU64 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu64                Where to return the opcode qword.
- */
-VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
-{
-    VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 4);
-    if (rcStrict == VINF_SUCCESS)
-    {
-        uint8_t offOpcode = pVCpu->iem.s.offOpcode;
-        *pu64 = (int32_t)RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
-                                             pVCpu->iem.s.abOpcode[offOpcode + 1],
-                                             pVCpu->iem.s.abOpcode[offOpcode + 2],
-                                             pVCpu->iem.s.abOpcode[offOpcode + 3]);
-        pVCpu->iem.s.offOpcode = offOpcode + 4;
-    }
-    else
-        *pu64 = 0;
-    return rcStrict;
-}
-
-#endif /* !IEM_WITH_SETJMP */
-
-#ifndef IEM_WITH_SETJMP
-
-/**
- * Deals with the problematic cases that iemOpcodeGetNextU64 doesn't like.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu64                Where to return the opcode qword.
- */
-VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
-{
-    VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 8);
-    if (rcStrict == VINF_SUCCESS)
-    {
-        uint8_t offOpcode = pVCpu->iem.s.offOpcode;
-# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
-        *pu64 = *(uint64_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-# else
-        *pu64 = RT_MAKE_U64_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 1],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 2],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 3],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 4],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 5],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 6],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 7]);
-# endif
-        pVCpu->iem.s.offOpcode = offOpcode + 8;
-    }
-    else
-        *pu64 = 0;
-    return rcStrict;
-}
-
-#else  /* IEM_WITH_SETJMP */
 
 /**
@@ -1107,9 +827,9 @@
 uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# ifdef IEM_WITH_CODE_TLB
+#ifdef IEM_WITH_CODE_TLB
     uint64_t u64;
     iemOpcodeFetchBytesJmp(pVCpu, sizeof(u64), &u64);
     return u64;
-# else
+#else
     VBOXSTRICTRC rcStrict = iemOpcodeFetchMoreBytes(pVCpu, 8);
     if (rcStrict == VINF_SUCCESS)
@@ -1117,7 +837,7 @@
         uint8_t offOpcode = pVCpu->iem.s.offOpcode;
         pVCpu->iem.s.offOpcode = offOpcode + 8;
-#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
         return *(uint64_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-#  else
+# else
         return RT_MAKE_U64_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
                                    pVCpu->iem.s.abOpcode[offOpcode + 1],
@@ -1128,10 +848,8 @@
                                    pVCpu->iem.s.abOpcode[offOpcode + 6],
                                    pVCpu->iem.s.abOpcode[offOpcode + 7]);
-#  endif
+# endif
     }
     IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(rcStrict));
-# endif
+#endif
 }
 
-#endif /* IEM_WITH_SETJMP */
-
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllThrdTables-x86.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllThrdTables-x86.h	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllThrdTables-x86.h	(revision 108278)
@@ -104,8 +104,4 @@
 #endif
 
-#ifndef IEM_WITH_SETJMP
-# error The setjmp approach must be enabled for the recompiler.
-#endif
-
 
 /*********************************************************************************************************************************
@@ -133,13 +129,7 @@
  */
 #undef IEM_MC_CALC_RM_EFF_ADDR
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
-    uint64_t uEffAddrInfo; \
-    IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddrJmpEx(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &(a_GCPtrEff), &uEffAddrInfo))
-#else
-# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
+#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
     uint64_t uEffAddrInfo; \
     ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmpEx(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &uEffAddrInfo))
-#endif
 
 /*
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllXcpt-x86.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllXcpt-x86.cpp	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllXcpt-x86.cpp	(revision 108278)
@@ -2601,5 +2601,4 @@
 }
 
-#ifdef IEM_WITH_SETJMP
 /**
  * See iemRaiseXcptOrInt.  Will not return.
@@ -2616,5 +2615,4 @@
     IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(rcStrict));
 }
-#endif
 
 
@@ -2635,5 +2633,4 @@
 
 
-#ifdef IEM_WITH_SETJMP
 /** \#DE - 00.  */
 DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
@@ -2641,5 +2638,4 @@
     iemRaiseXcptOrIntJmp(pVCpu, 0, X86_XCPT_DE, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
 }
-#endif
 
 
@@ -2668,5 +2664,4 @@
 
 
-#ifdef IEM_WITH_SETJMP
 /** \#UD - 06.  */
 DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
@@ -2674,5 +2669,4 @@
     iemRaiseXcptOrIntJmp(pVCpu, 0, X86_XCPT_UD, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
 }
-#endif
 
 
@@ -2684,5 +2678,4 @@
 
 
-#ifdef IEM_WITH_SETJMP
 /** \#NM - 07.  */
 DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
@@ -2690,5 +2683,4 @@
     iemRaiseXcptOrIntJmp(pVCpu, 0, X86_XCPT_NM, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0);
 }
-#endif
 
 
@@ -2775,5 +2767,5 @@
 }
 
-#ifdef IEM_WITH_SETJMP
+
 /** \#GP(0) - 0d.  */
 DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
@@ -2782,5 +2774,4 @@
     iemRaiseXcptOrIntJmp(pVCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0);
 }
-#endif
 
 
@@ -2813,5 +2804,5 @@
 }
 
-#ifdef IEM_WITH_SETJMP
+
 /** \#GP(sel) - 0d, longjmp.  */
 DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP
@@ -2823,5 +2814,5 @@
                          IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0);
 }
-#endif
+
 
 /** \#GP(sel) - 0d.  */
@@ -2834,5 +2825,5 @@
 }
 
-#ifdef IEM_WITH_SETJMP
+
 /** \#GP(sel) - 0d, longjmp.  */
 DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP
@@ -2843,5 +2834,4 @@
     iemRaiseXcptOrIntJmp(pVCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0);
 }
-#endif
 
 
@@ -2855,5 +2845,5 @@
 }
 
-#ifdef IEM_WITH_SETJMP
+
 /** \#GP(sel) - 0d, longjmp.  */
 DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP
@@ -2862,5 +2852,4 @@
     iemRaiseXcptOrIntJmp(pVCpu, 0, X86_XCPT_GP, IEM_XCPT_FLAGS_T_CPU_XCPT | IEM_XCPT_FLAGS_ERR, 0, 0);
 }
-#endif
 
 
@@ -2930,5 +2919,5 @@
 }
 
-#ifdef IEM_WITH_SETJMP
+
 /** \#PF(n) - 0e, longjmp.  */
 DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess,
@@ -2937,5 +2926,4 @@
     IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(iemRaisePageFault(pVCpu, GCPtrWhere, cbAccess, fAccess, rc)));
 }
-#endif
 
 
@@ -2951,5 +2939,5 @@
 }
 
-#ifdef IEM_WITH_SETJMP
+
 /** \#MF(0) - 10, longjmp.  */
 DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
@@ -2957,5 +2945,4 @@
     IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(iemRaiseMathFault(pVCpu)));
 }
-#endif
 
 
@@ -2966,5 +2953,5 @@
 }
 
-#ifdef IEM_WITH_SETJMP
+
 /** \#AC(0) - 11, longjmp.  */
 DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
@@ -2972,5 +2959,4 @@
     IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(iemRaiseAlignmentCheckException(pVCpu)));
 }
-#endif
 
 
@@ -2982,5 +2968,4 @@
 
 
-#ifdef IEM_WITH_SETJMP
 /** \#XF(0)/\#XM(0) - 19s, longjmp.  */
 DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
@@ -2988,5 +2973,4 @@
     IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(iemRaiseSimdFpException(pVCpu)));
 }
-#endif
 
 
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMInlineDecode-x86.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMInlineDecode-x86.h	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMInlineDecode-x86.h	(revision 108278)
@@ -36,54 +36,4 @@
 
 #ifndef IEM_WITH_OPAQUE_DECODER_STATE
-
-# ifndef IEM_WITH_SETJMP
-
-/**
- * Fetches the first opcode byte.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the
- *                              calling thread.
- * @param   pu8                 Where to return the opcode byte.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetFirstU8(PVMCPUCC pVCpu, uint8_t *pu8) RT_NOEXCEPT
-{
-    /*
-     * Check for hardware instruction breakpoints.
-     * Note! Guest breakpoints are only checked after POP SS or MOV SS on AMD CPUs.
-     */
-    if (RT_LIKELY(!(pVCpu->iem.s.fExec & IEM_F_PENDING_BRK_INSTR)))
-    { /* likely */ }
-    else
-    {
-        VBOXSTRICTRC rcStrict = DBGFBpCheckInstruction(pVCpu->CTX_SUFF(pVM), pVCpu,
-                                                       pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base,
-                                                          !(pVCpu->cpum.GstCtx.rflags.uBoth & CPUMCTX_INHIBIT_SHADOW_SS)
-                                                       || IEM_IS_GUEST_CPU_AMD(pVCpu));
-        if (RT_LIKELY(rcStrict == VINF_SUCCESS))
-        { /* likely */ }
-        else
-        {
-            *pu8 = 0xff; /* shut up gcc. sigh */
-            if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
-                return iemRaiseDebugException(pVCpu);
-            return rcStrict;
-        }
-    }
-
-    /*
-     * Fetch the first opcode byte.
-     */
-    uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
-    {
-        pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
-        *pu8 = pVCpu->iem.s.abOpcode[offOpcode];
-        return VINF_SUCCESS;
-    }
-    return iemOpcodeGetNextU8Slow(pVCpu, pu8);
-}
-
-# else  /* IEM_WITH_SETJMP */
 
 /**
@@ -120,5 +70,5 @@
      * Fetch the first opcode byte.
      */
-#  ifdef IEM_WITH_CODE_TLB
+# ifdef IEM_WITH_CODE_TLB
     uint8_t         bRet;
     uintptr_t       offBuf = pVCpu->iem.s.offInstrNextByte;
@@ -132,11 +82,11 @@
     else
         bRet = iemOpcodeGetNextU8SlowJmp(pVCpu);
-#   ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
+#  ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
     Assert(pVCpu->iem.s.offOpcode == 0);
     pVCpu->iem.s.abOpcode[pVCpu->iem.s.offOpcode++] = bRet;
-#   endif
+#  endif
     return bRet;
 
-#  else /* !IEM_WITH_CODE_TLB */
+# else /* !IEM_WITH_CODE_TLB */
     uintptr_t offOpcode = pVCpu->iem.s.offOpcode;
     if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
@@ -146,8 +96,6 @@
     }
     return iemOpcodeGetNextU8SlowJmp(pVCpu);
-#  endif
-}
-
-# endif /* IEM_WITH_SETJMP */
+# endif
+}
 
 /**
@@ -157,42 +105,6 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_FIRST_U8(a_pu8) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetFirstU8(pVCpu, (a_pu8)); \
-        if (rcStrict2 == VINF_SUCCESS) \
-        { /* likely */ } \
-        else \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_FIRST_U8(a_pu8) (*(a_pu8) = iemOpcodeGetFirstU8Jmp(pVCpu))
-# endif /* IEM_WITH_SETJMP */
-
-
-# ifndef IEM_WITH_SETJMP
-
-/**
- * Fetches the next opcode byte.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the
- *                              calling thread.
- * @param   pu8                 Where to return the opcode byte.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU8(PVMCPUCC pVCpu, uint8_t *pu8) RT_NOEXCEPT
-{
-    uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
-    {
-        pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
-        *pu8 = pVCpu->iem.s.abOpcode[offOpcode];
-        return VINF_SUCCESS;
-    }
-    return iemOpcodeGetNextU8Slow(pVCpu, pu8);
-}
-
-# else  /* IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_FIRST_U8(a_pu8) (*(a_pu8) = iemOpcodeGetFirstU8Jmp(pVCpu))
+
 
 /**
@@ -204,5 +116,5 @@
 DECL_INLINE_THROW(uint8_t) iemOpcodeGetNextU8Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  ifdef IEM_WITH_CODE_TLB
+# ifdef IEM_WITH_CODE_TLB
     uint8_t         bRet;
     uintptr_t       offBuf = pVCpu->iem.s.offInstrNextByte;
@@ -216,11 +128,11 @@
     else
         bRet = iemOpcodeGetNextU8SlowJmp(pVCpu);
-#   ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
+#  ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
     Assert(pVCpu->iem.s.offOpcode < sizeof(pVCpu->iem.s.abOpcode));
     pVCpu->iem.s.abOpcode[pVCpu->iem.s.offOpcode++] = bRet;
-#   endif
+#  endif
     return bRet;
 
-#  else /* !IEM_WITH_CODE_TLB */
+# else /* !IEM_WITH_CODE_TLB */
     uintptr_t offOpcode = pVCpu->iem.s.offOpcode;
     if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
@@ -230,8 +142,6 @@
     }
     return iemOpcodeGetNextU8SlowJmp(pVCpu);
-#  endif
-}
-
-# endif /* IEM_WITH_SETJMP */
+# endif
+}
 
 /**
@@ -241,33 +151,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_U8(a_pu8) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU8(pVCpu, (a_pu8)); \
-        if (rcStrict2 == VINF_SUCCESS) \
-        { /* likely */ } \
-        else \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_U8(a_pu8) (*(a_pu8) = iemOpcodeGetNextU8Jmp(pVCpu))
-# endif /* IEM_WITH_SETJMP */
-
-
-# ifndef IEM_WITH_SETJMP
-/**
- * Fetches the next signed byte from the opcode stream.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pi8                 Where to return the signed byte.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8(PVMCPUCC pVCpu, int8_t *pi8) RT_NOEXCEPT
-{
-    return iemOpcodeGetNextU8(pVCpu, (uint8_t *)pi8);
-}
-# endif /* !IEM_WITH_SETJMP */
-
+# define IEM_OPCODE_GET_NEXT_U8(a_pu8) (*(a_pu8) = iemOpcodeGetNextU8Jmp(pVCpu))
 
 /**
@@ -278,38 +160,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_S8(a_pi8) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8(pVCpu, (a_pi8)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else /* IEM_WITH_SETJMP */
-#  define IEM_OPCODE_GET_NEXT_S8(a_pi8) (*(a_pi8) = (int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
-
-# endif /* IEM_WITH_SETJMP */
-
-
-# ifndef IEM_WITH_SETJMP
-/**
- * Fetches the next signed byte from the opcode stream, extending it to
- * unsigned 16-bit.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu16                Where to return the unsigned word.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU16(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT
-{
-    uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_UNLIKELY(offOpcode >= pVCpu->iem.s.cbOpcode))
-        return iemOpcodeGetNextS8SxU16Slow(pVCpu, pu16);
-
-    *pu16 = (uint16_t)(int16_t)(int8_t)pVCpu->iem.s.abOpcode[offOpcode];
-    pVCpu->iem.s.offOpcode = offOpcode + 1;
-    return VINF_SUCCESS;
-}
-# endif /* !IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_NEXT_S8(a_pi8) (*(a_pi8) = (int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
 
 /**
@@ -320,36 +169,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU16(pVCpu, (a_pu16)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) (*(a_pu16) = (uint16_t)(int16_t)(int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
-# endif
-
-# ifndef IEM_WITH_SETJMP
-/**
- * Fetches the next signed byte from the opcode stream, extending it to
- * unsigned 32-bit.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu32                Where to return the unsigned dword.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU32(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
-{
-    uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_UNLIKELY(offOpcode >= pVCpu->iem.s.cbOpcode))
-        return iemOpcodeGetNextS8SxU32Slow(pVCpu, pu32);
-
-    *pu32 = (uint32_t)(int32_t)(int8_t)pVCpu->iem.s.abOpcode[offOpcode];
-    pVCpu->iem.s.offOpcode = offOpcode + 1;
-    return VINF_SUCCESS;
-}
-# endif /* !IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) (*(a_pu16) = (uint16_t)(int16_t)(int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
 
 /**
@@ -360,37 +178,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU32(pVCpu, (a_pu32)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) (*(a_pu32) = (uint32_t)(int32_t)(int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
-# endif
-
-
-# ifndef IEM_WITH_SETJMP
-/**
- * Fetches the next signed byte from the opcode stream, extending it to
- * unsigned 64-bit.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu64                Where to return the unsigned qword.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
-{
-    uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_UNLIKELY(offOpcode >= pVCpu->iem.s.cbOpcode))
-        return iemOpcodeGetNextS8SxU64Slow(pVCpu, pu64);
-
-    *pu64 = (uint64_t)(int64_t)(int8_t)pVCpu->iem.s.abOpcode[offOpcode];
-    pVCpu->iem.s.offOpcode = offOpcode + 1;
-    return VINF_SUCCESS;
-}
-# endif /* !IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) (*(a_pu32) = (uint32_t)(int32_t)(int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
 
 /**
@@ -401,43 +187,6 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU64(pVCpu, (a_pu64)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) (*(a_pu64) = (uint64_t)(int64_t)(int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
-# endif
-
-
-# ifndef IEM_WITH_SETJMP
-
-/**
- * Fetches the next opcode word.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu16                Where to return the opcode word.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT
-{
-    uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_LIKELY((uint8_t)offOpcode + 2 <= pVCpu->iem.s.cbOpcode))
-    {
-        pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 2;
-#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
-        *pu16 = *(uint16_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-#  else
-        *pu16 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
-#  endif
-        return VINF_SUCCESS;
-    }
-    return iemOpcodeGetNextU16Slow(pVCpu, pu16);
-}
-
-# else  /* IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) (*(a_pu64) = (uint64_t)(int64_t)(int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
+
 
 /**
@@ -449,5 +198,5 @@
 DECL_INLINE_THROW(uint16_t) iemOpcodeGetNextU16Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  ifdef IEM_WITH_CODE_TLB
+# ifdef IEM_WITH_CODE_TLB
     uint16_t        u16Ret;
     uintptr_t       offBuf = pVCpu->iem.s.offInstrNextByte;
@@ -457,43 +206,41 @@
     {
         pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 2;
-#   ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
         u16Ret = *(uint16_t const *)&pbBuf[offBuf];
-#   else
+#  else
         u16Ret = RT_MAKE_U16(pbBuf[offBuf], pbBuf[offBuf + 1]);
-#   endif
+#  endif
     }
     else
         u16Ret = iemOpcodeGetNextU16SlowJmp(pVCpu);
 
-#   ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
+#  ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
     uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
     Assert(offOpcode + 1 < sizeof(pVCpu->iem.s.abOpcode));
-#    ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+#   ifdef IEM_USE_UNALIGNED_DATA_ACCESS
     *(uint16_t *)&pVCpu->iem.s.abOpcode[offOpcode] = u16Ret;
-#    else
+#   else
     pVCpu->iem.s.abOpcode[offOpcode]     = RT_LO_U8(u16Ret);
     pVCpu->iem.s.abOpcode[offOpcode + 1] = RT_HI_U8(u16Ret);
-#    endif
+#   endif
     pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + (uint8_t)2;
-#   endif
+#  endif
 
     return u16Ret;
 
-#  else /* !IEM_WITH_CODE_TLB */
+# else /* !IEM_WITH_CODE_TLB */
     uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
     if (RT_LIKELY((uint8_t)offOpcode + 2 <= pVCpu->iem.s.cbOpcode))
     {
         pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 2;
-#   ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
         return *(uint16_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-#   else
+#  else
         return RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
-#   endif
+#  endif
     }
     return iemOpcodeGetNextU16SlowJmp(pVCpu);
-#  endif /* !IEM_WITH_CODE_TLB */
-}
-
-# endif /* IEM_WITH_SETJMP */
+# endif /* !IEM_WITH_CODE_TLB */
+}
 
 /**
@@ -503,35 +250,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_U16(a_pu16) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16(pVCpu, (a_pu16)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_U16(a_pu16) (*(a_pu16) = iemOpcodeGetNextU16Jmp(pVCpu))
-# endif
-
-# ifndef IEM_WITH_SETJMP
-/**
- * Fetches the next opcode word, zero extending it to a double word.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu32                Where to return the opcode double word.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16ZxU32(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
-{
-    uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_UNLIKELY(offOpcode + 2 > pVCpu->iem.s.cbOpcode))
-        return iemOpcodeGetNextU16ZxU32Slow(pVCpu, pu32);
-
-    *pu32 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
-    pVCpu->iem.s.offOpcode = offOpcode + 2;
-    return VINF_SUCCESS;
-}
-# endif /* !IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_NEXT_U16(a_pu16) (*(a_pu16) = iemOpcodeGetNextU16Jmp(pVCpu))
 
 /**
@@ -542,35 +259,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16ZxU32(pVCpu, (a_pu32)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) (*(a_pu32) = iemOpcodeGetNextU16Jmp(pVCpu))
-# endif
-
-# ifndef IEM_WITH_SETJMP
-/**
- * Fetches the next opcode word, zero extending it to a quad word.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu64                Where to return the opcode quad word.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16ZxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
-{
-    uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_UNLIKELY(offOpcode + 2 > pVCpu->iem.s.cbOpcode))
-        return iemOpcodeGetNextU16ZxU64Slow(pVCpu, pu64);
-
-    *pu64 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
-    pVCpu->iem.s.offOpcode = offOpcode + 2;
-    return VINF_SUCCESS;
-}
-# endif /* !IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) (*(a_pu32) = iemOpcodeGetNextU16Jmp(pVCpu))
 
 /**
@@ -581,31 +268,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16ZxU64(pVCpu, (a_pu64)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64)  (*(a_pu64) = iemOpcodeGetNextU16Jmp(pVCpu))
-# endif
-
-
-# ifndef IEM_WITH_SETJMP
-/**
- * Fetches the next signed word from the opcode stream.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pi16                Where to return the signed word.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS16(PVMCPUCC pVCpu, int16_t *pi16) RT_NOEXCEPT
-{
-    return iemOpcodeGetNextU16(pVCpu, (uint16_t *)pi16);
-}
-# endif /* !IEM_WITH_SETJMP */
-
+# define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64)  (*(a_pu64) = iemOpcodeGetNextU16Jmp(pVCpu))
 
 /**
@@ -616,45 +277,6 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_S16(a_pi16) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS16(pVCpu, (a_pi16)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_S16(a_pi16) (*(a_pi16) = (int16_t)iemOpcodeGetNextU16Jmp(pVCpu))
-# endif
-
-# ifndef IEM_WITH_SETJMP
-
-/**
- * Fetches the next opcode dword.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu32                Where to return the opcode double word.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU32(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
-{
-    uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_LIKELY((uint8_t)offOpcode + 4 <= pVCpu->iem.s.cbOpcode))
-    {
-        pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 4;
-#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
-        *pu32 = *(uint32_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-#  else
-        *pu32 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 1],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 2],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 3]);
-#  endif
-        return VINF_SUCCESS;
-    }
-    return iemOpcodeGetNextU32Slow(pVCpu, pu32);
-}
-
-# else  /* IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_NEXT_S16(a_pi16) (*(a_pi16) = (int16_t)iemOpcodeGetNextU16Jmp(pVCpu))
+
 
 /**
@@ -666,5 +288,5 @@
 DECL_INLINE_THROW(uint32_t) iemOpcodeGetNextU32Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  ifdef IEM_WITH_CODE_TLB
+# ifdef IEM_WITH_CODE_TLB
     uint32_t u32Ret;
     uintptr_t       offBuf = pVCpu->iem.s.offInstrNextByte;
@@ -674,51 +296,49 @@
     {
         pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 4;
-#   ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
         u32Ret = *(uint32_t const *)&pbBuf[offBuf];
-#   else
+#  else
         u32Ret = RT_MAKE_U32_FROM_U8(pbBuf[offBuf],
                                      pbBuf[offBuf + 1],
                                      pbBuf[offBuf + 2],
                                      pbBuf[offBuf + 3]);
-#   endif
+#  endif
     }
     else
         u32Ret = iemOpcodeGetNextU32SlowJmp(pVCpu);
 
-#   ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
+#  ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
     uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
     Assert(offOpcode + 3 < sizeof(pVCpu->iem.s.abOpcode));
-#    ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+#   ifdef IEM_USE_UNALIGNED_DATA_ACCESS
     *(uint32_t *)&pVCpu->iem.s.abOpcode[offOpcode] = u32Ret;
-#    else
+#   else
     pVCpu->iem.s.abOpcode[offOpcode]     = RT_BYTE1(u32Ret);
     pVCpu->iem.s.abOpcode[offOpcode + 1] = RT_BYTE2(u32Ret);
     pVCpu->iem.s.abOpcode[offOpcode + 2] = RT_BYTE3(u32Ret);
     pVCpu->iem.s.abOpcode[offOpcode + 3] = RT_BYTE4(u32Ret);
-#    endif
+#   endif
     pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + (uint8_t)4;
-#   endif /* IEM_WITH_CODE_TLB_AND_OPCODE_BUF */
+#  endif /* IEM_WITH_CODE_TLB_AND_OPCODE_BUF */
 
     return u32Ret;
 
-#  else  /* !IEM_WITH_CODE_TLB */
+# else  /* !IEM_WITH_CODE_TLB */
     uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
     if (RT_LIKELY((uint8_t)offOpcode + 4 <= pVCpu->iem.s.cbOpcode))
     {
         pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 4;
-#   ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
         return *(uint32_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-#   else
+#  else
         return RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
                                    pVCpu->iem.s.abOpcode[offOpcode + 1],
                                    pVCpu->iem.s.abOpcode[offOpcode + 2],
                                    pVCpu->iem.s.abOpcode[offOpcode + 3]);
-#   endif
+#  endif
     }
     return iemOpcodeGetNextU32SlowJmp(pVCpu);
-#  endif
-}
-
-# endif /* IEM_WITH_SETJMP */
+# endif
+}
 
 /**
@@ -728,38 +348,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_U32(a_pu32) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU32(pVCpu, (a_pu32)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_U32(a_pu32) (*(a_pu32) = iemOpcodeGetNextU32Jmp(pVCpu))
-# endif
-
-# ifndef IEM_WITH_SETJMP
-/**
- * Fetches the next opcode dword, zero extending it to a quad word.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu64                Where to return the opcode quad word.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU32ZxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
-{
-    uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_UNLIKELY(offOpcode + 4 > pVCpu->iem.s.cbOpcode))
-        return iemOpcodeGetNextU32ZxU64Slow(pVCpu, pu64);
-
-    *pu64 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
-                                pVCpu->iem.s.abOpcode[offOpcode + 1],
-                                pVCpu->iem.s.abOpcode[offOpcode + 2],
-                                pVCpu->iem.s.abOpcode[offOpcode + 3]);
-    pVCpu->iem.s.offOpcode = offOpcode + 4;
-    return VINF_SUCCESS;
-}
-# endif /* !IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_NEXT_U32(a_pu32) (*(a_pu32) = iemOpcodeGetNextU32Jmp(pVCpu))
 
 /**
@@ -770,30 +357,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU32ZxU64(pVCpu, (a_pu64)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) (*(a_pu64) = iemOpcodeGetNextU32Jmp(pVCpu))
-# endif
-
-
-# ifndef IEM_WITH_SETJMP
-/**
- * Fetches the next signed double word from the opcode stream.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pi32                Where to return the signed double word.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS32(PVMCPUCC pVCpu, int32_t *pi32) RT_NOEXCEPT
-{
-    return iemOpcodeGetNextU32(pVCpu, (uint32_t *)pi32);
-}
-# endif
+# define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) (*(a_pu64) = iemOpcodeGetNextU32Jmp(pVCpu))
 
 /**
@@ -804,39 +366,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_S32(a_pi32) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS32(pVCpu, (a_pi32)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_S32(a_pi32)    (*(a_pi32) = (int32_t)iemOpcodeGetNextU32Jmp(pVCpu))
-# endif
-
-# ifndef IEM_WITH_SETJMP
-/**
- * Fetches the next opcode dword, sign extending it into a quad word.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu64                Where to return the opcode quad word.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS32SxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
-{
-    uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_UNLIKELY(offOpcode + 4 > pVCpu->iem.s.cbOpcode))
-        return iemOpcodeGetNextS32SxU64Slow(pVCpu, pu64);
-
-    int32_t i32 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
-                                      pVCpu->iem.s.abOpcode[offOpcode + 1],
-                                      pVCpu->iem.s.abOpcode[offOpcode + 2],
-                                      pVCpu->iem.s.abOpcode[offOpcode + 3]);
-    *pu64 = (uint64_t)(int64_t)i32;
-    pVCpu->iem.s.offOpcode = offOpcode + 4;
-    return VINF_SUCCESS;
-}
-# endif /* !IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_NEXT_S32(a_pi32)    (*(a_pi32) = (int32_t)iemOpcodeGetNextU32Jmp(pVCpu))
 
 /**
@@ -847,49 +375,6 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS32SxU64(pVCpu, (a_pu64)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) (*(a_pu64) = (uint64_t)(int64_t)(int32_t)iemOpcodeGetNextU32Jmp(pVCpu))
-# endif
-
-# ifndef IEM_WITH_SETJMP
-
-/**
- * Fetches the next opcode qword.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pu64                Where to return the opcode qword.
- */
-DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
-{
-    uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
-    if (RT_LIKELY((uint8_t)offOpcode + 8 <= pVCpu->iem.s.cbOpcode))
-    {
-#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
-        *pu64 = *(uint64_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-#  else
-        *pu64 = RT_MAKE_U64_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 1],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 2],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 3],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 4],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 5],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 6],
-                                    pVCpu->iem.s.abOpcode[offOpcode + 7]);
-#  endif
-        pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 8;
-        return VINF_SUCCESS;
-    }
-    return iemOpcodeGetNextU64Slow(pVCpu, pu64);
-}
-
-# else  /* IEM_WITH_SETJMP */
+# define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) (*(a_pu64) = (uint64_t)(int64_t)(int32_t)iemOpcodeGetNextU32Jmp(pVCpu))
+
 
 /**
@@ -901,5 +386,5 @@
 DECL_INLINE_THROW(uint64_t) iemOpcodeGetNextU64Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
 {
-#  ifdef IEM_WITH_CODE_TLB
+# ifdef IEM_WITH_CODE_TLB
     uint64_t        u64Ret;
     uintptr_t       offBuf = pVCpu->iem.s.offInstrNextByte;
@@ -909,7 +394,7 @@
     {
         pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 8;
-#   ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
         u64Ret = *(uint64_t const *)&pbBuf[offBuf];
-#   else
+#  else
         u64Ret = RT_MAKE_U64_FROM_U8(pbBuf[offBuf],
                                      pbBuf[offBuf + 1],
@@ -920,15 +405,15 @@
                                      pbBuf[offBuf + 6],
                                      pbBuf[offBuf + 7]);
-#   endif
+#  endif
     }
     else
         u64Ret = iemOpcodeGetNextU64SlowJmp(pVCpu);
 
-#   ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
+#  ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
     uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
     Assert(offOpcode + 7 < sizeof(pVCpu->iem.s.abOpcode));
-#    ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+#   ifdef IEM_USE_UNALIGNED_DATA_ACCESS
     *(uint64_t *)&pVCpu->iem.s.abOpcode[offOpcode] = u64Ret;
-#    else
+#   else
     pVCpu->iem.s.abOpcode[offOpcode]     = RT_BYTE1(u64Ret);
     pVCpu->iem.s.abOpcode[offOpcode + 1] = RT_BYTE2(u64Ret);
@@ -939,18 +424,18 @@
     pVCpu->iem.s.abOpcode[offOpcode + 6] = RT_BYTE7(u64Ret);
     pVCpu->iem.s.abOpcode[offOpcode + 7] = RT_BYTE8(u64Ret);
-#    endif
+#   endif
     pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + (uint8_t)8;
-#   endif /* IEM_WITH_CODE_TLB_AND_OPCODE_BUF */
+#  endif /* IEM_WITH_CODE_TLB_AND_OPCODE_BUF */
 
     return u64Ret;
 
-#  else /* !IEM_WITH_CODE_TLB */
+# else /* !IEM_WITH_CODE_TLB */
     uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
     if (RT_LIKELY((uint8_t)offOpcode + 8 <= pVCpu->iem.s.cbOpcode))
     {
         pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 8;
-#   ifdef IEM_USE_UNALIGNED_DATA_ACCESS
+#  ifdef IEM_USE_UNALIGNED_DATA_ACCESS
         return *(uint64_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
-#   else
+#  else
         return RT_MAKE_U64_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
                                    pVCpu->iem.s.abOpcode[offOpcode + 1],
@@ -961,11 +446,9 @@
                                    pVCpu->iem.s.abOpcode[offOpcode + 6],
                                    pVCpu->iem.s.abOpcode[offOpcode + 7]);
-#   endif
+#  endif
     }
     return iemOpcodeGetNextU64SlowJmp(pVCpu);
-#  endif /* !IEM_WITH_CODE_TLB */
-}
-
-# endif /* IEM_WITH_SETJMP */
+# endif /* !IEM_WITH_CODE_TLB */
+}
 
 /**
@@ -975,15 +458,5 @@
  * @remark Implicitly references pVCpu.
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_GET_NEXT_U64(a_pu64) \
-    do \
-    { \
-        VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU64(pVCpu, (a_pu64)); \
-        if (rcStrict2 != VINF_SUCCESS) \
-            return rcStrict2; \
-    } while (0)
-# else
-#  define IEM_OPCODE_GET_NEXT_U64(a_pu64)    ( *(a_pu64) = iemOpcodeGetNextU64Jmp(pVCpu) )
-# endif
+# define IEM_OPCODE_GET_NEXT_U64(a_pu64)    ( *(a_pu64) = iemOpcodeGetNextU64Jmp(pVCpu) )
 
 /**
@@ -997,21 +470,10 @@
  *       used instead.  At least for now...
  */
-# ifndef IEM_WITH_SETJMP
-#  define IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(a_bRm) do { \
-        RTGCPTR      GCPtrEff; \
-        VBOXSTRICTRC rcStrict = iemOpHlpCalcRmEffAddr(pVCpu, bRm, 0, &GCPtrEff); \
-        if (rcStrict != VINF_SUCCESS) \
-            return rcStrict; \
-    } while (0)
-# else
-#  define IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(a_bRm) do { \
+# define IEM_OPCODE_SKIP_RM_EFF_ADDR_BYTES(a_bRm) do { \
         (void)iemOpHlpCalcRmEffAddrJmp(pVCpu, bRm, 0); \
     } while (0)
-# endif
-
-#endif /* !IEM_WITH_OPAQUE_DECODER_STATE */
-
-
-#ifndef IEM_WITH_OPAQUE_DECODER_STATE
+
+
+
 
 /**
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMInlineMem-x86.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMInlineMem-x86.h	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMInlineMem-x86.h	(revision 108278)
@@ -137,5 +137,4 @@
 
 
-#ifdef IEM_WITH_SETJMP
 
 /** @todo slim this down   */
@@ -278,5 +277,4 @@
 }
 
-#endif /* IEM_WITH_SETJMP */
 
 /**
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMInternal-x86.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMInternal-x86.h	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMInternal-x86.h	(revision 108278)
@@ -2846,22 +2846,14 @@
 VBOXSTRICTRC            iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
                                           uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
                                              uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
 VBOXSTRICTRC            iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
 VBOXSTRICTRC            iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
 VBOXSTRICTRC            iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
@@ -2875,37 +2867,21 @@
 VBOXSTRICTRC            iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
 VBOXSTRICTRC            iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
 VBOXSTRICTRC            iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
 VBOXSTRICTRC            iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 
 void                    iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
@@ -3029,22 +3005,8 @@
 VBOXSTRICTRC    iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
 #endif
-#ifdef IEM_WITH_SETJMP
 uint8_t         iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
 uint16_t        iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
 uint32_t        iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
 uint64_t        iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
-#else
-VBOXSTRICTRC    iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
-#endif
 
 VBOXSTRICTRC    iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
@@ -3066,5 +3028,4 @@
 VBOXSTRICTRC    iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
                                     RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 uint8_t         iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
 uint16_t        iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
@@ -3083,5 +3044,5 @@
 void            iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
-# if 0 /* these are inlined now */
+#if 0 /* these are inlined now */
 uint8_t         iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
 uint16_t        iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
@@ -3097,7 +3058,6 @@
 void            iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
-# endif
+#endif
 void            iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 
 VBOXSTRICTRC    iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
@@ -3120,5 +3080,4 @@
 VBOXSTRICTRC    iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
 VBOXSTRICTRC    iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 void            iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
@@ -3133,5 +3092,5 @@
 void            iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
-#if 0
+#if 0 /* inlined */
 void            iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
@@ -3145,7 +3104,5 @@
 void            iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
-
-#ifdef IEM_WITH_SETJMP
+
 uint8_t        *iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
 uint8_t        *iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
@@ -3174,5 +3131,4 @@
 PRTUINT128U     iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
 PCRTUINT128U    iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 
 VBOXSTRICTRC    iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
@@ -3198,5 +3154,4 @@
 VBOXSTRICTRC    iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
 
-#ifdef IEM_WITH_SETJMP
 void            iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
@@ -3226,6 +3181,4 @@
 uint32_t        iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
 uint64_t        iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
-
-#endif
 
 /** @} */
Index: trunk/src/VBox/VMM/VMMAll/target-x86/IEMOpHlp-x86.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMOpHlp-x86.h	(revision 108269)
+++ trunk/src/VBox/VMM/VMMAll/target-x86/IEMOpHlp-x86.h	(revision 108278)
@@ -654,10 +654,6 @@
       == (pVCpu->cpum.GstCtx.rip >> GUEST_PAGE_SHIFT))
 
-VBOXSTRICTRC    iemOpHlpCalcRmEffAddr(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, PRTGCPTR pGCPtrEff) RT_NOEXCEPT;
-VBOXSTRICTRC    iemOpHlpCalcRmEffAddrEx(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, PRTGCPTR pGCPtrEff, uint64_t *puInfo) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
-RTGCPTR         iemOpHlpCalcRmEffAddrJmp(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset) IEM_NOEXCEPT_MAY_LONGJMP;
-RTGCPTR         iemOpHlpCalcRmEffAddrJmpEx(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, uint64_t *puInfo) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
+RTGCPTR iemOpHlpCalcRmEffAddrJmp(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset) IEM_NOEXCEPT_MAY_LONGJMP;
+RTGCPTR iemOpHlpCalcRmEffAddrJmpEx(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, uint64_t *puInfo) IEM_NOEXCEPT_MAY_LONGJMP;
 
 /** @}  */
Index: trunk/src/VBox/VMM/include/IEMInline.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMInline.h	(revision 108269)
+++ trunk/src/VBox/VMM/include/IEMInline.h	(revision 108278)
@@ -351,12 +351,10 @@
  */
 
-#ifdef IEM_WITH_SETJMP
-
 DECL_INLINE_THROW(void) iemMemCommitAndUnmapRwJmp(PVMCPUCC pVCpu, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
     if (RT_LIKELY(bMapInfo == 0))
         return;
-# endif
+#endif
     iemMemCommitAndUnmapRwSafeJmp(pVCpu, bMapInfo);
 }
@@ -365,8 +363,8 @@
 DECL_INLINE_THROW(void) iemMemCommitAndUnmapAtJmp(PVMCPUCC pVCpu, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
     if (RT_LIKELY(bMapInfo == 0))
         return;
-# endif
+#endif
     iemMemCommitAndUnmapAtSafeJmp(pVCpu, bMapInfo);
 }
@@ -375,8 +373,8 @@
 DECL_INLINE_THROW(void) iemMemCommitAndUnmapWoJmp(PVMCPUCC pVCpu, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
     if (RT_LIKELY(bMapInfo == 0))
         return;
-# endif
+#endif
     iemMemCommitAndUnmapWoSafeJmp(pVCpu, bMapInfo);
 }
@@ -385,8 +383,8 @@
 DECL_INLINE_THROW(void) iemMemCommitAndUnmapRoJmp(PVMCPUCC pVCpu, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
     if (RT_LIKELY(bMapInfo == 0))
         return;
-# endif
+#endif
     iemMemCommitAndUnmapRoSafeJmp(pVCpu, bMapInfo);
 }
@@ -394,13 +392,10 @@
 DECLINLINE(void) iemMemRollbackAndUnmapWo(PVMCPUCC pVCpu, uint8_t bMapInfo) RT_NOEXCEPT
 {
-# if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
+#if defined(IEM_WITH_DATA_TLB) && defined(IN_RING3)
     if (RT_LIKELY(bMapInfo == 0))
         return;
-# endif
+#endif
     iemMemRollbackAndUnmapWoSafe(pVCpu, bMapInfo);
 }
-
-#endif /* IEM_WITH_SETJMP */
-
 
 /** @} */
Index: trunk/src/VBox/VMM/include/IEMInternal-armv8.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMInternal-armv8.h	(revision 108269)
+++ trunk/src/VBox/VMM/include/IEMInternal-armv8.h	(revision 108278)
@@ -56,18 +56,7 @@
 #endif
 
-/** @def IEM_WITH_SETJMP
- * Enables alternative status code handling using setjmps.
- *
- * This adds a bit of expense via the setjmp() call since it saves all the
- * non-volatile registers.  However, it eliminates return code checks and allows
- * for more optimal return value passing (return regs instead of stack buffer).
- */
-#if defined(DOXYGEN_RUNNING) || defined(RT_OS_WINDOWS) || 1
-# define IEM_WITH_SETJMP
-#endif
-
 /** @def IEM_WITH_THROW_CATCH
  * Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
- * mode code when IEM_WITH_SETJMP is in effect.
+ * mode code.
  *
  * With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
@@ -80,5 +69,5 @@
  * Linux, but it should be quite a bit faster for normal code.
  */
-#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) || defined(_MSC_VER))) \
+#if (defined(IN_RING3) && (defined(__GNUC__) || defined(_MSC_VER))) \
  || defined(DOXYGEN_RUNNING)
 # define IEM_WITH_THROW_CATCH
@@ -92,10 +81,8 @@
  * @param   a_rc        The status code jump back with / throw.
  */
-#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
-# ifdef IEM_WITH_THROW_CATCH
-#  define IEM_DO_LONGJMP(a_pVCpu, a_rc)  throw int(a_rc)
-# else
-#  define IEM_DO_LONGJMP(a_pVCpu, a_rc)  longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
-# endif
+#ifdef IEM_WITH_THROW_CATCH
+# define IEM_DO_LONGJMP(a_pVCpu, a_rc)  throw int(a_rc)
+#else
+# define IEM_DO_LONGJMP(a_pVCpu, a_rc)  longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
 #endif
 
@@ -130,5 +117,5 @@
  * @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
  */
-#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) || defined(IEM_WITH_THROW_CATCH))
+#if defined(_MSC_VER) || defined(IEM_WITH_THROW_CATCH)
 # define IEM_NOEXCEPT_MAY_LONGJMP   RT_NOEXCEPT_EX(false)
 #else
@@ -1222,20 +1209,14 @@
 VBOXSTRICTRC            iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
                                           uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
                                              uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
 VBOXSTRICTRC            iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
 VBOXSTRICTRC            iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
 VBOXSTRICTRC            iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
 VBOXSTRICTRC            iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 DECL_NO_RETURN(void)    iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 VBOXSTRICTRC            iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
 
@@ -1287,5 +1268,4 @@
 VBOXSTRICTRC    iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
 VBOXSTRICTRC    iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 uint8_t         iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
 uint16_t        iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
@@ -1296,5 +1276,4 @@
 void            iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 
 VBOXSTRICTRC    iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
@@ -1309,5 +1288,4 @@
 VBOXSTRICTRC    iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
 VBOXSTRICTRC    iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
-#ifdef IEM_WITH_SETJMP
 void            iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
@@ -1316,5 +1294,4 @@
 void            iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
-#endif
 
 VBOXSTRICTRC    iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
Index: trunk/src/VBox/VMM/include/IEMInternal.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMInternal.h	(revision 108269)
+++ trunk/src/VBox/VMM/include/IEMInternal.h	(revision 108278)
@@ -65,18 +65,7 @@
 #endif
 
-/** @def IEM_WITH_SETJMP
- * Enables alternative status code handling using setjmps.
- *
- * This adds a bit of expense via the setjmp() call since it saves all the
- * non-volatile registers.  However, it eliminates return code checks and allows
- * for more optimal return value passing (return regs instead of stack buffer).
- */
-#if defined(DOXYGEN_RUNNING) || defined(RT_OS_WINDOWS) || 1
-# define IEM_WITH_SETJMP
-#endif
-
 /** @def IEM_WITH_THROW_CATCH
  * Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
- * mode code when IEM_WITH_SETJMP is in effect.
+ * mode code.
  *
  * With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
@@ -89,5 +78,5 @@
  * Linux, but it should be quite a bit faster for normal code.
  */
-#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) || defined(_MSC_VER)) /* ASM-NOINC-START */
+#if defined(__cplusplus) && defined(IN_RING3) && (defined(__GNUC__) || defined(_MSC_VER)) /* ASM-NOINC-START */
 # define IEM_WITH_THROW_CATCH
 #endif /*ASM-NOINC-END*/
@@ -183,18 +172,16 @@
  * @param   a_rc        The status code jump back with / throw.
  */
-#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
-# ifdef IEM_WITH_THROW_CATCH
-#  ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
-#   define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
+#ifdef IEM_WITH_THROW_CATCH
+# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
+#  define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
             if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
                 iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
             throw int(a_rc); \
         } while (0)
-#  else
-#   define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
-#  endif
 # else
-#  define IEM_DO_LONGJMP(a_pVCpu, a_rc)  longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
+#  define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
 # endif
+#else
+# define IEM_DO_LONGJMP(a_pVCpu, a_rc)  longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
 #endif
 
@@ -229,5 +216,5 @@
  * @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
  */
-#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) || defined(IEM_WITH_THROW_CATCH))
+#if defined(_MSC_VER) || defined(IEM_WITH_THROW_CATCH)
 # define IEM_NOEXCEPT_MAY_LONGJMP   RT_NOEXCEPT_EX(false)
 #else
@@ -2537,37 +2524,35 @@
  * @param   a_pVCpu     The cross context virtual CPU structure of the calling EMT.
  */
-#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
-# ifdef IEM_WITH_THROW_CATCH
-#  define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
+#ifdef IEM_WITH_THROW_CATCH
+# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
         a_rcTarget = VINF_SUCCESS; \
         try
-#  define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
+# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
         IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
-#  define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
+# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
         catch (int rcThrown) \
         { \
             a_rcTarget = rcThrown
-#  define IEM_CATCH_LONGJMP_END(a_pVCpu) \
+# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
         } \
         ((void)0)
-# else  /* !IEM_WITH_THROW_CATCH */
-#  define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
+#else  /* !IEM_WITH_THROW_CATCH */
+# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
         jmp_buf  JmpBuf; \
         jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
         (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
         if ((rcStrict = setjmp(JmpBuf)) == 0)
-#  define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
+# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
         pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
         (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
         if ((rcStrict = setjmp(JmpBuf)) == 0)
-#  define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
+# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
         else \
         { \
             ((void)0)
-#  define IEM_CATCH_LONGJMP_END(a_pVCpu) \
+# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
         } \
         (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
-# endif /* !IEM_WITH_THROW_CATCH */
-#endif  /* IEM_WITH_SETJMP */
+#endif /* !IEM_WITH_THROW_CATCH */
 
 
@@ -3171,5 +3156,4 @@
 void            iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
 
-#ifdef IEM_WITH_SETJMP
 void            iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
@@ -3178,5 +3162,4 @@
 void            iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
 void            iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
-#endif
 
 void            iemTlbInvalidateAllPhysicalSlow(PVMCPUCC pVCpu) RT_NOEXCEPT;
Index: trunk/src/VBox/VMM/include/IEMMc.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMMc.h	(revision 108269)
+++ trunk/src/VBox/VMM/include/IEMMc.h	(revision 108278)
@@ -970,239 +970,124 @@
     do { IEM_MC_INT_CLEAR_ZMM_256_UP(a_iYReg); } while (0)
 
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
-# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
-#else
-# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
     ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
+#define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
     ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
-# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
+#define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
     ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
 
-# define IEM_MC_FETCH_MEM_FLAT_U8(a_u8Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U8(a_u8Dst, a_GCPtrMem) \
     ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM16_FLAT_U8(a_u8Dst, a_GCPtrMem16) \
+#define IEM_MC_FETCH_MEM16_FLAT_U8(a_u8Dst, a_GCPtrMem16) \
     ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem16)))
-# define IEM_MC_FETCH_MEM32_FLAT_U8(a_u8Dst, a_GCPtrMem32) \
+#define IEM_MC_FETCH_MEM32_FLAT_U8(a_u8Dst, a_GCPtrMem32) \
     ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem32)))
-#endif
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
-# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_I16_DISP(a_i16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
-#else
-# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
+
+#define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
     ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
+#define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
     ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
-# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
     ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_I16_DISP(a_i16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
+#define IEM_MC_FETCH_MEM_I16_DISP(a_i16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
     ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
 
-# define IEM_MC_FETCH_MEM_FLAT_U16(a_u16Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U16(a_u16Dst, a_GCPtrMem) \
     ((a_u16Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U16_DISP(a_u16Dst, a_GCPtrMem, a_offDisp) \
+#define IEM_MC_FETCH_MEM_FLAT_U16_DISP(a_u16Dst, a_GCPtrMem, a_offDisp) \
     ((a_u16Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
-# define IEM_MC_FETCH_MEM_FLAT_I16(a_i16Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_I16(a_i16Dst, a_GCPtrMem) \
     ((a_i16Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_I16_DISP(a_i16Dst, a_GCPtrMem, a_offDisp) \
+#define IEM_MC_FETCH_MEM_FLAT_I16_DISP(a_i16Dst, a_GCPtrMem, a_offDisp) \
     ((a_i16Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
-#endif
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
-# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_I32_DISP(a_i32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
-#else
-# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
+
+#define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
     ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
+#define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
     ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
-# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
     ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_I32_DISP(a_i32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
+#define IEM_MC_FETCH_MEM_I32_DISP(a_i32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
     ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
 
-# define IEM_MC_FETCH_MEM_FLAT_U32(a_u32Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U32(a_u32Dst, a_GCPtrMem) \
     ((a_u32Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U32_DISP(a_u32Dst, a_GCPtrMem, a_offDisp) \
+#define IEM_MC_FETCH_MEM_FLAT_U32_DISP(a_u32Dst, a_GCPtrMem, a_offDisp) \
     ((a_u32Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
-# define IEM_MC_FETCH_MEM_FLAT_I32(a_i32Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_I32(a_i32Dst, a_GCPtrMem) \
     ((a_i32Dst) = (int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_I32_DISP(a_i32Dst, a_GCPtrMem, a_offDisp) \
+#define IEM_MC_FETCH_MEM_FLAT_I32_DISP(a_i32Dst, a_GCPtrMem, a_offDisp) \
     ((a_i32Dst) = (int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
-#endif
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
-# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
-#else
-# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
+
+#define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
     ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
+#define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
     ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
-# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
     ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
     ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
 
-# define IEM_MC_FETCH_MEM_FLAT_U64(a_u64Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U64(a_u64Dst, a_GCPtrMem) \
     ((a_u64Dst) = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U64_DISP(a_u64Dst, a_GCPtrMem, a_offDisp) \
+#define IEM_MC_FETCH_MEM_FLAT_U64_DISP(a_u64Dst, a_GCPtrMem, a_offDisp) \
     ((a_u64Dst) = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
-# define IEM_MC_FETCH_MEM_FLAT_U64_ALIGN_U128(a_u64Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U64_ALIGN_U128(a_u64Dst, a_GCPtrMem) \
     ((a_u64Dst) = iemMemFlatFetchDataU64AlignedU128Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_I64(a_i64Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_I64(a_i64Dst, a_GCPtrMem) \
     ((a_i64Dst) = (int64_t)iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
-#endif
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
-#else
-# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
+
+#define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
     ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
     ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
 
-# define IEM_MC_FETCH_MEM_FLAT_R32(a_r32Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_R32(a_r32Dst, a_GCPtrMem) \
     ((a_r32Dst).u = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_R64(a_r64Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_R64(a_r64Dst, a_GCPtrMem) \
     ((a_r64Dst).u = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_R80(a_r80Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_R80(a_r80Dst, a_GCPtrMem) \
     iemMemFlatFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_FLAT_D80(a_d80Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_D80(a_d80Dst, a_GCPtrMem) \
     iemMemFlatFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_GCPtrMem))
-#endif
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128NoAc(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
-
-# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128NoAc(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
-
-# define IEM_MC_FETCH_MEM_U128_NO_AC_AND_XREG_U128(a_u128Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128NoAc(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2))); \
-        (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
-        (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
-    } while (0)
-
-# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE_AND_XREG_XMM(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_Dst).uSrc2.uXmm, (a_iSeg2), (a_GCPtrMem2))); \
-        (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
-        (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
-    } while (0)
-
-# define IEM_MC_FETCH_MEM_XMM_NO_AC_AND_XREG_XMM(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128NoAc(pVCpu, &(a_Dst).uSrc2.uXmm, (a_iSeg2), (a_GCPtrMem2))); \
-        (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
-        (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
-    } while (0)
-
-# define IEM_MC_FETCH_MEM_XMM_U32_AND_XREG_XMM(a_Dst, a_iXReg1, a_iDWord2, a_iSeg2, a_GCPtrMem2) do { \
-        (a_Dst).uSrc2.uXmm.au64[0] = 0; \
-        (a_Dst).uSrc2.uXmm.au64[1] = 0; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_Dst).uSrc2.uXmm.au32[(a_iDWord2)], (a_iSeg2), (a_GCPtrMem2))); \
-        (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
-        (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
-    } while (0)
-
-# define IEM_MC_FETCH_MEM_XMM_U64_AND_XREG_XMM(a_Dst, a_iXReg1, a_iQWord2, a_iSeg2, a_GCPtrMem2) do { \
-        (a_Dst).uSrc2.uXmm.au64[1] = 0; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_Dst).uSrc2.uXmm.au64[(a_iQWord2)], (a_iSeg2), (a_GCPtrMem2))); \
-        (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
-        (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
-    } while (0)
-
-# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2))); \
-        (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
-        (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
-        (a_Dst).u64Rax        = pVCpu->cpum.GstCtx.rax; \
-        (a_Dst).u64Rdx        = pVCpu->cpum.GstCtx.rdx; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2))); \
-        (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
-        (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
-        (a_Dst).u64Rax        = (int64_t)(int32_t)pVCpu->cpum.GstCtx.eax; \
-        (a_Dst).u64Rdx        = (int64_t)(int32_t)pVCpu->cpum.GstCtx.edx; \
-    } while (0)
-
-#else
-# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
+
+#define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU128NoAcJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
 
-# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU128NoAcJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
 
-# define IEM_MC_FETCH_MEM_FLAT_U128(a_u128Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U128(a_u128Dst, a_GCPtrMem) \
     iemMemFlatFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_FLAT_U128_NO_AC(a_u128Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U128_NO_AC(a_u128Dst, a_GCPtrMem) \
     iemMemFlatFetchDataU128NoAcJmp(pVCpu, &(a_u128Dst), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_FLAT_U128_ALIGN_SSE(a_u128Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U128_ALIGN_SSE(a_u128Dst, a_GCPtrMem) \
     iemMemFlatFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_GCPtrMem))
 
-# define IEM_MC_FETCH_MEM_FLAT_XMM(a_XmmDst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_XMM(a_XmmDst, a_GCPtrMem) \
     iemMemFlatFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC(a_XmmDst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC(a_XmmDst, a_GCPtrMem) \
     iemMemFlatFetchDataU128NoAcJmp(pVCpu, &(a_XmmDst).uXmm, (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE(a_XmmDst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE(a_XmmDst, a_GCPtrMem) \
     iemMemFlatFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_GCPtrMem))
 
-# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_U128_AND_XREG_U128(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
         iemMemFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2)); \
         (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
         (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
     } while (0)
-# define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
         iemMemFlatFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_GCPtrMem2)); \
         (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
@@ -1210,5 +1095,5 @@
     } while (0)
 
-# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE_AND_XREG_XMM(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE_AND_XREG_XMM(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
         iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_Dst).uSrc2.uXmm, (a_iSeg2), (a_GCPtrMem2)); \
         (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
@@ -1216,5 +1101,5 @@
     } while (0)
 
-# define IEM_MC_FETCH_MEM_XMM_NO_AC_AND_XREG_XMM(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_XMM_NO_AC_AND_XREG_XMM(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
         iemMemFetchDataU128NoAcJmp(pVCpu, &(a_Dst).uSrc2.uXmm, (a_iSeg2), (a_GCPtrMem2)); \
         (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
@@ -1222,5 +1107,5 @@
     } while (0)
 
-# define IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE_AND_XREG_XMM(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE_AND_XREG_XMM(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
         iemMemFlatFetchDataU128AlignedSseJmp(pVCpu, &(a_Dst).uSrc2.uXmm, (a_GCPtrMem2)); \
         (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
@@ -1228,5 +1113,5 @@
     } while (0)
 
-# define IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC_AND_XREG_XMM(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC_AND_XREG_XMM(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
         iemMemFlatFetchDataU128NoAcJmp(pVCpu, &(a_Dst).uSrc2.uXmm, (a_GCPtrMem2)); \
         (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
@@ -1234,5 +1119,5 @@
     } while (0)
 
-# define IEM_MC_FETCH_MEM_XMM_U32_AND_XREG_XMM(a_Dst, a_iXReg1, a_iDWord2, a_iSeg2, a_GCPtrMem2) do {  \
+#define IEM_MC_FETCH_MEM_XMM_U32_AND_XREG_XMM(a_Dst, a_iXReg1, a_iDWord2, a_iSeg2, a_GCPtrMem2) do {  \
         (a_Dst).uSrc2.uXmm.au64[0] = 0; \
         (a_Dst).uSrc2.uXmm.au64[1] = 0; \
@@ -1241,5 +1126,5 @@
         (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
     } while (0)
-# define IEM_MC_FETCH_MEM_FLAT_XMM_U32_AND_XREG_XMM(a_Dst, a_iXReg1, a_iDWord2, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_FLAT_XMM_U32_AND_XREG_XMM(a_Dst, a_iXReg1, a_iDWord2, a_GCPtrMem2) do { \
         (a_Dst).uSrc2.uXmm.au64[0] = 0; \
         (a_Dst).uSrc2.uXmm.au64[1] = 0; \
@@ -1249,5 +1134,5 @@
     } while (0)
 
-# define IEM_MC_FETCH_MEM_XMM_U64_AND_XREG_XMM(a_Dst, a_iXReg1, a_iQWord2, a_iSeg2, a_GCPtrMem2) do {  \
+#define IEM_MC_FETCH_MEM_XMM_U64_AND_XREG_XMM(a_Dst, a_iXReg1, a_iQWord2, a_iSeg2, a_GCPtrMem2) do {  \
         (a_Dst).uSrc2.uXmm.au64[!(a_iQWord2)] = 0; \
         (a_Dst).uSrc2.uXmm.au64[(a_iQWord2)]  = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg2), (a_GCPtrMem2)); \
@@ -1255,5 +1140,5 @@
         (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
     } while (0)
-# define IEM_MC_FETCH_MEM_FLAT_XMM_U64_AND_XREG_XMM(a_Dst, a_iXReg1, a_iQWord2, a_GCPtrMem2) do {  \
+#define IEM_MC_FETCH_MEM_FLAT_XMM_U64_AND_XREG_XMM(a_Dst, a_iXReg1, a_iQWord2, a_GCPtrMem2) do {  \
         (a_Dst).uSrc2.uXmm.au64[1] = 0; \
         (a_Dst).uSrc2.uXmm.au64[(a_iQWord2)]  = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem2)); \
@@ -1263,5 +1148,5 @@
 
 
-# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
         iemMemFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2)); \
         (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
@@ -1270,5 +1155,5 @@
         (a_Dst).u64Rdx        = pVCpu->cpum.GstCtx.rdx; \
     } while (0)
-# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
         iemMemFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2)); \
         (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
@@ -1278,5 +1163,5 @@
     } while (0)
 
-# define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
         iemMemFlatFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_GCPtrMem2)); \
         (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
@@ -1285,5 +1170,5 @@
         (a_Dst).u64Rdx        = pVCpu->cpum.GstCtx.rdx; \
     } while (0)
-# define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
         iemMemFlatFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_GCPtrMem2)); \
         (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
@@ -1293,46 +1178,20 @@
     } while (0)
 
-#endif
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256NoAc(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256NoAc(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedAvx(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
-
-# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256NoAc(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256NoAc(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedAvx(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
-
-# define IEM_MC_FETCH_MEM_YMM_NO_AC_AND_YREG_YMM(a_uYmmDst, a_iYRegSrc1, a_iSeg2, a_GCPtrMem2) do { \
-        uintptr_t const a_iYRegSrc1Tmp = (a_iYRegSrc1); \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256NoAc(pVCpu, &(a_uYmmDst).uSrc2.ymm, (a_iSeg2), (a_GCPtrMem2))); \
-        (a_uYmmDst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[a_iYRegSrc1Tmp].au64[0]; \
-        (a_uYmmDst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[a_iYRegSrc1Tmp].au64[1]; \
-        (a_uYmmDst).uSrc1.au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[a_iYRegSrc1Tmp].au64[0]; \
-        (a_uYmmDst).uSrc1.au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[a_iYRegSrc1Tmp].au64[1]; \
-    } while (0)
-
-#else
-# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
+
+#define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU256NoAcJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU256NoAcJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU256AlignedAvxJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
 
-# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU256NoAcJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU256NoAcJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
     iemMemFetchDataU256AlignedAvxJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
 
-# define IEM_MC_FETCH_MEM_YMM_NO_AC_AND_YREG_YMM(a_uYmmDst, a_iYRegSrc1, a_iSeg2, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_YMM_NO_AC_AND_YREG_YMM(a_uYmmDst, a_iYRegSrc1, a_iSeg2, a_GCPtrMem2) do { \
         uintptr_t const a_iYRegSrc1Tmp = (a_iYRegSrc1); \
         iemMemFetchDataU256NoAcJmp(pVCpu, &(a_uYmmDst).uSrc2.ymm, (a_iSeg2), (a_GCPtrMem2)); \
@@ -1343,19 +1202,19 @@
     } while (0)
 
-# define IEM_MC_FETCH_MEM_FLAT_U256(a_u256Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U256(a_u256Dst, a_GCPtrMem) \
     iemMemFlatFetchDataU256NoAcJmp(pVCpu, &(a_u256Dst), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_FLAT_U256_NO_AC(a_u256Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U256_NO_AC(a_u256Dst, a_GCPtrMem) \
     iemMemFlatFetchDataU256NoAcJmp(pVCpu, &(a_u256Dst), (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_FLAT_U256_ALIGN_AVX(a_u256Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U256_ALIGN_AVX(a_u256Dst, a_GCPtrMem) \
     iemMemFlatFetchDataU256AlignedAvxJmp(pVCpu, &(a_u256Dst), (a_GCPtrMem))
 
-# define IEM_MC_FETCH_MEM_FLAT_YMM(a_YmmDst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_YMM(a_YmmDst, a_GCPtrMem) \
     iemMemFlatFetchDataU256NoAcJmp(pVCpu, &(a_YmmDst).ymm, (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_FLAT_YMM_NO_AC(a_YmmDst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_YMM_NO_AC(a_YmmDst, a_GCPtrMem) \
     iemMemFlatFetchDataU256NoAcJmp(pVCpu, &(a_YmmDst).ymm, (a_GCPtrMem))
-# define IEM_MC_FETCH_MEM_FLAT_YMM_ALIGN_AVX(a_YmmDst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_YMM_ALIGN_AVX(a_YmmDst, a_GCPtrMem) \
     iemMemFlatFetchDataU256AlignedAvxJmp(pVCpu, &(a_YmmDst).ymm, (a_GCPtrMem))
 
-# define IEM_MC_FETCH_MEM_FLAT_YMM_ALIGN_AVX_AND_YREG_YMM(a_uYmmDst, a_iYRegSrc1, a_GCPtrMem2) do { \
+#define IEM_MC_FETCH_MEM_FLAT_YMM_ALIGN_AVX_AND_YREG_YMM(a_uYmmDst, a_iYRegSrc1, a_GCPtrMem2) do { \
         uintptr_t const a_iYRegSrc1Tmp = (a_iYRegSrc1); \
         iemMemFlatFetchDataU256AlignedAvxJmp(pVCpu, &(a_uYmmDst).uSrc2.ymm, (a_GCPtrMem2)); \
@@ -1366,195 +1225,93 @@
     } while (0)
 
-#endif
-
-
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint8_t u8Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u16Dst) = u8Tmp; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint8_t u8Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u32Dst) = u8Tmp; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint8_t u8Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u64Dst) = u8Tmp; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint16_t u16Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u32Dst) = u16Tmp; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint16_t u16Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u64Dst) = u16Tmp; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint32_t u32Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u64Dst) = u32Tmp; \
-    } while (0)
-#else  /* IEM_WITH_SETJMP */
-# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
+
+
+#define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
     ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
     ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
     ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
     ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
     ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
     ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
 
-# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U16(a_u16Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U16(a_u16Dst, a_GCPtrMem) \
     ((a_u16Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U32(a_u32Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U32(a_u32Dst, a_GCPtrMem) \
     ((a_u32Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U64(a_u64Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U64(a_u64Dst, a_GCPtrMem) \
     ((a_u64Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U32(a_u32Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U32(a_u32Dst, a_GCPtrMem) \
     ((a_u32Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U64(a_u64Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U64(a_u64Dst, a_GCPtrMem) \
     ((a_u64Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U32_ZX_U64(a_u64Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U32_ZX_U64(a_u64Dst, a_GCPtrMem) \
     ((a_u64Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
-#endif /* IEM_WITH_SETJMP */
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint8_t u8Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u16Dst) = (int8_t)u8Tmp; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint8_t u8Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u32Dst) = (int8_t)u8Tmp; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint8_t u8Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u64Dst) = (int8_t)u8Tmp; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint16_t u16Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u32Dst) = (int16_t)u16Tmp; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint16_t u16Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u64Dst) = (int16_t)u16Tmp; \
-    } while (0)
-# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
-    do { \
-        uint32_t u32Tmp; \
-        IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
-        (a_u64Dst) = (int32_t)u32Tmp; \
-    } while (0)
-#else  /* IEM_WITH_SETJMP */
-# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
+
+#define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
     ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
     ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
     ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
     ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
     ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
     ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
 
-# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U16(a_u16Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U8_SX_U16(a_u16Dst, a_GCPtrMem) \
     ((a_u16Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U32(a_u32Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U8_SX_U32(a_u32Dst, a_GCPtrMem) \
     ((a_u32Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U64(a_u64Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U8_SX_U64(a_u64Dst, a_GCPtrMem) \
     ((a_u64Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U16_SX_U32(a_u32Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U16_SX_U32(a_u32Dst, a_GCPtrMem) \
     ((a_u32Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U16_SX_U64(a_u64Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U16_SX_U64(a_u64Dst, a_GCPtrMem) \
     ((a_u64Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
-# define IEM_MC_FETCH_MEM_FLAT_U32_SX_U64(a_u64Dst, a_GCPtrMem) \
+#define IEM_MC_FETCH_MEM_FLAT_U32_SX_U64(a_u64Dst, a_GCPtrMem) \
     ((a_u64Dst) = (int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
-#endif /* IEM_WITH_SETJMP */
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
-# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
-# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
-# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
-#else
-# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
+
+#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
     iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
-# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
+#define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
     iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
-# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
+#define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
     iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
-# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
+#define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
     iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
 
-# define IEM_MC_STORE_MEM_FLAT_U8(a_GCPtrMem, a_u8Value) \
+#define IEM_MC_STORE_MEM_FLAT_U8(a_GCPtrMem, a_u8Value) \
     iemMemFlatStoreDataU8Jmp(pVCpu, (a_GCPtrMem), (a_u8Value))
-# define IEM_MC_STORE_MEM_FLAT_U16(a_GCPtrMem, a_u16Value) \
+#define IEM_MC_STORE_MEM_FLAT_U16(a_GCPtrMem, a_u16Value) \
     iemMemFlatStoreDataU16Jmp(pVCpu, (a_GCPtrMem), (a_u16Value))
-# define IEM_MC_STORE_MEM_FLAT_U32(a_GCPtrMem, a_u32Value) \
+#define IEM_MC_STORE_MEM_FLAT_U32(a_GCPtrMem, a_u32Value) \
     iemMemFlatStoreDataU32Jmp(pVCpu, (a_GCPtrMem), (a_u32Value))
-# define IEM_MC_STORE_MEM_FLAT_U64(a_GCPtrMem, a_u64Value) \
+#define IEM_MC_STORE_MEM_FLAT_U64(a_GCPtrMem, a_u64Value) \
     iemMemFlatStoreDataU64Jmp(pVCpu, (a_GCPtrMem), (a_u64Value))
-#endif
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
-# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
-# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
-# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
-#else
-# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
+
+#define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
     iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
-# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
+#define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
     iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
-# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
+#define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
     iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
-# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
+#define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
     iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
 
-# define IEM_MC_STORE_MEM_FLAT_U8_CONST(a_GCPtrMem, a_u8C) \
+#define IEM_MC_STORE_MEM_FLAT_U8_CONST(a_GCPtrMem, a_u8C) \
     iemMemFlatStoreDataU8Jmp(pVCpu, (a_GCPtrMem), (a_u8C))
-# define IEM_MC_STORE_MEM_FLAT_U16_CONST(a_GCPtrMem, a_u16C) \
+#define IEM_MC_STORE_MEM_FLAT_U16_CONST(a_GCPtrMem, a_u16C) \
     iemMemFlatStoreDataU16Jmp(pVCpu, (a_GCPtrMem), (a_u16C))
-# define IEM_MC_STORE_MEM_FLAT_U32_CONST(a_GCPtrMem, a_u32C) \
+#define IEM_MC_STORE_MEM_FLAT_U32_CONST(a_GCPtrMem, a_u32C) \
     iemMemFlatStoreDataU32Jmp(pVCpu, (a_GCPtrMem), (a_u32C))
-# define IEM_MC_STORE_MEM_FLAT_U64_CONST(a_GCPtrMem, a_u64C) \
+#define IEM_MC_STORE_MEM_FLAT_U64_CONST(a_GCPtrMem, a_u64C) \
     iemMemFlatStoreDataU64Jmp(pVCpu, (a_GCPtrMem), (a_u64C))
-#endif
 
 #define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst,  a_i8C)     *(a_pi8Dst)  = (a_i8C)
@@ -1575,102 +1332,56 @@
     } while (0)
 
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u128Value)))
-# define IEM_MC_STORE_MEM_U128_NO_AC(a_iSeg, a_GCPtrMem, a_u128Value) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128NoAc(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u128Value)))
-# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
-#else
-# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
+#define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
     iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u128Value))
-# define IEM_MC_STORE_MEM_U128_NO_AC(a_iSeg, a_GCPtrMem, a_u128Value) \
+#define IEM_MC_STORE_MEM_U128_NO_AC(a_iSeg, a_GCPtrMem, a_u128Value) \
     iemMemStoreDataU128NoAcJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u128Value))
-# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
+#define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
     iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
 
-# define IEM_MC_STORE_MEM_FLAT_U128(a_GCPtrMem, a_u128Value) \
+#define IEM_MC_STORE_MEM_FLAT_U128(a_GCPtrMem, a_u128Value) \
     iemMemFlatStoreDataU128Jmp(pVCpu, (a_GCPtrMem), &(a_u128Value))
-# define IEM_MC_STORE_MEM_FLAT_U128_NO_AC(a_GCPtrMem, a_u128Value) \
+#define IEM_MC_STORE_MEM_FLAT_U128_NO_AC(a_GCPtrMem, a_u128Value) \
     iemMemFlatStoreDataU128NoAcJmp(pVCpu, (a_GCPtrMem), &(a_u128Value))
-# define IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE(a_GCPtrMem, a_u128Value) \
+#define IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE(a_GCPtrMem, a_u128Value) \
     iemMemStoreDataU128AlignedSseJmp(pVCpu, UINT8_MAX, (a_GCPtrMem), (a_u128Value))
-#endif
-
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
-# define IEM_MC_STORE_MEM_U256_NO_AC(a_iSeg, a_GCPtrMem, a_u256Value) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256NoAc(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
-# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
-#else
-# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
+
+#define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
     iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
-# define IEM_MC_STORE_MEM_U256_NO_AC(a_iSeg, a_GCPtrMem, a_u256Value) \
+#define IEM_MC_STORE_MEM_U256_NO_AC(a_iSeg, a_GCPtrMem, a_u256Value) \
     iemMemStoreDataU256NoAcJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
-# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
+#define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
     iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
 
-# define IEM_MC_STORE_MEM_FLAT_U256(a_GCPtrMem, a_u256Value) \
+#define IEM_MC_STORE_MEM_FLAT_U256(a_GCPtrMem, a_u256Value) \
     iemMemFlatStoreDataU256Jmp(pVCpu, (a_GCPtrMem), &(a_u256Value))
-# define IEM_MC_STORE_MEM_FLAT_U256_NO_AC(a_GCPtrMem, a_u256Value) \
+#define IEM_MC_STORE_MEM_FLAT_U256_NO_AC(a_GCPtrMem, a_u256Value) \
     iemMemFlatStoreDataU256NoAcJmp(pVCpu, (a_GCPtrMem), &(a_u256Value))
-# define IEM_MC_STORE_MEM_FLAT_U256_ALIGN_AVX(a_GCPtrMem, a_u256Value) \
+#define IEM_MC_STORE_MEM_FLAT_U256_ALIGN_AVX(a_GCPtrMem, a_u256Value) \
     iemMemFlatStoreDataU256AlignedAvxJmp(pVCpu, (a_GCPtrMem), &(a_u256Value))
-#endif
 
 /* Regular stack push and pop: */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_PUSH_U16(a_u16Value)            IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
-# define IEM_MC_PUSH_U32(a_u32Value)            IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
-# define IEM_MC_PUSH_U32_SREG(a_uSegVal)        IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_uSegVal)))
-# define IEM_MC_PUSH_U64(a_u64Value)            IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
-
-# define IEM_MC_POP_GREG_U16(a_iGReg)           IEM_MC_RETURN_ON_FAILURE(iemMemStackPopGRegU16(pVCpu, (a_iGReg)))
-# define IEM_MC_POP_GREG_U32(a_iGReg)           IEM_MC_RETURN_ON_FAILURE(iemMemStackPopGRegU32(pVCpu, (a_iGReg)))
-# define IEM_MC_POP_GREG_U64(a_iGReg)           IEM_MC_RETURN_ON_FAILURE(iemMemStackPopGRegU64(pVCpu, (a_iGReg)))
-#else
-# define IEM_MC_PUSH_U16(a_u16Value)            iemMemStackPushU16Jmp(pVCpu, (a_u16Value))
-# define IEM_MC_PUSH_U32(a_u32Value)            iemMemStackPushU32Jmp(pVCpu, (a_u32Value))
-# define IEM_MC_PUSH_U32_SREG(a_uSegVal)        iemMemStackPushU32SRegJmp(pVCpu, (a_uSegVal))
-# define IEM_MC_PUSH_U64(a_u64Value)            iemMemStackPushU64Jmp(pVCpu, (a_u64Value))
-
-# define IEM_MC_POP_GREG_U16(a_iGReg)           iemMemStackPopGRegU16Jmp(pVCpu, (a_iGReg))
-# define IEM_MC_POP_GREG_U32(a_iGReg)           iemMemStackPopGRegU32Jmp(pVCpu, (a_iGReg))
-# define IEM_MC_POP_GREG_U64(a_iGReg)           iemMemStackPopGRegU64Jmp(pVCpu, (a_iGReg))
-#endif
+#define IEM_MC_PUSH_U16(a_u16Value)             iemMemStackPushU16Jmp(pVCpu, (a_u16Value))
+#define IEM_MC_PUSH_U32(a_u32Value)             iemMemStackPushU32Jmp(pVCpu, (a_u32Value))
+#define IEM_MC_PUSH_U32_SREG(a_uSegVal)         iemMemStackPushU32SRegJmp(pVCpu, (a_uSegVal))
+#define IEM_MC_PUSH_U64(a_u64Value)             iemMemStackPushU64Jmp(pVCpu, (a_u64Value))
+
+#define IEM_MC_POP_GREG_U16(a_iGReg)            iemMemStackPopGRegU16Jmp(pVCpu, (a_iGReg))
+#define IEM_MC_POP_GREG_U32(a_iGReg)            iemMemStackPopGRegU32Jmp(pVCpu, (a_iGReg))
+#define IEM_MC_POP_GREG_U64(a_iGReg)            iemMemStackPopGRegU64Jmp(pVCpu, (a_iGReg))
 
 /* 32-bit flat stack push and pop: */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FLAT32_PUSH_U16(a_u16Value)     IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
-# define IEM_MC_FLAT32_PUSH_U32(a_u32Value)     IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
-# define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_uSegVal)))
-
-# define IEM_MC_FLAT32_POP_GREG_U16(a_iGReg)    IEM_MC_RETURN_ON_FAILURE(iemMemStackPopGRegU16(pVCpu, (a_iGReg)))
-# define IEM_MC_FLAT32_POP_GREG_U32(a_iGReg)    IEM_MC_RETURN_ON_FAILURE(iemMemStackPopGRegU32(pVCpu, (a_iGReg)))
-#else
-# define IEM_MC_FLAT32_PUSH_U16(a_u16Value)     iemMemFlat32StackPushU16Jmp(pVCpu, (a_u16Value))
-# define IEM_MC_FLAT32_PUSH_U32(a_u32Value)     iemMemFlat32StackPushU32Jmp(pVCpu, (a_u32Value))
-# define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal) iemMemFlat32StackPushU32SRegJmp(pVCpu, (a_uSegVal))
-
-# define IEM_MC_FLAT32_POP_GREG_U16(a_iGReg)    iemMemFlat32StackPopGRegU16Jmp(pVCpu, a_iGReg))
-# define IEM_MC_FLAT32_POP_GREG_U32(a_iGReg)    iemMemFlat32StackPopGRegU32Jmp(pVCpu, a_iGReg))
-#endif
+#define IEM_MC_FLAT32_PUSH_U16(a_u16Value)      iemMemFlat32StackPushU16Jmp(pVCpu, (a_u16Value))
+#define IEM_MC_FLAT32_PUSH_U32(a_u32Value)      iemMemFlat32StackPushU32Jmp(pVCpu, (a_u32Value))
+#define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal)  iemMemFlat32StackPushU32SRegJmp(pVCpu, (a_uSegVal))
+
+#define IEM_MC_FLAT32_POP_GREG_U16(a_iGReg)     iemMemFlat32StackPopGRegU16Jmp(pVCpu, a_iGReg))
+#define IEM_MC_FLAT32_POP_GREG_U32(a_iGReg)     iemMemFlat32StackPopGRegU32Jmp(pVCpu, a_iGReg))
 
 /* 64-bit flat stack push and pop: */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_FLAT64_PUSH_U16(a_u16Value)     IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
-# define IEM_MC_FLAT64_PUSH_U64(a_u64Value)     IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
-
-# define IEM_MC_FLAT64_POP_GREG_U16(a_iGReg)    IEM_MC_RETURN_ON_FAILURE(iemMemStackPopGRegU16(pVCpu, (a_iGReg)))
-# define IEM_MC_FLAT64_POP_GREG_U64(a_iGReg)    IEM_MC_RETURN_ON_FAILURE(iemMemStackPopGRegU64(pVCpu, (a_iGReg)))
-#else
-# define IEM_MC_FLAT64_PUSH_U16(a_u16Value)     iemMemFlat64StackPushU16Jmp(pVCpu, (a_u16Value))
-# define IEM_MC_FLAT64_PUSH_U64(a_u64Value)     iemMemFlat64StackPushU64Jmp(pVCpu, (a_u64Value))
-
-# define IEM_MC_FLAT64_POP_GREG_U16(a_iGReg)    iemMemFlat64StackPopGRegU16Jmp(pVCpu, (a_iGReg))
-# define IEM_MC_FLAT64_POP_GREG_U64(a_iGReg)    iemMemFlat64StackPopGRegU64Jmp(pVCpu, (a_iGReg))
-#endif
+#define IEM_MC_FLAT64_PUSH_U16(a_u16Value)      iemMemFlat64StackPushU16Jmp(pVCpu, (a_u16Value))
+#define IEM_MC_FLAT64_PUSH_U64(a_u64Value)      iemMemFlat64StackPushU64Jmp(pVCpu, (a_u64Value))
+
+#define IEM_MC_FLAT64_POP_GREG_U16(a_iGReg)     iemMemFlat64StackPopGRegU16Jmp(pVCpu, (a_iGReg))
+#define IEM_MC_FLAT64_POP_GREG_U64(a_iGReg)     iemMemFlat64StackPopGRegU64Jmp(pVCpu, (a_iGReg))
 
 
@@ -1688,12 +1399,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U8_ATOMIC(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_ATOMIC, 0))
-#else
-# define IEM_MC_MEM_MAP_U8_ATOMIC(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U8_ATOMIC(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu8Mem) = iemMemMapDataU8AtJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -1707,12 +1412,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RW
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_RW, 0))
-#else
-# define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu8Mem) = iemMemMapDataU8RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -1726,12 +1425,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, 0))
-#else
-# define IEM_MC_MEM_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu8Mem) = iemMemMapDataU8WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -1745,12 +1438,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_R, 0))
-#else
-# define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu8Mem) = iemMemMapDataU8RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -1764,12 +1451,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U8_ATOMIC(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_ATOMIC, 0))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U8_ATOMIC(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U8_ATOMIC(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu8Mem) = iemMemFlatMapDataU8AtJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -1783,12 +1464,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RW
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_RW, 0))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu8Mem) = iemMemFlatMapDataU8RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -1802,12 +1477,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, 0))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu8Mem) = iemMemFlatMapDataU8WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -1821,12 +1490,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_R, 0))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu8Mem) = iemMemFlatMapDataU8RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 
@@ -1843,12 +1506,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U16_ATOMIC(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_ATOMIC, sizeof(uint16_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U16_ATOMIC(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U16_ATOMIC(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu16Mem) = iemMemMapDataU16AtJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -1862,12 +1519,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RW
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint16_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu16Mem) = iemMemMapDataU16RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -1881,12 +1532,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu16Mem) = iemMemMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -1900,12 +1545,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint16_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu16Mem) = iemMemMapDataU16RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -1919,12 +1558,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U16_ATOMIC(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_ATOMIC, sizeof(uint16_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U16_ATOMIC(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U16_ATOMIC(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu16Mem) = iemMemFlatMapDataU16AtJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -1938,12 +1571,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RW
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint16_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu16Mem) = iemMemFlatMapDataU16RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -1957,12 +1584,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu16Mem) = iemMemFlatMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -1976,30 +1597,14 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
-   IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), UINT8_MAX, \
-                                      (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint16_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu16Mem) = iemMemFlatMapDataU16RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /** int16_t alias. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-         IEM_MC_MEM_MAP_U16_WO(a_pi16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem)
-#else
-# define IEM_MC_MEM_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pi16Mem) = (int16_t *)iemMemMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /** Flat int16_t alias. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_GCPtrMem) \
-         IEM_MC_MEM_FLAT_MAP_U16_WO(a_pi16Mem, a_bUnmapInfo, a_GCPtrMem)
-#else
-# define IEM_MC_MEM_FLAT_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pi16Mem) = (int16_t *)iemMemFlatMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 
@@ -2016,12 +1621,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U32_ATOMIC(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_ATOMIC, sizeof(uint32_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U32_ATOMIC(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U32_ATOMIC(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu32Mem) = iemMemMapDataU32AtJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2035,12 +1634,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RW
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint32_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu32Mem) = iemMemMapDataU32RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2054,12 +1647,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu32Mem) = iemMemMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2073,12 +1660,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint32_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu32Mem) = iemMemMapDataU32RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2092,12 +1673,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U32_ATOMIC(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_ATOMIC, sizeof(uint32_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U32_ATOMIC(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U32_ATOMIC(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu32Mem) = iemMemFlatMapDataU32AtJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -2111,12 +1686,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RW
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint32_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu32Mem) = iemMemFlatMapDataU32RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -2130,12 +1699,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu32Mem) = iemMemFlatMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -2149,48 +1712,22 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint32_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu32Mem) = iemMemFlatMapDataU32RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /** int32_t alias. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-         IEM_MC_MEM_MAP_U32_WO(a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem)
-#else
-# define IEM_MC_MEM_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pi32Mem) = (int32_t *)iemMemMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /** Flat int32_t alias. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_GCPtrMem) \
-         IEM_MC_MEM_FLAT_MAP_U32_WO(a_pi32Mem, a_bUnmapInfo, a_GCPtrMem)
-#else
-# define IEM_MC_MEM_FLAT_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pi32Mem) = (int32_t *)iemMemFlatMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /** RTFLOAT32U alias. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-         IEM_MC_MEM_MAP_U32_WO(a_pr32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem)
-#else
-# define IEM_MC_MEM_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pr32Mem) = (PRTFLOAT32U)iemMemMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /** Flat RTFLOAT32U alias. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_GCPtrMem) \
-         IEM_MC_MEM_FLAT_MAP_U32_WO(a_pr32Mem, a_bUnmapInfo, a_GCPtrMem)
-#else
-# define IEM_MC_MEM_FLAT_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pr32Mem) = (PRTFLOAT32U)iemMemFlatMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 
@@ -2207,12 +1744,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U64_ATOMIC(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_ATOMIC, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U64_ATOMIC(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U64_ATOMIC(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu64Mem) = iemMemMapDataU64AtJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2226,12 +1757,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RW
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu64Mem) = iemMemMapDataU64RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2245,12 +1770,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu64Mem) = iemMemMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2264,12 +1783,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu64Mem) = iemMemMapDataU64RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2283,12 +1796,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U64_ATOMIC(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_ATOMIC, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U64_ATOMIC(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U64_ATOMIC(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu64Mem) = iemMemFlatMapDataU64AtJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -2302,12 +1809,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RW
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu64Mem) = iemMemFlatMapDataU64RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -2321,12 +1822,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu64Mem) = iemMemFlatMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -2340,48 +1835,22 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu64Mem) = iemMemFlatMapDataU64RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /** int64_t alias. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-         IEM_MC_MEM_MAP_U64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem)
-#else
-# define IEM_MC_MEM_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pi64Mem) = (int64_t *)iemMemMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /** Flat int64_t alias. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem) \
-         IEM_MC_MEM_FLAT_MAP_U64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem)
-#else
-# define IEM_MC_MEM_FLAT_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pi64Mem) = (int64_t *)iemMemFlatMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /** RTFLOAT64U alias. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-         IEM_MC_MEM_MAP_U64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem)
-#else
-# define IEM_MC_MEM_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pr64Mem) = (PRTFLOAT64U)iemMemMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /** Flat RTFLOAT64U alias. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_GCPtrMem) \
-         IEM_MC_MEM_FLAT_MAP_U64_WO(a_pr64Mem, a_bUnmapInfo, a_GCPtrMem)
-#else
-# define IEM_MC_MEM_FLAT_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pr64Mem) = (PRTFLOAT64U)iemMemFlatMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 
@@ -2398,12 +1867,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U128_ATOMIC(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128U), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_ATOMIC, sizeof(RTUINT128U) - 1))
-#else
-# define IEM_MC_MEM_MAP_U128_ATOMIC(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U128_ATOMIC(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu128Mem) = iemMemMapDataU128AtJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2417,12 +1880,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RW
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128U), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(RTUINT128U) - 1))
-#else
-# define IEM_MC_MEM_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu128Mem) = iemMemMapDataU128RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2436,12 +1893,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(RTUINT128) - 1))
-#else
-# define IEM_MC_MEM_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu128Mem) = iemMemMapDataU128WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2455,12 +1906,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(RTUINT128) - 1))
-#else
-# define IEM_MC_MEM_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pu128Mem) = iemMemMapDataU128RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2474,12 +1919,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U128_ATOMIC(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_ATOMIC, sizeof(RTUINT128) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U128_ATOMIC(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U128_ATOMIC(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu128Mem) = iemMemFlatMapDataU128AtJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -2493,12 +1932,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RW
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(RTUINT128) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu128Mem) = iemMemFlatMapDataU128RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -2512,12 +1945,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(RTUINT128) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu128Mem) = iemMemFlatMapDataU128WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 /**
@@ -2531,12 +1958,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_RO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(RTUINT128) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pu128Mem) = iemMemFlatMapDataU128RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 
@@ -2553,12 +1974,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pr80Mem), &(a_bUnmapInfo), sizeof(RTFLOAT80U), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pr80Mem) = iemMemMapDataR80WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2571,12 +1986,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pr80Mem), &(a_bUnmapInfo), sizeof(RTFLOAT80U), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pr80Mem) = iemMemFlatMapDataR80WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 
@@ -2591,12 +2000,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pd80Mem), &(a_bUnmapInfo), sizeof(RTFLOAT80U), (a_iSeg), \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
+#define IEM_MC_MEM_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
     (a_pd80Mem) = iemMemMapDataD80WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
-#endif
 
 /**
@@ -2609,12 +2012,6 @@
  * @see     IEM_MC_MEM_COMMIT_AND_UNMAP_WO
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_FLAT_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_GCPtrMem) \
-    IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pd80Mem), &(a_bUnmapInfo), sizeof(RTFLOAT80U), UINT8_MAX, \
-                                       (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
-#else
-# define IEM_MC_MEM_FLAT_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_GCPtrMem) \
+#define IEM_MC_MEM_FLAT_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_GCPtrMem) \
     (a_pd80Mem) = iemMemFlatMapDataD80WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
-#endif
 
 
@@ -2626,9 +2023,5 @@
  * @note        Implictly frees the a_bMapInfo variable.
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_bMapInfo)         IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, a_bMapInfo))
-#else
-# define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_bMapInfo)         iemMemCommitAndUnmapRwJmp(pVCpu, (a_bMapInfo))
-#endif
+#define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_bMapInfo)          iemMemCommitAndUnmapRwJmp(pVCpu, (a_bMapInfo))
 
 /** Commits the memory and unmaps guest memory previously mapped ATOMIC.
@@ -2636,9 +2029,5 @@
  * @note        Implictly frees the a_bMapInfo variable.
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(a_bMapInfo)     IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, a_bMapInfo))
-#else
-# define IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(a_bMapInfo)     iemMemCommitAndUnmapRwJmp(pVCpu, (a_bMapInfo))
-#endif
+#define IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(a_bMapInfo)      iemMemCommitAndUnmapRwJmp(pVCpu, (a_bMapInfo))
 
 /** Commits the memory and unmaps guest memory previously mapped W.
@@ -2646,9 +2035,5 @@
  * @note        Implictly frees the a_bMapInfo variable.
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_COMMIT_AND_UNMAP_WO(a_bMapInfo)         IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, a_bMapInfo))
-#else
-# define IEM_MC_MEM_COMMIT_AND_UNMAP_WO(a_bMapInfo)         iemMemCommitAndUnmapWoJmp(pVCpu, (a_bMapInfo))
-#endif
+#define IEM_MC_MEM_COMMIT_AND_UNMAP_WO(a_bMapInfo)          iemMemCommitAndUnmapWoJmp(pVCpu, (a_bMapInfo))
 
 /** Commits the memory and unmaps guest memory previously mapped R.
@@ -2656,9 +2041,5 @@
  * @note        Implictly frees the a_bMapInfo variable.
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_COMMIT_AND_UNMAP_RO(a_bMapInfo)         IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, a_bMapInfo))
-#else
-# define IEM_MC_MEM_COMMIT_AND_UNMAP_RO(a_bMapInfo)         iemMemCommitAndUnmapRoJmp(pVCpu, (a_bMapInfo))
-#endif
+#define IEM_MC_MEM_COMMIT_AND_UNMAP_RO(a_bMapInfo)          iemMemCommitAndUnmapRoJmp(pVCpu, (a_bMapInfo))
 
 
@@ -2673,15 +2054,5 @@
  * @note        Implictly frees both the a_bMapInfo and a_u16FSW variables.
  */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE_WO(a_bMapInfo, a_u16FSW) do { \
-        if (   !(a_u16FSW & X86_FSW_ES) \
-            || !(  (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
-                 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
-            IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, a_bMapInfo)); \
-        else \
-            iemMemRollbackAndUnmap(pVCpu, (a_pvMem), IEM_ACCESS_DATA_W); \
-    } while (0)
-#else
-# define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE_WO(a_bMapInfo, a_u16FSW) do { \
+#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE_WO(a_bMapInfo, a_u16FSW) do { \
         if (   !(a_u16FSW & X86_FSW_ES) \
             || !(  (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
@@ -2691,24 +2062,14 @@
             iemMemRollbackAndUnmapWo(pVCpu, a_bMapInfo); \
     } while (0)
-#endif
 
 /** Rolls back (conceptually only, assumes no writes) and unmaps the guest memory.
  * @note        Implictly frees the a_bMapInfo variable. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO(a_bMapInfo)       iemMemRollbackAndUnmap(pVCpu, a_bMapInfo)
-#else
-# define IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO(a_bMapInfo)       iemMemRollbackAndUnmapWo(pVCpu, a_bMapInfo)
-#endif
+#define IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO(a_bMapInfo)        iemMemRollbackAndUnmapWo(pVCpu, a_bMapInfo)
 
 
 
 /** Calculate efficient address from R/M. */
-#ifndef IEM_WITH_SETJMP
-# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
-    IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &(a_GCPtrEff)))
-#else
-# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
+#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
     ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (a_bRm), (a_cbImmAndRspOffset)))
-#endif
 
 
