Changeset 108313 in vbox
- Timestamp:
- Feb 20, 2025 3:41:00 PM (3 weeks ago)
- svn:sync-xref-src-repo-rev:
- 167657
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 7 edited
-
VMMAll/IEMAllInstPython.py (modified) (1 diff)
-
VMMAll/target-x86/IEMAllInstOneByte-x86.cpp.h (modified) (30 diffs)
-
VMMAll/target-x86/IEMAllInstTwoByte0f-x86.cpp.h (modified) (86 diffs)
-
VMMAll/target-x86/IEMAllN8veLiveness-x86.h (modified) (1 diff)
-
VMMAll/target-x86/IEMAllN8veRecompFuncs-x86.h (modified) (10 diffs)
-
include/IEMMc.h (modified) (1 diff)
-
testcase/tstIEMCheckMc.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r108299 r108313 3225 3225 'IEM_MC_IF_ECX_IS_NOT_ONE_AND_EFL_BIT_NOT_SET': (McBlock.parseMcGenericCond, True, False, True, ), 3226 3226 'IEM_MC_IF_ECX_IS_NOT_ONE_AND_EFL_BIT_SET': (McBlock.parseMcGenericCond, True, False, True, ), 3227 'IEM_MC_IF_ EFL_ANY_BITS_SET':(McBlock.parseMcGenericCond, True, False, True, ),3228 'IEM_MC_IF_ EFL_BIT_NOT_SET':(McBlock.parseMcGenericCond, True, False, True, ),3229 'IEM_MC_IF_ EFL_BIT_NOT_SET_AND_BITS_EQ':(McBlock.parseMcGenericCond, True, False, True, ),3230 'IEM_MC_IF_ EFL_BIT_SET':(McBlock.parseMcGenericCond, True, False, True, ),3231 'IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE':(McBlock.parseMcGenericCond, True, False, True, ),3232 'IEM_MC_IF_ EFL_BITS_EQ':(McBlock.parseMcGenericCond, True, False, True, ),3233 'IEM_MC_IF_ EFL_BITS_NE':(McBlock.parseMcGenericCond, True, False, True, ),3234 'IEM_MC_IF_ EFL_NO_BITS_SET':(McBlock.parseMcGenericCond, True, False, True, ),3227 'IEM_MC_IF_FLAGS_ANY_BITS_SET': (McBlock.parseMcGenericCond, True, False, True, ), 3228 'IEM_MC_IF_FLAGS_BIT_NOT_SET': (McBlock.parseMcGenericCond, True, False, True, ), 3229 'IEM_MC_IF_FLAGS_BIT_NOT_SET_AND_BITS_EQ': (McBlock.parseMcGenericCond, True, False, True, ), 3230 'IEM_MC_IF_FLAGS_BIT_SET': (McBlock.parseMcGenericCond, True, False, True, ), 3231 'IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE': (McBlock.parseMcGenericCond, True, False, True, ), 3232 'IEM_MC_IF_FLAGS_BITS_EQ': (McBlock.parseMcGenericCond, True, False, True, ), 3233 'IEM_MC_IF_FLAGS_BITS_NE': (McBlock.parseMcGenericCond, True, False, True, ), 3234 'IEM_MC_IF_FLAGS_NO_BITS_SET': (McBlock.parseMcGenericCond, True, False, True, ), 3235 3235 'IEM_MC_IF_FCW_IM': (McBlock.parseMcGenericCond, True, True, False, ), 3236 3236 'IEM_MC_IF_FPUREG_IS_EMPTY': (McBlock.parseMcGenericCond, True, True, False, ), -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstOneByte-x86.cpp.h
r108296 r108313 4071 4071 IEM_MC_BEGIN(0, 0); 4072 4072 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4073 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF) {4073 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF) { 4074 4074 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4075 4075 } IEM_MC_ELSE() { … … 4092 4092 IEM_MC_BEGIN(0, 0); 4093 4093 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4094 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF) {4094 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF) { 4095 4095 IEM_MC_ADVANCE_PC_AND_FINISH(); 4096 4096 } IEM_MC_ELSE() { … … 4112 4112 IEM_MC_BEGIN(0, 0); 4113 4113 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4114 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {4114 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 4115 4115 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4116 4116 } IEM_MC_ELSE() { … … 4133 4133 IEM_MC_BEGIN(0, 0); 4134 4134 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4135 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {4135 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 4136 4136 IEM_MC_ADVANCE_PC_AND_FINISH(); 4137 4137 } IEM_MC_ELSE() { … … 4154 4154 IEM_MC_BEGIN(0, 0); 4155 4155 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4156 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {4156 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 4157 4157 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4158 4158 } IEM_MC_ELSE() { … … 4175 4175 IEM_MC_BEGIN(0, 0); 4176 4176 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4177 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {4177 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 4178 4178 IEM_MC_ADVANCE_PC_AND_FINISH(); 4179 4179 } IEM_MC_ELSE() { … … 4196 4196 IEM_MC_BEGIN(0, 0); 4197 4197 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4198 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {4198 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 4199 4199 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4200 4200 } IEM_MC_ELSE() { … … 4217 4217 IEM_MC_BEGIN(0, 0); 4218 4218 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4219 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {4219 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 4220 4220 IEM_MC_ADVANCE_PC_AND_FINISH(); 4221 4221 } IEM_MC_ELSE() { … … 4238 4238 IEM_MC_BEGIN(0, 0); 4239 4239 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4240 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF) {4240 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF) { 4241 4241 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4242 4242 } IEM_MC_ELSE() { … … 4259 4259 IEM_MC_BEGIN(0, 0); 4260 4260 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4261 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF) {4261 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF) { 4262 4262 IEM_MC_ADVANCE_PC_AND_FINISH(); 4263 4263 } IEM_MC_ELSE() { … … 4280 4280 IEM_MC_BEGIN(0, 0); 4281 4281 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4282 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {4282 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 4283 4283 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4284 4284 } IEM_MC_ELSE() { … … 4301 4301 IEM_MC_BEGIN(0, 0); 4302 4302 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4303 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {4303 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 4304 4304 IEM_MC_ADVANCE_PC_AND_FINISH(); 4305 4305 } IEM_MC_ELSE() { … … 4322 4322 IEM_MC_BEGIN(0, 0); 4323 4323 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4324 IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {4324 IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 4325 4325 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4326 4326 } IEM_MC_ELSE() { … … 4343 4343 IEM_MC_BEGIN(0, 0); 4344 4344 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4345 IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {4345 IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 4346 4346 IEM_MC_ADVANCE_PC_AND_FINISH(); 4347 4347 } IEM_MC_ELSE() { … … 4364 4364 IEM_MC_BEGIN(0, 0); 4365 4365 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4366 IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {4366 IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 4367 4367 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4368 4368 } IEM_MC_ELSE() { … … 4385 4385 IEM_MC_BEGIN(0, 0); 4386 4386 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4387 IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {4387 IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 4388 4388 IEM_MC_ADVANCE_PC_AND_FINISH(); 4389 4389 } IEM_MC_ELSE() { … … 7404 7404 IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xDI); \ 7405 7405 IEM_MC_STORE_MEM_SEG_U##ValBits(X86_SREG_ES, uAddr, uValue); \ 7406 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_DF) { \7406 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_DF) { \ 7407 7407 IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \ 7408 7408 IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \ … … 7612 7612 \ 7613 7613 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 7614 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_DF) { \7614 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_DF) { \ 7615 7615 IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \ 7616 7616 IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \ … … 7937 7937 IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xDI); \ 7938 7938 IEM_MC_STORE_MEM_SEG_U##ValBits(X86_SREG_ES, uAddr, uValue); \ 7939 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_DF) { \7939 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_DF) { \ 7940 7940 IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \ 7941 7941 } IEM_MC_ELSE() { \ … … 8118 8118 IEM_MC_FETCH_MEM_SEG_U##ValBits(uValue, pVCpu->iem.s.iEffSeg, uAddr); \ 8119 8119 IEM_MC_STORE_GREG_U##ValBits(X86_GREG_xAX, uValue); \ 8120 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_DF) { \8120 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_DF) { \ 8121 8121 IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \ 8122 8122 } IEM_MC_ELSE() { \ … … 8319 8319 \ 8320 8320 IEM_MC_COMMIT_EFLAGS(fEFlagsRet);\ 8321 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_DF) { \8321 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_DF) { \ 8322 8322 IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \ 8323 8323 } IEM_MC_ELSE() { \ … … 10481 10481 IEM_MC_BEGIN(0, 0); 10482 10482 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 10483 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {10483 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 10484 10484 IEM_MC_STORE_GREG_U8_CONST(X86_GREG_xAX, 0xff); 10485 10485 } IEM_MC_ELSE() { … … 11696 11696 IEM_MC_PREPARE_FPU_USAGE(); 11697 11697 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, IEM_GET_MODRM_RM_8(bRm), 0) { 11698 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {11698 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 11699 11699 IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN); 11700 11700 } IEM_MC_ENDIF(); … … 11722 11722 IEM_MC_PREPARE_FPU_USAGE(); 11723 11723 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, IEM_GET_MODRM_RM_8(bRm), 0) { 11724 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {11724 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 11725 11725 IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN); 11726 11726 } IEM_MC_ENDIF(); … … 11748 11748 IEM_MC_PREPARE_FPU_USAGE(); 11749 11749 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, IEM_GET_MODRM_RM_8(bRm), 0) { 11750 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {11750 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 11751 11751 IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN); 11752 11752 } IEM_MC_ENDIF(); … … 11774 11774 IEM_MC_PREPARE_FPU_USAGE(); 11775 11775 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, IEM_GET_MODRM_RM_8(bRm), 0) { 11776 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {11776 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 11777 11777 IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN); 11778 11778 } IEM_MC_ENDIF(); … … 12253 12253 IEM_MC_PREPARE_FPU_USAGE(); 12254 12254 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, IEM_GET_MODRM_RM_8(bRm), 0) { 12255 IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_CF) {12255 IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_CF) { 12256 12256 IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN); 12257 12257 } IEM_MC_ENDIF(); … … 12279 12279 IEM_MC_PREPARE_FPU_USAGE(); 12280 12280 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, IEM_GET_MODRM_RM_8(bRm), 0) { 12281 IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_ZF) {12281 IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_ZF) { 12282 12282 IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN); 12283 12283 } IEM_MC_ENDIF(); … … 12305 12305 IEM_MC_PREPARE_FPU_USAGE(); 12306 12306 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, IEM_GET_MODRM_RM_8(bRm), 0) { 12307 IEM_MC_IF_ EFL_NO_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {12307 IEM_MC_IF_FLAGS_NO_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 12308 12308 IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN); 12309 12309 } IEM_MC_ENDIF(); … … 12331 12331 IEM_MC_PREPARE_FPU_USAGE(); 12332 12332 IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(pr80ValueN, IEM_GET_MODRM_RM_8(bRm), 0) { 12333 IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_PF) {12333 IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_PF) { 12334 12334 IEM_MC_STORE_FPUREG_R80_SRC_REF(0, pr80ValueN); 12335 12335 } IEM_MC_ENDIF(); -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstTwoByte0f-x86.cpp.h
r108296 r108313 5050 5050 { 5051 5051 IEMOP_MNEMONIC(cmovo_Gv_Ev, "cmovo Gv,Ev"); 5052 CMOV_X(IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF));5052 CMOV_X(IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF)); 5053 5053 } 5054 5054 … … 5061 5061 { 5062 5062 IEMOP_MNEMONIC(cmovno_Gv_Ev, "cmovno Gv,Ev"); 5063 CMOV_X(IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_OF));5063 CMOV_X(IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_OF)); 5064 5064 } 5065 5065 … … 5072 5072 { 5073 5073 IEMOP_MNEMONIC(cmovc_Gv_Ev, "cmovc Gv,Ev"); 5074 CMOV_X(IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF));5074 CMOV_X(IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF)); 5075 5075 } 5076 5076 … … 5083 5083 { 5084 5084 IEMOP_MNEMONIC(cmovnc_Gv_Ev, "cmovnc Gv,Ev"); 5085 CMOV_X(IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_CF));5085 CMOV_X(IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_CF)); 5086 5086 } 5087 5087 … … 5094 5094 { 5095 5095 IEMOP_MNEMONIC(cmove_Gv_Ev, "cmove Gv,Ev"); 5096 CMOV_X(IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF));5096 CMOV_X(IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF)); 5097 5097 } 5098 5098 … … 5105 5105 { 5106 5106 IEMOP_MNEMONIC(cmovne_Gv_Ev, "cmovne Gv,Ev"); 5107 CMOV_X(IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_ZF));5107 CMOV_X(IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_ZF)); 5108 5108 } 5109 5109 … … 5116 5116 { 5117 5117 IEMOP_MNEMONIC(cmovbe_Gv_Ev, "cmovbe Gv,Ev"); 5118 CMOV_X(IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF));5118 CMOV_X(IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF)); 5119 5119 } 5120 5120 … … 5127 5127 { 5128 5128 IEMOP_MNEMONIC(cmovnbe_Gv_Ev, "cmovnbe Gv,Ev"); 5129 CMOV_X(IEM_MC_IF_ EFL_NO_BITS_SET(X86_EFL_CF | X86_EFL_ZF));5129 CMOV_X(IEM_MC_IF_FLAGS_NO_BITS_SET(X86_EFL_CF | X86_EFL_ZF)); 5130 5130 } 5131 5131 … … 5138 5138 { 5139 5139 IEMOP_MNEMONIC(cmovs_Gv_Ev, "cmovs Gv,Ev"); 5140 CMOV_X(IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF));5140 CMOV_X(IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF)); 5141 5141 } 5142 5142 … … 5149 5149 { 5150 5150 IEMOP_MNEMONIC(cmovns_Gv_Ev, "cmovns Gv,Ev"); 5151 CMOV_X(IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_SF));5151 CMOV_X(IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_SF)); 5152 5152 } 5153 5153 … … 5160 5160 { 5161 5161 IEMOP_MNEMONIC(cmovp_Gv_Ev, "cmovp Gv,Ev"); 5162 CMOV_X(IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF));5162 CMOV_X(IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF)); 5163 5163 } 5164 5164 … … 5171 5171 { 5172 5172 IEMOP_MNEMONIC(cmovnp_Gv_Ev, "cmovnp Gv,Ev"); 5173 CMOV_X(IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_PF));5173 CMOV_X(IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_PF)); 5174 5174 } 5175 5175 … … 5182 5182 { 5183 5183 IEMOP_MNEMONIC(cmovl_Gv_Ev, "cmovl Gv,Ev"); 5184 CMOV_X(IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF));5184 CMOV_X(IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF)); 5185 5185 } 5186 5186 … … 5193 5193 { 5194 5194 IEMOP_MNEMONIC(cmovnl_Gv_Ev, "cmovnl Gv,Ev"); 5195 CMOV_X(IEM_MC_IF_ EFL_BITS_EQ(X86_EFL_SF, X86_EFL_OF));5195 CMOV_X(IEM_MC_IF_FLAGS_BITS_EQ(X86_EFL_SF, X86_EFL_OF)); 5196 5196 } 5197 5197 … … 5204 5204 { 5205 5205 IEMOP_MNEMONIC(cmovle_Gv_Ev, "cmovle Gv,Ev"); 5206 CMOV_X(IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF));5206 CMOV_X(IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF)); 5207 5207 } 5208 5208 … … 5215 5215 { 5216 5216 IEMOP_MNEMONIC(cmovnle_Gv_Ev, "cmovnle Gv,Ev"); 5217 CMOV_X(IEM_MC_IF_ EFL_BIT_NOT_SET_AND_BITS_EQ(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF));5217 CMOV_X(IEM_MC_IF_FLAGS_BIT_NOT_SET_AND_BITS_EQ(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF)); 5218 5218 } 5219 5219 … … 7578 7578 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7579 7579 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7580 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF) {7580 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF) { 7581 7581 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7582 7582 } IEM_MC_ELSE() { … … 7590 7590 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7591 7591 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7592 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF) {7592 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF) { 7593 7593 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7594 7594 } IEM_MC_ELSE() { … … 7614 7614 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7615 7615 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7616 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF) {7616 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF) { 7617 7617 IEM_MC_ADVANCE_PC_AND_FINISH(); 7618 7618 } IEM_MC_ELSE() { … … 7626 7626 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7627 7627 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7628 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF) {7628 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF) { 7629 7629 IEM_MC_ADVANCE_PC_AND_FINISH(); 7630 7630 } IEM_MC_ELSE() { … … 7650 7650 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7651 7651 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7652 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {7652 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 7653 7653 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7654 7654 } IEM_MC_ELSE() { … … 7662 7662 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7663 7663 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7664 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {7664 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 7665 7665 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7666 7666 } IEM_MC_ELSE() { … … 7686 7686 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7687 7687 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7688 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {7688 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 7689 7689 IEM_MC_ADVANCE_PC_AND_FINISH(); 7690 7690 } IEM_MC_ELSE() { … … 7698 7698 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7699 7699 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7700 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {7700 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 7701 7701 IEM_MC_ADVANCE_PC_AND_FINISH(); 7702 7702 } IEM_MC_ELSE() { … … 7722 7722 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7723 7723 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7724 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {7724 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 7725 7725 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7726 7726 } IEM_MC_ELSE() { … … 7734 7734 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7735 7735 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7736 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {7736 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 7737 7737 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7738 7738 } IEM_MC_ELSE() { … … 7758 7758 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7759 7759 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7760 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {7760 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 7761 7761 IEM_MC_ADVANCE_PC_AND_FINISH(); 7762 7762 } IEM_MC_ELSE() { … … 7770 7770 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7771 7771 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7772 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {7772 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 7773 7773 IEM_MC_ADVANCE_PC_AND_FINISH(); 7774 7774 } IEM_MC_ELSE() { … … 7794 7794 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7795 7795 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7796 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {7796 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 7797 7797 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7798 7798 } IEM_MC_ELSE() { … … 7806 7806 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7807 7807 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7808 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {7808 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 7809 7809 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7810 7810 } IEM_MC_ELSE() { … … 7830 7830 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7831 7831 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7832 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {7832 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 7833 7833 IEM_MC_ADVANCE_PC_AND_FINISH(); 7834 7834 } IEM_MC_ELSE() { … … 7842 7842 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7843 7843 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7844 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {7844 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 7845 7845 IEM_MC_ADVANCE_PC_AND_FINISH(); 7846 7846 } IEM_MC_ELSE() { … … 7866 7866 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7867 7867 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7868 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF) {7868 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF) { 7869 7869 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7870 7870 } IEM_MC_ELSE() { … … 7878 7878 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7879 7879 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7880 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF) {7880 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF) { 7881 7881 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7882 7882 } IEM_MC_ELSE() { … … 7902 7902 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7903 7903 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7904 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF) {7904 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF) { 7905 7905 IEM_MC_ADVANCE_PC_AND_FINISH(); 7906 7906 } IEM_MC_ELSE() { … … 7914 7914 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7915 7915 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7916 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF) {7916 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF) { 7917 7917 IEM_MC_ADVANCE_PC_AND_FINISH(); 7918 7918 } IEM_MC_ELSE() { … … 7938 7938 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7939 7939 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7940 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {7940 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 7941 7941 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7942 7942 } IEM_MC_ELSE() { … … 7950 7950 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7951 7951 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7952 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {7952 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 7953 7953 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7954 7954 } IEM_MC_ELSE() { … … 7974 7974 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 7975 7975 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7976 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {7976 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 7977 7977 IEM_MC_ADVANCE_PC_AND_FINISH(); 7978 7978 } IEM_MC_ELSE() { … … 7986 7986 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 7987 7987 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7988 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {7988 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 7989 7989 IEM_MC_ADVANCE_PC_AND_FINISH(); 7990 7990 } IEM_MC_ELSE() { … … 8010 8010 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 8011 8011 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8012 IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {8012 IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 8013 8013 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 8014 8014 } IEM_MC_ELSE() { … … 8022 8022 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 8023 8023 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8024 IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {8024 IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 8025 8025 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 8026 8026 } IEM_MC_ELSE() { … … 8046 8046 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 8047 8047 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8048 IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {8048 IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 8049 8049 IEM_MC_ADVANCE_PC_AND_FINISH(); 8050 8050 } IEM_MC_ELSE() { … … 8058 8058 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 8059 8059 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8060 IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {8060 IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 8061 8061 IEM_MC_ADVANCE_PC_AND_FINISH(); 8062 8062 } IEM_MC_ELSE() { … … 8082 8082 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 8083 8083 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8084 IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {8084 IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 8085 8085 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 8086 8086 } IEM_MC_ELSE() { … … 8094 8094 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 8095 8095 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8096 IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {8096 IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 8097 8097 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 8098 8098 } IEM_MC_ELSE() { … … 8118 8118 int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm); 8119 8119 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8120 IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {8120 IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 8121 8121 IEM_MC_ADVANCE_PC_AND_FINISH(); 8122 8122 } IEM_MC_ELSE() { … … 8130 8130 int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm); 8131 8131 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8132 IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {8132 IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 8133 8133 IEM_MC_ADVANCE_PC_AND_FINISH(); 8134 8134 } IEM_MC_ELSE() { … … 8158 8158 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8159 8159 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8160 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF) {8160 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF) { 8161 8161 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8162 8162 } IEM_MC_ELSE() { … … 8173 8173 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8174 8174 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8175 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF) {8175 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF) { 8176 8176 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8177 8177 } IEM_MC_ELSE() { … … 8202 8202 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8203 8203 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8204 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF) {8204 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF) { 8205 8205 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8206 8206 } IEM_MC_ELSE() { … … 8217 8217 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8218 8218 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8219 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_OF) {8219 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_OF) { 8220 8220 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8221 8221 } IEM_MC_ELSE() { … … 8246 8246 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8247 8247 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8248 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {8248 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 8249 8249 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8250 8250 } IEM_MC_ELSE() { … … 8261 8261 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8262 8262 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8263 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {8263 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 8264 8264 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8265 8265 } IEM_MC_ELSE() { … … 8290 8290 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8291 8291 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8292 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {8292 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 8293 8293 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8294 8294 } IEM_MC_ELSE() { … … 8305 8305 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8306 8306 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8307 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_CF) {8307 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_CF) { 8308 8308 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8309 8309 } IEM_MC_ELSE() { … … 8334 8334 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8335 8335 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8336 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {8336 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 8337 8337 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8338 8338 } IEM_MC_ELSE() { … … 8349 8349 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8350 8350 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8351 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {8351 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 8352 8352 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8353 8353 } IEM_MC_ELSE() { … … 8378 8378 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8379 8379 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8380 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {8380 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 8381 8381 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8382 8382 } IEM_MC_ELSE() { … … 8393 8393 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8394 8394 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8395 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {8395 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 8396 8396 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8397 8397 } IEM_MC_ELSE() { … … 8422 8422 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8423 8423 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8424 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {8424 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 8425 8425 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8426 8426 } IEM_MC_ELSE() { … … 8437 8437 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8438 8438 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8439 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {8439 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 8440 8440 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8441 8441 } IEM_MC_ELSE() { … … 8466 8466 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8467 8467 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8468 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {8468 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 8469 8469 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8470 8470 } IEM_MC_ELSE() { … … 8481 8481 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8482 8482 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8483 IEM_MC_IF_ EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {8483 IEM_MC_IF_FLAGS_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 8484 8484 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8485 8485 } IEM_MC_ELSE() { … … 8510 8510 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8511 8511 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8512 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF) {8512 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF) { 8513 8513 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8514 8514 } IEM_MC_ELSE() { … … 8525 8525 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8526 8526 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8527 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF) {8527 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF) { 8528 8528 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8529 8529 } IEM_MC_ELSE() { … … 8554 8554 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8555 8555 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8556 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF) {8556 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF) { 8557 8557 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8558 8558 } IEM_MC_ELSE() { … … 8569 8569 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8570 8570 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8571 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_SF) {8571 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_SF) { 8572 8572 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8573 8573 } IEM_MC_ELSE() { … … 8598 8598 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8599 8599 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8600 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {8600 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 8601 8601 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8602 8602 } IEM_MC_ELSE() { … … 8613 8613 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8614 8614 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8615 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {8615 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 8616 8616 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8617 8617 } IEM_MC_ELSE() { … … 8642 8642 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8643 8643 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8644 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {8644 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 8645 8645 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8646 8646 } IEM_MC_ELSE() { … … 8657 8657 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8658 8658 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8659 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_PF) {8659 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_PF) { 8660 8660 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8661 8661 } IEM_MC_ELSE() { … … 8686 8686 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8687 8687 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8688 IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {8688 IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 8689 8689 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8690 8690 } IEM_MC_ELSE() { … … 8701 8701 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8702 8702 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8703 IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {8703 IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 8704 8704 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8705 8705 } IEM_MC_ELSE() { … … 8730 8730 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8731 8731 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8732 IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {8732 IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 8733 8733 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8734 8734 } IEM_MC_ELSE() { … … 8745 8745 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8746 8746 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8747 IEM_MC_IF_ EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {8747 IEM_MC_IF_FLAGS_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 8748 8748 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8749 8749 } IEM_MC_ELSE() { … … 8774 8774 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8775 8775 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8776 IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {8776 IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 8777 8777 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8778 8778 } IEM_MC_ELSE() { … … 8789 8789 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8790 8790 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8791 IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {8791 IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 8792 8792 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8793 8793 } IEM_MC_ELSE() { … … 8818 8818 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); 8819 8819 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8820 IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {8820 IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 8821 8821 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8822 8822 } IEM_MC_ELSE() { … … 8833 8833 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 8834 8834 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8835 IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {8835 IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 8836 8836 IEM_MC_STORE_MEM_SEG_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8837 8837 } IEM_MC_ELSE() { … … 10286 10286 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u32, pu32Dst, pu32Eax, u32Src, pEFlags); 10287 10287 10288 IEM_MC_IF_ EFL_BIT_SET(X86_EFL_ZF) {10288 IEM_MC_IF_FLAGS_BIT_SET(X86_EFL_ZF) { 10289 10289 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); 10290 10290 } IEM_MC_ELSE() { … … 10374 10374 IEM_MC_COMMIT_EFLAGS(EFlags); \ 10375 10375 \ 10376 IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_ZF) { \10376 IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_ZF) { \ 10377 10377 IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u32Eax); \ 10378 10378 } IEM_MC_ENDIF(); \ … … 11186 11186 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU32, fEFlagsIn, pu32Dst, u32Src); \ 11187 11187 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 11188 IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_ZF) { \11188 IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_ZF) { \ 11189 11189 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 11190 11190 } IEM_MC_ENDIF(); \ … … 11251 11251 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 11252 11252 \ 11253 IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_ZF) { \11253 IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_ZF) { \ 11254 11254 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 11255 11255 } IEM_MC_ENDIF(); \ … … 12381 12381 IEM_MC_MEM_COMMIT_AND_UNMAP_##a_Type(bUnmapInfo); \ 12382 12382 IEM_MC_COMMIT_EFLAGS(EFlags); \ 12383 IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_ZF) { \12383 IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_ZF) { \ 12384 12384 IEM_MC_STORE_GREG_PAIR_U32(X86_GREG_xAX, X86_GREG_xDX, u64EaxEdx); \ 12385 12385 } IEM_MC_ENDIF(); \ … … 12439 12439 IEM_MC_MEM_COMMIT_AND_UNMAP_##a_Type(bUnmapInfo); \ 12440 12440 IEM_MC_COMMIT_EFLAGS(EFlags); \ 12441 IEM_MC_IF_ EFL_BIT_NOT_SET(X86_EFL_ZF) { \12441 IEM_MC_IF_FLAGS_BIT_NOT_SET(X86_EFL_ZF) { \ 12442 12442 IEM_MC_STORE_GREG_PAIR_U64(X86_GREG_xAX, X86_GREG_xDX, u128RaxRdx); \ 12443 12443 } IEM_MC_ENDIF(); \ -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veLiveness-x86.h
r108296 r108313 1181 1181 } while (0) 1182 1182 1183 #define IEM_MC_IF_ EFL_BIT_SET(a_fBit)IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit); {1184 #define IEM_MC_IF_ EFL_BIT_NOT_SET(a_fBit)IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit); {1185 #define IEM_MC_IF_ EFL_ANY_BITS_SET(a_fBits) \1183 #define IEM_MC_IF_FLAGS_BIT_SET(a_fBit) IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit); { 1184 #define IEM_MC_IF_FLAGS_BIT_NOT_SET(a_fBit) IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit); { 1185 #define IEM_MC_IF_FLAGS_ANY_BITS_SET(a_fBits) \ 1186 1186 do { if ((a_fBits) == (X86_EFL_CF | X86_EFL_ZF)) \ 1187 1187 { IEM_LIVENESS_ONE_EFLAG_INPUT(fEflCf); IEM_LIVENESS_ONE_EFLAG_INPUT(fEflZf); } \ 1188 1188 else { AssertMsgFailed(("#s (%#x)\n", #a_fBits, (a_fBits))); IEM_LIVENESS_ALL_EFLAGS_INPUT(); } \ 1189 1189 } while (0); { 1190 #define IEM_MC_IF_ EFL_NO_BITS_SET(a_fBits) \1190 #define IEM_MC_IF_FLAGS_NO_BITS_SET(a_fBits) \ 1191 1191 do { if ((a_fBits) == (X86_EFL_CF | X86_EFL_ZF)) \ 1192 1192 { IEM_LIVENESS_ONE_EFLAG_INPUT(fEflCf); IEM_LIVENESS_ONE_EFLAG_INPUT(fEflZf); } \ 1193 1193 else { AssertMsgFailed(("#s (%#x)\n", #a_fBits, (a_fBits))); IEM_LIVENESS_ALL_EFLAGS_INPUT(); } \ 1194 1194 } while (0); { 1195 #define IEM_MC_IF_ EFL_BITS_NE(a_fBit1, a_fBit2) \1195 #define IEM_MC_IF_FLAGS_BITS_NE(a_fBit1, a_fBit2) \ 1196 1196 IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit1); \ 1197 1197 IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit2); { 1198 #define IEM_MC_IF_ EFL_BITS_EQ(a_fBit1, a_fBit2) \1198 #define IEM_MC_IF_FLAGS_BITS_EQ(a_fBit1, a_fBit2) \ 1199 1199 IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit1); \ 1200 1200 IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit2); { 1201 #define IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \1201 #define IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \ 1202 1202 IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit); \ 1203 1203 IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit1); \ 1204 1204 IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit2); { 1205 #define IEM_MC_IF_ EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \1205 #define IEM_MC_IF_FLAGS_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \ 1206 1206 IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit); \ 1207 1207 IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit1); \ -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veRecompFuncs-x86.h
r108296 r108313 3365 3365 3366 3366 3367 #define IEM_MC_IF_ EFL_ANY_BITS_SET(a_fBits) \3367 #define IEM_MC_IF_FLAGS_ANY_BITS_SET(a_fBits) \ 3368 3368 off = iemNativeEmitIfEflagAnysBitsSet(pReNative, off, (a_fBits), iemNativeEflagsToLivenessMask<a_fBits>()); \ 3369 3369 do { 3370 3370 3371 /** Emits code for IEM_MC_IF_ EFL_ANY_BITS_SET. */3371 /** Emits code for IEM_MC_IF_FLAGS_ANY_BITS_SET. */ 3372 3372 DECL_INLINE_THROW(uint32_t) 3373 3373 iemNativeEmitIfEflagAnysBitsSet(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fBitsInEfl, uint64_t fLivenessEflBits) … … 3393 3393 3394 3394 3395 #define IEM_MC_IF_ EFL_NO_BITS_SET(a_fBits) \3395 #define IEM_MC_IF_FLAGS_NO_BITS_SET(a_fBits) \ 3396 3396 off = iemNativeEmitIfEflagNoBitsSet(pReNative, off, (a_fBits), iemNativeEflagsToLivenessMask<a_fBits>()); \ 3397 3397 do { 3398 3398 3399 /** Emits code for IEM_MC_IF_ EFL_NO_BITS_SET. */3399 /** Emits code for IEM_MC_IF_FLAGS_NO_BITS_SET. */ 3400 3400 DECL_INLINE_THROW(uint32_t) 3401 3401 iemNativeEmitIfEflagNoBitsSet(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fBitsInEfl, uint64_t fLivenessEflBits) … … 3421 3421 3422 3422 3423 #define IEM_MC_IF_ EFL_BIT_SET(a_fBit) \3423 #define IEM_MC_IF_FLAGS_BIT_SET(a_fBit) \ 3424 3424 off = iemNativeEmitIfEflagsBitSet(pReNative, off, iemNativeEflagsToSingleBitNo<a_fBit>(), \ 3425 3425 iemNativeEflagsToLivenessMask<a_fBit>()); \ 3426 3426 do { 3427 3427 3428 /** Emits code for IEM_MC_IF_ EFL_BIT_SET. */3428 /** Emits code for IEM_MC_IF_FLAGS_BIT_SET. */ 3429 3429 DECL_INLINE_THROW(uint32_t) 3430 3430 iemNativeEmitIfEflagsBitSet(PIEMRECOMPILERSTATE pReNative, uint32_t off, unsigned iBitNo, uint64_t fLivenessEflBit) … … 3450 3450 3451 3451 3452 #define IEM_MC_IF_ EFL_BIT_NOT_SET(a_fBit) \3452 #define IEM_MC_IF_FLAGS_BIT_NOT_SET(a_fBit) \ 3453 3453 off = iemNativeEmitIfEflagsBitNotSet(pReNative, off, iemNativeEflagsToSingleBitNo<a_fBit>(), \ 3454 3454 iemNativeEflagsToLivenessMask<a_fBit>()); \ 3455 3455 do { 3456 3456 3457 /** Emits code for IEM_MC_IF_ EFL_BIT_NOT_SET. */3457 /** Emits code for IEM_MC_IF_FLAGS_BIT_NOT_SET. */ 3458 3458 DECL_INLINE_THROW(uint32_t) 3459 3459 iemNativeEmitIfEflagsBitNotSet(PIEMRECOMPILERSTATE pReNative, uint32_t off, unsigned iBitNo, uint64_t fLivenessEflBit) … … 3479 3479 3480 3480 3481 #define IEM_MC_IF_ EFL_BITS_EQ(a_fBit1, a_fBit2) \3481 #define IEM_MC_IF_FLAGS_BITS_EQ(a_fBit1, a_fBit2) \ 3482 3482 off = iemNativeEmitIfEflagsTwoBitsEqual(pReNative, off, false /*fInverted*/, \ 3483 3483 iemNativeEflagsToSingleBitNo<a_fBit1>(), \ … … 3486 3486 do { 3487 3487 3488 #define IEM_MC_IF_ EFL_BITS_NE(a_fBit1, a_fBit2) \3488 #define IEM_MC_IF_FLAGS_BITS_NE(a_fBit1, a_fBit2) \ 3489 3489 off = iemNativeEmitIfEflagsTwoBitsEqual(pReNative, off, true /*fInverted*/, \ 3490 3490 iemNativeEflagsToSingleBitNo<a_fBit1>(), \ … … 3493 3493 do { 3494 3494 3495 /** Emits code for IEM_MC_IF_ EFL_BITS_EQ and IEM_MC_IF_EFL_BITS_NE. */3495 /** Emits code for IEM_MC_IF_FLAGS_BITS_EQ and IEM_MC_IF_FLAGS_BITS_NE. */ 3496 3496 DECL_INLINE_THROW(uint32_t) 3497 3497 iemNativeEmitIfEflagsTwoBitsEqual(PIEMRECOMPILERSTATE pReNative, uint32_t off, … … 3552 3552 3553 3553 3554 #define IEM_MC_IF_ EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \3554 #define IEM_MC_IF_FLAGS_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \ 3555 3555 off = iemNativeEmitIfEflagsBitNotSetAndTwoBitsEqual(pReNative, off, false /*fInverted*/, \ 3556 3556 iemNativeEflagsToSingleBitNo<a_fBit>(), \ … … 3560 3560 do { 3561 3561 3562 #define IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \3562 #define IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \ 3563 3563 off = iemNativeEmitIfEflagsBitNotSetAndTwoBitsEqual(pReNative, off, true /*fInverted*/, \ 3564 3564 iemNativeEflagsToSingleBitNo<a_fBit>(), \ … … 3568 3568 do { 3569 3569 3570 /** Emits code for IEM_MC_IF_ EFL_BIT_NOT_SET_AND_BITS_EQ and3571 * IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE. */3570 /** Emits code for IEM_MC_IF_FLAGS_BIT_NOT_SET_AND_BITS_EQ and 3571 * IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE. */ 3572 3572 DECL_INLINE_THROW(uint32_t) 3573 3573 iemNativeEmitIfEflagsBitNotSetAndTwoBitsEqual(PIEMRECOMPILERSTATE pReNative, uint32_t off, bool fInverted, -
trunk/src/VBox/VMM/include/IEMMc.h
r108312 r108313 1441 1441 * arm: EFL == NZCV. 1442 1442 */ 1443 /** @todo s/IEM_MC_IF_EFL_/IEM_MC_IF_FLAGS_/ */1444 1443 1445 1444 /** @note x86: Not for IOPL or IF testing. */ 1446 #define IEM_MC_IF_ EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {1445 #define IEM_MC_IF_FLAGS_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) { 1447 1446 /** @note x86: Not for IOPL or IF testing. */ 1448 #define IEM_MC_IF_ EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {1447 #define IEM_MC_IF_FLAGS_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) { 1449 1448 /** @note x86: Not for IOPL or IF testing. */ 1450 #define IEM_MC_IF_ EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {1449 #define IEM_MC_IF_FLAGS_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) { 1451 1450 /** @note x86: Not for IOPL or IF testing. */ 1452 #define IEM_MC_IF_ EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {1451 #define IEM_MC_IF_FLAGS_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) { 1453 1452 /** @note x86: Not for IOPL or IF testing. */ 1454 #define IEM_MC_IF_ EFL_BITS_NE(a_fBit1, a_fBit2) \1453 #define IEM_MC_IF_FLAGS_BITS_NE(a_fBit1, a_fBit2) \ 1455 1454 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \ 1456 1455 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) { 1457 1456 /** @note x86: Not for IOPL or IF testing. */ 1458 #define IEM_MC_IF_ EFL_BITS_EQ(a_fBit1, a_fBit2) \1457 #define IEM_MC_IF_FLAGS_BITS_EQ(a_fBit1, a_fBit2) \ 1459 1458 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \ 1460 1459 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) { 1461 1460 /** @note x86: Not for IOPL or IF testing. */ 1462 #define IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \1461 #define IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \ 1463 1462 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \ 1464 1463 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \ 1465 1464 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) { 1466 1465 /** @note x86: Not for IOPL or IF testing. */ 1467 #define IEM_MC_IF_ EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \1466 #define IEM_MC_IF_FLAGS_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \ 1468 1467 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \ 1469 1468 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \ -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r108296 r108313 1113 1113 do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0) 1114 1114 1115 #define IEM_MC_IF_ EFL_BIT_SET(a_fBit)(void)fMcBegin; if (g_fRandom) {1116 #define IEM_MC_IF_ EFL_BIT_NOT_SET(a_fBit)(void)fMcBegin; if (g_fRandom) {1117 #define IEM_MC_IF_ EFL_ANY_BITS_SET(a_fBits)(void)fMcBegin; if (g_fRandom) {1118 #define IEM_MC_IF_ EFL_NO_BITS_SET(a_fBits)(void)fMcBegin; if (g_fRandom) {1119 #define IEM_MC_IF_ EFL_BITS_NE(a_fBit1, a_fBit2)(void)fMcBegin; if (g_fRandom) {1120 #define IEM_MC_IF_ EFL_BITS_EQ(a_fBit1, a_fBit2)(void)fMcBegin; if (g_fRandom) {1121 #define IEM_MC_IF_ EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2)(void)fMcBegin; if (g_fRandom) {1122 #define IEM_MC_IF_ EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) {1115 #define IEM_MC_IF_FLAGS_BIT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) { 1116 #define IEM_MC_IF_FLAGS_BIT_NOT_SET(a_fBit) (void)fMcBegin; if (g_fRandom) { 1117 #define IEM_MC_IF_FLAGS_ANY_BITS_SET(a_fBits) (void)fMcBegin; if (g_fRandom) { 1118 #define IEM_MC_IF_FLAGS_NO_BITS_SET(a_fBits) (void)fMcBegin; if (g_fRandom) { 1119 #define IEM_MC_IF_FLAGS_BITS_NE(a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) { 1120 #define IEM_MC_IF_FLAGS_BITS_EQ(a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) { 1121 #define IEM_MC_IF_FLAGS_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) { 1122 #define IEM_MC_IF_FLAGS_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) (void)fMcBegin; if (g_fRandom) { 1123 1123 #define IEM_MC_IF_CX_IS_NZ() (void)fMcBegin; if (g_fRandom) { 1124 1124 #define IEM_MC_IF_ECX_IS_NZ() (void)fMcBegin; if (g_fRandom) {
Note:
See TracChangeset
for help on using the changeset viewer.
