Changeset 108443 in vbox for trunk/src/VBox/VMM/include

Timestamp:

Mar 4, 2025 8:15:22 PM (2 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

167817

Message:

VMM/GIC: bugref:10404 Fixes to the interrupt priority logic which fixes hang during arm64 Windows 11 guest boot.
Other minor cleanups.

File:

• trunk/src/VBox/VMM/include/GICInternal.h (modified) (6 diffs)

trunk/src/VBox/VMM/include/GICInternal.h

@@ -68 +68 @@
 #endif
 
+#if 0
 /** Maximum number of SPI interrupts. */
 #define GIC_SPI_MAX                         32
-
+#endif
+
+#if 0
 /** @def GIC_CACHE_LINE_SIZE
  * Padding (in bytes) for aligning data in different cache lines. The ARMv8 cache
@@ -79 +82 @@
 #define GIC_CACHE_LINE_SIZE                64
 
-#if 1
 /**
  * GIC Interrupt-Delivery Bitmap (IDB).
@@ -107 +109 @@
     IOMMMIOHANDLE               hMmioReDist;
 
-    /** @name Distributor register state for SPIs and extended SPIs.
+    /** @name Distributor register state.
      * @{
      */
@@ -129 +131 @@
 
     /** Flag whether group 0 interrupts are enabled. */
-    bool                        fIrqGrp0Enabled;
+    bool                        fIntrGroup0Enabled;
     /** Flag whether group 1 interrupts are enabled. */
-    bool                        fIrqGrp1Enabled;
+    bool                        fIntrGroup1Enabled;
     /** Flag whether affinity routing is enabled. */
     bool                        fAffRoutingEnabled;
-    /** Padding. */
-    bool                        afPadding;
+    /** Alignment. */
+    bool                        fAlignment0;
     /** @} */
 #else
@@ -180 +182 @@
     /** Whether range-selector is supported (GICD_TYPER.RSS and ICC_CTLR_EL1.RSS). */
     bool                        fRangeSelSupport;
+    /** Alignment. */
+    bool                        afAlignment0[3];
     /** @} */
 } GICDEV;
@@ -258 +262 @@
     /** The current interrupt priority, only interrupts with a higher priority get signalled. */
     uint8_t                     bInterruptPriority;
-    /** The interrupt controller Binary Point Register for Group 0 interrupts. */
+    /** The binary point register for group 0 interrupts. */
     uint8_t                     bBinaryPointGrp0;
-    /** The interrupt controller Binary Point Register for Group 1 interrupts. */
+    /** The binary point register for group 1 interrupts. */
     uint8_t                     bBinaryPointGrp1;
-    /** Flag whether group 0 interrupts are currently enabled. */
-    bool                        fIrqGrp0Enabled;
-    /** Flag whether group 1 interrupts are currently enabled. */
-    bool                        fIrqGrp1Enabled;
+    /** Flag whether group 0 interrupts are enabled. */
+    bool                        fIntrGroup0Enabled;
+    /** Flag whether group 1 interrupts are enabled. */
+    bool                        fIntrGroup1Enabled;
+    /** Alignment. */
+    bool                        afAlignment0[2];
     /** @} */