Changeset 108444 in vbox for trunk/include
- Timestamp:
- Mar 4, 2025 9:27:37 PM (7 weeks ago)
- svn:sync-xref-src-repo-rev:
- 167818
- File:
-
- 1 edited
-
trunk/include/VBox/vmm/pgm.h (modified) (8 diffs)
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trunk/include/VBox/vmm/pgm.h
r108132 r108444 378 378 379 379 380 /** @name PGM_PTATTRS_XXX - PGM page-table attributes. 381 * 382 * This is VirtualBox's combined page table attributes. It combines regular page 383 * table and Intel EPT attributes. It's 64-bit in size so there's ample room for 384 * bits added in the future to EPT or regular page tables (for e.g. Protection Key). 380 /** PGM page-table attributes. 381 * 382 * This is VirtualBox's combined page table attributes. This combines 383 * attributes from the regular page/translation tables and the nested page 384 * tables / stage 2 translation tables. */ 385 typedef uint64_t PGMPTATTRS; 386 /** Pointer to a PGMPTATTRS type. */ 387 typedef PGMPTATTRS *PPGMPTATTRS; 388 389 #if defined(VBOX_VMM_TARGET_X86) || defined(DOXYGEN_RUNNING) 390 /** @name PGM_PTATTRS_XXX - PGM page-table attributes, x86 edition. 385 391 * 386 392 * The following bits map 1:1 (shifted by PGM_PTATTRS_EPT_SHIFT) to the Intel EPT … … 410 416 * 411 417 * @{ */ 412 typedef uint64_t PGMPTATTRS;413 /** Pointer to a PGMPTATTRS type. */414 typedef PGMPTATTRS *PPGMPTATTRS;415 416 418 /** Read bit (always 1 for regular PT, copy of EPT_R for EPT). */ 417 419 #define PGM_PTATTRS_R_SHIFT 0 … … 569 571 AssertCompile(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_IGNORE_PAT); 570 572 AssertCompile(PGM_PTATTRS_EPT_X_USER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_USER_EXECUTE); 573 /** @} */ 574 #endif /* VBOX_VMM_TARGET_X86 || DOXYGEN_RUNNING */ 575 576 #if defined(VBOX_VMM_TARGET_ARMV8) || defined(DOXYGEN_RUNNING) 577 /** @name PGM_PTATTRS_XXX - PGM page-table attributes, ARMv8 edition. 578 * 579 * The translation tables on ARMv8 are complicated by compressed and index 580 * attributes as well as a myriade of feature dependent field interpretations. 581 * 582 * The stage 1 effective access attributes are placed in bits 47:32, with some 583 * room reserved for new stuff. A set of leaf bits are copied raw, but NSE had 584 * to be shifted down due to nG confusion. 585 * 586 * The stage 2 effective access attributes are placed in bit 31:24. Bits taken 587 * directly from the leaf translation table entry are shifted down 7 bits to 588 * avoid collision with similar bits from the stage 1 leaf. 589 * 590 * @{ */ 591 592 /** Stage 2, page/block: D - dirty flag. (shifted down 7) */ 593 #define PGM_PTATTRS_S2_D_SHIFT 0 594 #define PGM_PTATTRS_S2_D_MASK RT_BIT_64(PGM_PTATTRS_S2_D_SHIFT) 595 /** Stage 2, page/block: AF - access flag. (shifted down 7) */ 596 #define PGM_PTATTRS_S2_AF_SHIFT 3 597 #define PGM_PTATTRS_S2_AF_MASK RT_BIT_64(PGM_PTATTRS_S2_AF_SHIFT) 598 /** Page/block level: NS - Non-secure. */ 599 #define PGM_PTATTRS_NS_SHIFT 5 600 #define PGM_PTATTRS_NS_MASK RT_BIT_64(PGM_PTATTRS_NS_SHIFT) 601 /** Page/block level: NSE - Non-secure extension (?) - FEAT_RME, FEAT_SEL2. 602 * @note Overlaps with nG, shifted down. */ 603 #define PGM_PTATTRS_NSE_SHIFT 6 604 #define PGM_PTATTRS_NSE_MASK RT_BIT_64(PGM_PTATTRS_NSE_SHIFT) 605 /** Page/block level: nD - Not dirty. */ 606 #define PGM_PTATTRS_ND_SHIFT 7 607 #define PGM_PTATTRS_ND_MASK RT_BIT_64(PGM_PTATTRS_AF_SHIFT) 608 /** Stage 2, page/block: nT, FEAT_BBM. Only supported with 64KB page size. */ 609 #define PGM_PTATTRS_S2_NT_SHIFT 9 610 #define PGM_PTATTRS_S2_NT_MASK RT_BIT_64(PGM_PTATTRS_NT_SHIFT) 611 /** Combined: AF - Access flag. 612 * @note The table and page/block AF attributes ANDed together. */ 613 #define PGM_PTATTRS_AF_SHIFT 10 614 #define PGM_PTATTRS_AF_MASK RT_BIT_64(PGM_PTATTRS_AF_SHIFT) 615 /** Page/block level: nG - Not global nG bit. */ 616 #define PGM_PTATTRS_NG_SHIFT 11 617 #define PGM_PTATTRS_NG_MASK RT_BIT_64(PGM_PTATTRS_NG_SHIFT) 618 /** Page/block level: nT, FEAT_BBM. Only supported with 64KB page size. */ 619 #define PGM_PTATTRS_NT_SHIFT 16 620 #define PGM_PTATTRS_NT_MASK RT_BIT_64(PGM_PTATTRS_NT_SHIFT) 621 622 /** Stage 2: Read access. */ 623 #define PGM_PTATTRS_S2_R_SHIFT 24 624 #define PGM_PTATTRS_S2_R_MASK RT_BIT_64(PGM_PTATTRS_S2_UX_SHIFT) 625 /** Stage 2: Full write access. */ 626 #define PGM_PTATTRS_S2_W_SHIFT 25 627 #define PGM_PTATTRS_S2_W_MASK RT_BIT_64(PGM_PTATTRS_S2_UX_SHIFT) 628 /** Stage 2: Privileged execution access. */ 629 #define PGM_PTATTRS_S2_PX_SHIFT 26 630 #define PGM_PTATTRS_S2_PX_MASK RT_BIT_64(PGM_PTATTRS_S2_UX_SHIFT) 631 /** Stage 2: Unprivileged execution access. */ 632 #define PGM_PTATTRS_S2_UX_SHIFT 27 633 #define PGM_PTATTRS_S2_UX_MASK RT_BIT_64(PGM_PTATTRS_S2_UX_SHIFT) 634 /** Stage 2: Limited write access - only MMU and RCW. */ 635 #define PGM_PTATTRS_S2_W_LIM_SHIFT 28 636 #define PGM_PTATTRS_S2_W_LIM_MASK RT_BIT_64(PGM_PTATTRS_S2_UX_SHIFT) 637 /** Stage 2: TopLevel0 - only used with PGM_PTATTRS_S2_W_LIM_MASK. */ 638 #define PGM_PTATTRS_S2_TL0_SHIFT 29 639 #define PGM_PTATTRS_S2_TL0_MASK RT_BIT_64(PGM_PTATTRS_S2_TL0_SHIFT) 640 /** Stage 2: TopLevel1 - only used with PGM_PTATTRS_S2_W_LIM_MASK. */ 641 #define PGM_PTATTRS_S2_TL1_SHIFT 30 642 #define PGM_PTATTRS_S2_TL1_MASK RT_BIT_64(PGM_PTATTRS_S2_TL1_SHIFT) 643 644 /** Stage 1: Privileged read access. */ 645 #define PGM_PTATTRS_PR_SHIFT 32 646 #define PGM_PTATTRS_PR_MASK RT_BIT_64(PGM_PTATTRS_PR_SHIFT) 647 /** Stage 1: Privileged write access. */ 648 #define PGM_PTATTRS_PW_SHIFT 33 649 #define PGM_PTATTRS_PW_MASK RT_BIT_64(PGM_PTATTRS_PW_SHIFT) 650 /** Stage 1: Privileged execute access. */ 651 #define PGM_PTATTRS_PX_SHIFT 34 652 #define PGM_PTATTRS_PX_MASK RT_BIT_64(PGM_PTATTRS_PX_SHIFT) 653 /** Stage 1: Privileged guarded control stack (GCS) access. */ 654 #define PGM_PTATTRS_PGCS_SHIFT 35 655 #define PGM_PTATTRS_PGCS_MASK RT_BIT_64(PGM_PTATTRS_PGCS_SHIFT) 656 /** Stage 1: Privileged write-implies-no-execute access. 657 * @todo not sure if we need expose this bit. */ 658 #define PGM_PTATTRS_PWXN_SHIFT 36 659 #define PGM_PTATTRS_PWXN_MASK RT_BIT_64(PGM_PTATTRS_PWXN_SHIFT) 660 661 /** Stage 1: Unprivileged read access. */ 662 #define PGM_PTATTRS_UR_SHIFT 40 663 #define PGM_PTATTRS_UR_MASK RT_BIT_64(PGM_PTATTRS_UR_SHIFT) 664 /** Stage 1: Unprivileged write access. */ 665 #define PGM_PTATTRS_UW_SHIFT 41 666 #define PGM_PTATTRS_UW_MASK RT_BIT_64(PGM_PTATTRS_UW_SHIFT) 667 /** Stage 1: Unprivileged execute access. */ 668 #define PGM_PTATTRS_UX_SHIFT 42 669 #define PGM_PTATTRS_UX_MASK RT_BIT_64(PGM_PTATTRS_UX_SHIFT) 670 /** Stage 1: Unprivileged guarded control stack (GCS) access. */ 671 #define PGM_PTATTRS_UGCS_SHIFT 43 672 #define PGM_PTATTRS_UGCS_MASK RT_BIT_64(PGM_PTATTRS_UGCS_SHIFT) 673 /** Stage 1: Unprivileged write-implies-no-execute access. 674 * @todo not sure if we need expose this bit. */ 675 #define PGM_PTATTRS_UWXN_SHIFT 44 676 #define PGM_PTATTRS_UWXN_MASK RT_BIT_64(PGM_PTATTRS_UWXN_SHIFT) 677 678 /** Page/block level: Guarded page */ 679 #define PGM_PTATTRS_GP_SHIFT 50 680 #define PGM_PTATTRS_GP_MASK RT_BIT_64(PGM_PTATTRS_GP_SHIFT) 681 /** Stage 2, page/block: AssuredOnly. (shifted down 7 bits) */ 682 #define PGM_PTATTRS_S2_AO_SHIFT 51 683 #define PGM_PTATTRS_S2_AO_MASK RT_BIT_64(PGM_PTATTRS_S2_TL1_SHIFT) 684 /** Stage 2, page/block: Alternate MECID (encryption related). (shifted down 685 * 7 bits) */ 686 #define PGM_PTATTRS_S2_AMEC_SHIFT 56 687 #define PGM_PTATTRS_S2_AMEC_MASK RT_BIT_64(PGM_PTATTRS_S2_AMEC_SHIFT) 688 /** Page/block level: Alternate MECID (encryption related). */ 689 #define PGM_PTATTRS_AMEC_SHIFT 63 690 #define PGM_PTATTRS_AMEC_MASK RT_BIT_64(PGM_PTATTRS_AMEC_SHIFT) 691 692 /** Stage 1 page/block level bits that are copied raw. */ 693 #define PGM_PTATTRS_S1_LEAF_MASK ( PGM_PTATTRS_NS_MASK \ 694 /*| PGM_PTATTRS_NSE_MASK shifted */ \ 695 | PGM_PTATTRS_AF_MASK \ 696 | PGM_PTATTRS_NG_MASK \ 697 | PGM_PTATTRS_NT_MASK \ 698 | PGM_PTATTRS_GP_MASK \ 699 | PGM_PTATTRS_AMEC_MASK ) 700 701 /** Stage 2 page/block level entry shift down count. */ 702 #define PGM_PTATTRS_S2_LEAF_SHIFT 7 703 /** Stage 2 page/block level entry mask of shifted down bits copied. */ 704 #define PGM_PTATTRS_S2_LEAF_MASK ( PGM_PTATTRS_S2_D_MASK \ 705 | PGM_PTATTRS_S2_AF_MASK \ 706 | PGM_PTATTRS_S2_NT_MASK \ 707 | PGM_PTATTRS_S2_AO_MASK \ 708 | PGM_PTATTRS_S2_AMEC_MASK ) 709 571 710 /** @} */ 711 #endif /* VBOX_VMM_TARGET_ARMV8 || DOXYGEN_RUNNING */ 712 572 713 573 714 … … 583 724 RTGCPTR GCPtr; 584 725 585 /** The second-level physical address (input/output).726 /** The second-level (/ stage 2) physical address (input/output). 586 727 * @remarks only valid if fIsSlat is set. */ 587 728 RTGCPHYS GCPhysNested; … … 592 733 /** Set if the walk succeeded. */ 593 734 bool fSucceeded; 594 /** Whether this is a second-level address translation. */735 /** Whether this is a second-level (/ stage 2) address translation. */ 595 736 bool fIsSlat; 596 737 /** Whether the linear address (GCPtr) caused the second-level … … 598 739 bool fIsLinearAddrValid; 599 740 /** The level problem arrised at. 600 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is 601 * level 8. This is 0 on success. */ 741 * @x86 PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, 742 * CR3 is level 8. This is 0 on success. 743 * @arm64 TBD. 744 * @todo Check if anyone is using this and unify it between the platforms. */ 602 745 uint8_t uLevel; 603 746 /** Set if the page isn't present. */ … … 609 752 /** Set if it involves a big page (2/4 MB). */ 610 753 bool fBigPage; 611 /** Set if it involves a gigantic page ( 1 GB). */754 /** Set if it involves a gigantic page (X86: 1 GB; ARM: ). */ 612 755 bool fGigantPage; 613 756 bool afPadding[3]; … … 628 771 /** Set if the walk succeeded. */ 629 772 #define PGM_WALKINFO_SUCCEEDED RT_BIT_32(0) 630 /** Whether this is a second-level address translation. */773 /** Whether this is a second-level (/ stage 2) address translation. */ 631 774 #define PGM_WALKINFO_IS_SLAT RT_BIT_32(1) 632 775 633 /** Set if it involves a big page (2/4 MB). */ 776 /** Set if it involves a big page. 777 * @x86 2MB (PAE+LM), 4MB (legacy). 778 * @arm64 Level 2 block - 2MB (gr=4KB v8), 32MB (gr=16KB v8), 512MB (gr=64KB 779 * v8), 1MB (gr=4K v9), 16MB (gr=16KB v9), 256MB (gr=64KB v9). */ 634 780 #define PGM_WALKINFO_BIG_PAGE RT_BIT_32(7) 635 /** Set if it involves a gigantic page (1 GB). */ 781 /** Set if it involves a gigantic page. 782 * @x86 1 GB. 783 * @arm64 Level 1 block - 1GB (gr=4KB v8), 256MB (gr=4KB v9), 16GB (gr=16KB 784 * v9), 1TB (gr=64KB v9). */ 636 785 #define PGM_WALKINFO_GIGANTIC_PAGE RT_BIT_32(8) 786 787 /** @todo Add a level 0 block flag for ARM/VMSAv9. */ 637 788 638 789 /** Whether the linear address (GCPtr) caused the second-level
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