Index: trunk/src/VBox/VMM/VMMAll/target-armv8/IEMAll-armv8.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/target-x86/IEMAll-x86.cpp	(revision 108260)
+++ trunk/src/VBox/VMM/VMMAll/target-armv8/IEMAll-armv8.cpp	(revision 108710)
@@ -1,5 +1,5 @@
 /* $Id$ */
 /** @file
- * IEM - Interpreted Execution Manager - x86 target, miscellaneous.
+ * IEM - Interpreted Execution Manager - ARMv8 target, miscellaneous.
  */
 
@@ -32,7 +32,4 @@
 #define LOG_GROUP   LOG_GROUP_IEM
 #define VMCPU_INCL_CPUM_GST_CTX
-#ifdef IN_RING0
-# define VBOX_VMM_TARGET_X86
-#endif
 #include <VBox/vmm/iem.h>
 #include <VBox/vmm/cpum.h>
@@ -41,25 +38,11 @@
 #include <VBox/vmm/vmcc.h>
 #include <VBox/log.h>
-#include <VBox/param.h>
 #include <iprt/assert.h>
-#include <iprt/errcore.h>
-#include <iprt/string.h>
-#include <iprt/x86.h>
+#include <iprt/armv8.h>
 
-#include "IEMInline-x86.h" /* iemRegFinishClearingRF */
 
 
 /**
- * Calculates IEM_F_BRK_PENDING_XXX (IEM_F_PENDING_BRK_MASK) flags, slow code
- * path.
- *
- * This will also invalidate TLB entries for any pages with active data
- * breakpoints on them.
- *
- * @returns IEM_F_BRK_PENDING_XXX or zero.
- * @param   pVCpu               The cross context virtual CPU structure of the
- *                              calling thread.
- *
- * @note    Don't call directly, use iemCalcExecDbgFlags instead.
+ * Slow iemCalcExecDbgFlags() code path.
  */
 uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu)
@@ -67,4 +50,5 @@
     uint32_t fExec = 0;
 
+#if 0 /** @todo ARM hardware breakpoints/watchpoints. */
     /*
      * Helper for invalidate the data TLB for breakpoint addresses.
@@ -137,161 +121,9 @@
         PROCESS_ONE_BP(fHyperDr7, 3, DBGFBpGetDR3(pVM));
     }
+#else
+    RT_NOREF(pVCpu);
+#endif
 
     return fExec;
 }
 
-
-/** @name   Register Access.
- * @{
- */
-
-/**
- * Adds a 8-bit signed jump offset to RIP/EIP/IP.
- *
- * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
- * segment limit.
- *
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   cbInstr             Instruction size.
- * @param   offNextInstr        The offset of the next instruction.
- * @param   enmEffOpSize        Effective operand size.
- */
-VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
-                                                        IEMMODE enmEffOpSize) RT_NOEXCEPT
-{
-    switch (enmEffOpSize)
-    {
-        case IEMMODE_16BIT:
-        {
-            uint16_t const uNewIp = pVCpu->cpum.GstCtx.ip + cbInstr + (int16_t)offNextInstr;
-            if (RT_LIKELY(   uNewIp <= pVCpu->cpum.GstCtx.cs.u32Limit
-                          || IEM_IS_64BIT_CODE(pVCpu) /* no CS limit checks in 64-bit mode */))
-                pVCpu->cpum.GstCtx.rip = uNewIp;
-            else
-                return iemRaiseGeneralProtectionFault0(pVCpu);
-            break;
-        }
-
-        case IEMMODE_32BIT:
-        {
-            Assert(!IEM_IS_64BIT_CODE(pVCpu));
-            Assert(pVCpu->cpum.GstCtx.rip <= UINT32_MAX);
-
-            uint32_t const uNewEip = pVCpu->cpum.GstCtx.eip + cbInstr + (int32_t)offNextInstr;
-            if (RT_LIKELY(uNewEip <= pVCpu->cpum.GstCtx.cs.u32Limit))
-                pVCpu->cpum.GstCtx.rip = uNewEip;
-            else
-                return iemRaiseGeneralProtectionFault0(pVCpu);
-            break;
-        }
-
-        case IEMMODE_64BIT:
-        {
-            Assert(IEM_IS_64BIT_CODE(pVCpu));
-
-            uint64_t const uNewRip = pVCpu->cpum.GstCtx.rip + cbInstr + (int64_t)offNextInstr;
-            if (RT_LIKELY(IEM_IS_CANONICAL(uNewRip)))
-                pVCpu->cpum.GstCtx.rip = uNewRip;
-            else
-                return iemRaiseGeneralProtectionFault0(pVCpu);
-            break;
-        }
-
-        IEM_NOT_REACHED_DEFAULT_CASE_RET();
-    }
-
-#ifndef IEM_WITH_CODE_TLB
-    /* Flush the prefetch buffer. */
-    pVCpu->iem.s.cbOpcode = cbInstr;
-#endif
-
-    /*
-     * Clear RF and finish the instruction (maybe raise #DB).
-     */
-    return iemRegFinishClearingRF(pVCpu, VINF_SUCCESS);
-}
-
-
-/**
- * Adds a 16-bit signed jump offset to RIP/EIP/IP.
- *
- * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
- * segment limit.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   cbInstr             Instruction size.
- * @param   offNextInstr        The offset of the next instruction.
- */
-VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT
-{
-    Assert(pVCpu->iem.s.enmEffOpSize == IEMMODE_16BIT);
-
-    uint16_t const uNewIp = pVCpu->cpum.GstCtx.ip + cbInstr + offNextInstr;
-    if (RT_LIKELY(   uNewIp <= pVCpu->cpum.GstCtx.cs.u32Limit
-                  || IEM_IS_64BIT_CODE(pVCpu) /* no limit checking in 64-bit mode */))
-        pVCpu->cpum.GstCtx.rip = uNewIp;
-    else
-        return iemRaiseGeneralProtectionFault0(pVCpu);
-
-#ifndef IEM_WITH_CODE_TLB
-    /* Flush the prefetch buffer. */
-    pVCpu->iem.s.cbOpcode = IEM_GET_INSTR_LEN(pVCpu);
-#endif
-
-    /*
-     * Clear RF and finish the instruction (maybe raise #DB).
-     */
-    return iemRegFinishClearingRF(pVCpu, VINF_SUCCESS);
-}
-
-
-/**
- * Adds a 32-bit signed jump offset to RIP/EIP/IP.
- *
- * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
- * segment limit.
- *
- * @returns Strict VBox status code.
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   cbInstr             Instruction size.
- * @param   offNextInstr        The offset of the next instruction.
- * @param   enmEffOpSize        Effective operand size.
- */
-VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
-                                                         IEMMODE enmEffOpSize) RT_NOEXCEPT
-{
-    if (enmEffOpSize == IEMMODE_32BIT)
-    {
-        Assert(pVCpu->cpum.GstCtx.rip <= UINT32_MAX); Assert(!IEM_IS_64BIT_CODE(pVCpu));
-
-        uint32_t const uNewEip = pVCpu->cpum.GstCtx.eip + cbInstr + offNextInstr;
-        if (RT_LIKELY(uNewEip <= pVCpu->cpum.GstCtx.cs.u32Limit))
-            pVCpu->cpum.GstCtx.rip = uNewEip;
-        else
-            return iemRaiseGeneralProtectionFault0(pVCpu);
-    }
-    else
-    {
-        Assert(enmEffOpSize == IEMMODE_64BIT);
-
-        uint64_t const uNewRip = pVCpu->cpum.GstCtx.rip + cbInstr + (int64_t)offNextInstr;
-        if (RT_LIKELY(IEM_IS_CANONICAL(uNewRip)))
-            pVCpu->cpum.GstCtx.rip = uNewRip;
-        else
-            return iemRaiseGeneralProtectionFault0(pVCpu);
-    }
-
-#ifndef IEM_WITH_CODE_TLB
-    /* Flush the prefetch buffer. */
-    pVCpu->iem.s.cbOpcode = IEM_GET_INSTR_LEN(pVCpu);
-#endif
-
-    /*
-     * Clear RF and finish the instruction (maybe raise #DB).
-     */
-    return iemRegFinishClearingRF(pVCpu, VINF_SUCCESS);
-}
-
-/** @}  */
-
