Changeset 108745 in vbox

Timestamp:

Mar 26, 2025 7:34:58 AM (3 weeks ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

168170

Message:

VMM/GIC: bugref:10877 Assert adjustments on unexpected/unknown register accesses.

File:

• trunk/src/VBox/VMM/VMMAll/GICAll.cpp (modified) (6 diffs)

trunk/src/VBox/VMM/VMMAll/GICAll.cpp

@@ -2032 +2032 @@
             break;
         }
-        case GIC_DIST_REG_STATUSR_OFF:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_ITARGETSRn_OFF_START:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_IGRPMODRn_OFF_START:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_NSACRn_OFF_START:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_SGIR_OFF:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_CPENDSGIRn_OFF_START:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_SPENDSGIRn_OFF_START:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_INMIn_OFF_START:
-            AssertReleaseFailed();
-            break;
         case GIC_DIST_REG_PIDR2_OFF:
             Assert(pGicDev->uArchRev <= GIC_DIST_REG_PIDR2_ARCH_REV_GICV4);
@@ -2254 +2230 @@
             pGicDev->fIntrGroup1Enabled = RT_BOOL(uValue & GIC_DIST_REG_CTRL_ENABLE_GRP1_NS);
             rcStrict = gicDistUpdateIrqState(pVM, pGicDev);
-            break;
-        case GIC_DIST_REG_STATUSR_OFF:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_SETSPI_NSR_OFF:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_CLRSPI_NSR_OFF:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_SETSPI_SR_OFF:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_CLRSPI_SR_OFF:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_ITARGETSRn_OFF_START:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_IGRPMODRn_OFF_START:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_NSACRn_OFF_START:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_SGIR_OFF:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_CPENDSGIRn_OFF_START:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_SPENDSGIRn_OFF_START:
-            AssertReleaseFailed();
-            break;
-        case GIC_DIST_REG_INMIn_OFF_START:
-            AssertReleaseFailed();
             break;
         default:
@@ -2333 +2273 @@
             break;
         }
+        case GIC_REDIST_REG_WAKER_OFF:
+            *puValue = 0;
+            break;
         case GIC_REDIST_REG_IIDR_OFF:
             *puValue = 0x43b;    /* JEP106 code 0x43b is an ARM implementation. */
@@ -2347 +2290 @@
             break;
         default:
+            AssertReleaseMsgFailed(("offReg=%#x\n",  offReg));
             *puValue = 0;
             break;
@@ -2444 +2388 @@
     }
 
-    AssertReleaseFailed();
+    AssertReleaseMsgFailed(("offReg=%#x\n",  offReg));
     *puValue = 0;
     return VINF_SUCCESS;
@@ -2471 +2415 @@
             break;
         default:
-            AssertReleaseFailed();
+            AssertReleaseMsgFailed(("offReg=%#x uValue=%#RX32\n", offReg, uValue));
             break;
     }