Changeset 108751 in vbox for trunk/include
- Timestamp:
- Mar 26, 2025 10:33:33 AM (4 weeks ago)
- svn:sync-xref-src-repo-rev:
- 168176
- Location:
- trunk/include/VBox
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/gic-its.h
r108694 r108751 204 204 #define GITS_CTRL_REG_BASER_RANGE_SIZE (GITS_CTRL_REG_BASER_OFF_LAST + sizeof(uint64_t) - GITS_CTRL_REG_BASER_OFF_FIRST) 205 205 206 /** GITS_PIDR2: ITS Peripheral ID2 register - RO. */ 207 #define GITS_CTRL_REG_PIDR2_OFF 0xffe8 208 /** GITS_PIDR2: JEDEC - JEP code. */ 209 #define GITS_BF_CTRL_REG_PIDR2_JEDEC_SHIFT 0 210 #define GITS_BF_CTRL_REG_PIDR2_JEDEC_MASK UINT32_C(0x00000007) 211 /** GITS_PIDR2: DES_1 - JEP106 identification code (bits 6:4). */ 212 #define GITS_BF_CTRL_REG_PIDR2_DES_1_SHIFT 3 213 #define GITS_BF_CTRL_REG_PIDR2_DES_1_MASK UINT32_C(0x00000008) 214 /** GITS_PIDR2: Architecture revision . */ 215 #define GITS_BF_CTRL_REG_PIDR2_ARCHREV_SHIFT 4 216 #define GITS_BF_CTRL_REG_PIDR2_ARCHREV_MASK UINT32_C(0x000000f0) 217 /** GITS_PIDR2: Reserved (bits 31:8). */ 218 #define GITS_BF_CTRL_REG_PIDR2_RSVD_31_8_SHIFT 8 219 #define GITS_BF_CTRL_REG_PIDR2_RSVD_31_8_MASK UINT32_C(0xffffff00) 220 RT_BF_ASSERT_COMPILE_CHECKS(GITS_BF_CTRL_REG_PIDR2_, UINT32_C(0), UINT32_MAX, 221 (JEDEC, DES_1, ARCHREV, RSVD_31_8)); 222 223 /** GITS_PIDR2: GICv1 architecture revision. */ 224 #define GITS_CTRL_REG_PIDR2_ARCHREV_GICV1 0x1 225 /** GITS_PIDR2: GICv2 architecture revision. */ 226 #define GITS_CTRL_REG_PIDR2_ARCHREV_GICV2 0x2 227 /** GITS_PIDR2: GICv3 architecture revision. */ 228 #define GITS_CTRL_REG_PIDR2_ARCHREV_GICV3 0x3 229 /** GITS_PIDR2: GICv4 architecture revision. */ 230 #define GITS_CTRL_REG_PIDR2_ARCHREV_GICV4 0x4 231 232 /** GITS_TRANSLATER register. */ 206 233 #define GITS_TRANSLATION_REG_TRANSLATER 0x0040 207 234 -
trunk/include/VBox/gic.h
r108681 r108751 389 389 #define GIC_DIST_REG_PIDR2_OFF 0xffe8 390 390 /** Bit 4 - 7 - GIC architecture revision */ 391 # define GIC_DIST_REG_PIDR2_ARCH_REV ( RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) \ 392 | RT_BIT_32(7)) 393 # define GIC_DIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV) 391 # define GIC_DIST_REG_PIDR2_ARCHREV (RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7)) 392 # define GIC_DIST_REG_PIDR2_ARCHREV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCHREV) 394 393 /** GICv1 architecture revision. */ 395 # define GIC_DIST_REG_PIDR2_ARCH _REV_GICV10x1394 # define GIC_DIST_REG_PIDR2_ARCHREV_GICV1 0x1 396 395 /** GICv2 architecture revision. */ 397 # define GIC_DIST_REG_PIDR2_ARCH _REV_GICV20x2396 # define GIC_DIST_REG_PIDR2_ARCHREV_GICV2 0x2 398 397 /** GICv3 architecture revision. */ 399 # define GIC_DIST_REG_PIDR2_ARCH _REV_GICV30x3398 # define GIC_DIST_REG_PIDR2_ARCHREV_GICV3 0x3 400 399 /** GICv4 architecture revision. */ 401 # define GIC_DIST_REG_PIDR2_ARCH _REV_GICV40x4400 # define GIC_DIST_REG_PIDR2_ARCHREV_GICV4 0x4 402 401 /** @} */ 403 402 … … 527 526 #define GIC_REDIST_REG_PIDR2_OFF 0xffe8 528 527 /** Bit 4 - 7 - GIC architecture revision */ 529 # define GIC_REDIST_REG_PIDR2_ARCH_REV ( RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) \ 530 | RT_BIT_32(7)) 531 # define GIC_REDIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV) 528 # define GIC_REDIST_REG_PIDR2_ARCHREV (RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7)) 529 # define GIC_REDIST_REG_PIDR2_ARCHREV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_REDIST_REG_PIDR2_ARCHREV) 532 530 /** GICv1 architecture revision. */ 533 # define GIC_REDIST_REG_PIDR2_ARCH _REV_GICV10x1531 # define GIC_REDIST_REG_PIDR2_ARCHREV_GICV1 0x1 534 532 /** GICv2 architecture revision. */ 535 # define GIC_REDIST_REG_PIDR2_ARCH _REV_GICV20x2533 # define GIC_REDIST_REG_PIDR2_ARCHREV_GICV2 0x2 536 534 /** GICv3 architecture revision. */ 537 # define GIC_REDIST_REG_PIDR2_ARCH _REV_GICV30x3535 # define GIC_REDIST_REG_PIDR2_ARCHREV_GICV3 0x3 538 536 /** GICv4 architecture revision. */ 539 # define GIC_REDIST_REG_PIDR2_ARCH _REV_GICV40x4537 # define GIC_REDIST_REG_PIDR2_ARCHREV_GICV4 0x4 540 538 /** @} */ 541 539 … … 641 639 642 640 641 /** @name JEDEC codes for ARM. 642 * @{ */ 643 /** JEP106 identification code. */ 644 #define GIC_JEDEC_JEP106_IDENTIFICATION_CODE 0x3b 645 /** JEP106 continuation code. */ 646 #define GIC_JEDEC_JEP106_CONTINUATION_CODE 0x4 647 648 /** DES_0 - JEP106 identification code bits (3:0). */ 649 #define GIC_JEDEC_JEP10_DES_0(a_JepIdCode) ((a_JepIdCode) & 0xf) 650 /** DES_1 - JEP106 identification code bits (6:4). */ 651 #define GIC_JEDEC_JEP10_DES_1(a_JepIdCode) (((a_JepIdCode) >> 4) & 0x70) 652 /** @} */ 653 643 654 #endif /* !VBOX_INCLUDED_gic_h */ 644 655
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