Changeset 108758 in vbox for trunk/src/VBox/VMM

Timestamp:

Mar 26, 2025 4:05:20 PM (6 weeks ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

168185

Message:

VMM/Arm: Add ACTLR_EL1 to the CPU state, bugref:10392

Location:

trunk/src/VBox/VMM

Files:

• VMMR3/CPUM-armv8.cpp (modified) (4 diffs)
• VMMR3/CPUMDbg-armv8.cpp (modified) (1 diff)
• VMMR3/NEMR3Native-darwin-armv8.cpp (modified) (6 diffs)
• VMMR3/NEMR3Native-win-armv8.cpp (modified) (3 diffs)
• include/CPUMInternal.h (modified) (2 diffs)
• include/NEMInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMR3/CPUM-armv8.cpp

@@ -416 +416 @@
 };
 
+/**
+ * Additional fields for v2
+ */
+static const SSMFIELD g_aCpumCtxFieldsV2[] =
+{
+    SSMFIELD_ENTRY(         CPUMCTX, Actlr.u64),
+    SSMFIELD_ENTRY_TERM()
+};
+
 
 /**
@@ -641 +650 @@
 
         SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
+        SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFieldsV2, NULL);
 
         SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
@@ -669 +679 @@
      * Validate version.
      */
-    if (uVersion != CPUM_SAVED_STATE_VERSION)
+    if (   uVersion != CPUM_SAVED_STATE_VERSION
+        && uVersion != CPUM_SAVED_STATE_VERSION_ARMV8_V1)
     {
         AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
@@ -695 +706 @@
             rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
             AssertRCReturn(rc, rc);
+
+            if (uVersion == CPUM_SAVED_STATE_VERSION_ARMV8_V2)
+            {
+                rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFieldsV2, NULL);
+                AssertRCReturn(rc, rc);
+            }
 
             /*

trunk/src/VBox/VMM/VMMR3/CPUMDbg-armv8.cpp

@@ -313 +313 @@
     CPU_REG_RW_AS("elr_el1",        ELR_EL1,        U64, Elr,             cpumR3RegGet_Generic,         cpumR3RegSet_Generic,         NULL,                       NULL                    ),
     CPU_REG_RW_AS("vbar_el1",       VBAR_EL1,       U64, VBar,            cpumR3RegGet_Generic,         cpumR3RegSet_Generic,         NULL,                       NULL                    ),
+    CPU_REG_RW_AS("actlr_el1",      ACTLR_EL1,      U64, Actlr,           cpumR3RegGet_Generic,         cpumR3RegSet_Generic,         NULL,                       NULL                    ),
 
     CPU_REG_RW_AS("cnthctl_el2",    CNTHCTL_EL2,    U64, CntHCtlEl2,      cpumR3RegGet_Generic,         cpumR3RegSet_Generic,         NULL,                       NULL                    ),

trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp

@@ -142 +142 @@
     HV_GIC_INT_PERFORMANCE_MONITOR = 30
 } hv_gic_intid_t;
+
+# define HV_SYS_REG_ACTLR_EL1   (hv_sys_reg_t)0xc081
 
 #else
@@ -533 +535 @@
     { HV_SYS_REG_MDCCINT_EL1,       CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, MDccInt.u64)      }
 
+};
+/** Additional System registers to sync when on at least macOS Sequioa 15.0. */
+static const struct
+{
+    hv_sys_reg_t    enmHvReg;
+    uint32_t        fCpumExtrn;
+    uint32_t        offCpumCtx;
+} s_aCpumSysRegsSequioa[] =
+{
+    { HV_SYS_REG_ACTLR_EL1,         CPUMCTX_EXTRN_SYSREG_MISC,      RT_UOFFSETOF(CPUMCTX, Actlr.u64)        }
 };
 /** EL2 support system registers. */
@@ -905 +917 @@
                         "sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
                         "ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
-                        "vbar_el1=%016VR{vbar_el1}\n"
+                        "vbar_el1=%016VR{vbar_el1} actlr_el1=%016VR{actlr_el1}\n"
                         );
         if (pVM->nem.s.fEl2Enabled)
@@ -998 +1010 @@
     }
 
+    if (   pVM->nem.s.fMacOsSequia
+        && (fWhat & CPUMCTX_EXTRN_SYSREG_MISC))
+    {
+        for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegsSequioa); i++)
+        {
+            uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegsSequioa[i].offCpumCtx);
+            hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegsSequioa[i].enmHvReg, pu64);
+
+            /* Make sure only the TOS bit is kept as this seems to return 0x0000000000000c00 which fails during writes. */
+            /** @todo r=aeichner Need to find out where the value comes from, some bits were reverse engineered here
+             * https://github.com/AsahiLinux/docs/blob/main/docs/hw/cpu/system-registers.md#actlr_el1-arm-standard-not-standard
+             * But the ones being set are not documented. Maybe they are always set by the Hypervisor...
+             */
+            if (s_aCpumSysRegsSequioa[i].enmHvReg == HV_SYS_REG_ACTLR_EL1)
+                *pu64 &= RT_BIT_64(1);
+        }
+    }
+
     if (   hrc == HV_SUCCESS
         && (fWhat & CPUMCTX_EXTRN_SYSREG_EL2)
@@ -1098 +1128 @@
                 hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, *pu64);
             }
+        }
+    }
+
+    if (   pVM->nem.s.fMacOsSequia
+        && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_MISC))
+    {
+        for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegsSequioa); i++)
+        {
+            uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegsSequioa[i].offCpumCtx);
+            hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegsSequioa[i].enmHvReg, *pu64);
+            Assert(hrc == HV_SUCCESS);
         }
     }
@@ -1288 +1329 @@
         && hv_vm_config_get_el2_supported)
     {
+        pVM->nem.s.fMacOsSequia = true; /* hv_vm_config_get_el2_supported is only available on Sequioa 15.0. */
+
         hVmCfg = hv_vm_config_create();
 

trunk/src/VBox/VMM/VMMR3/NEMR3Native-win-armv8.cpp

@@ -1412 +1412 @@
         ADD_SYSREG64(WHvArm64RegisterTpidrEl0,      pVCpu->cpum.GstCtx.aTpIdr[0]);
         ADD_SYSREG64(WHvArm64RegisterTpidrEl1,      pVCpu->cpum.GstCtx.aTpIdr[1]);
+        ADD_SYSREG64(WHvArm64RegisterActlrEl1,      pVCpu->cpum.GstCtx.Actlr);
     }
 
@@ -1601 +1602 @@
         aenmNames[iReg++] = WHvArm64RegisterTpidrEl0;
         aenmNames[iReg++] = WHvArm64RegisterTpidrEl1;
+        aenmNames[iReg++] = WHvArm64RegisterActlrEl1;
     }
 
@@ -1798 +1800 @@
         GET_SYSREG64(pVCpu->cpum.GstCtx.aTpIdr[0],  WHvArm64RegisterTpidrEl0);
         GET_SYSREG64(pVCpu->cpum.GstCtx.aTpIdr[1],  WHvArm64RegisterTpidrEl1);
+        GET_SYSREG64(pVCpu->cpum.GstCtx.Actlr,      WHvArm64RegisterActlrEl1);
     }
 

trunk/src/VBox/VMM/include/CPUMInternal.h

@@ -116 +116 @@
 # define CPUM_SAVED_STATE_VERSION               CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4
 #elif defined(VBOX_VMM_TARGET_ARMV8)
-# define CPUM_SAVED_STATE_VERSION               CPUM_SAVED_STATE_VERSION_ARMV8_V1
+# define CPUM_SAVED_STATE_VERSION               CPUM_SAVED_STATE_VERSION_ARMV8_V2
 #endif
 
@@ -163 +163 @@
 
 #if defined(VBOX_VMM_TARGET_ARMV8)
+/** Adds ACTLR_EL1 to the ARMv8 saved state. */
+# define CPUM_SAVED_STATE_VERSION_ARMV8_V2      2
 /** The initial ARMv8 saved state. */
 # define CPUM_SAVED_STATE_VERSION_ARMV8_V1      1

trunk/src/VBox/VMM/include/NEMInternal.h

@@ -337 +337 @@
     /** Set if EL2 is enabled. */
     bool                        fEl2Enabled  : 1;
+    /** Set if we are running at least on macOS Sequioa 15.0. */
+    bool                        fMacOsSequia : 1;
 # ifdef VBOX_VMM_TARGET_ARMV8
     /** @name vTimer related state.