Changeset 108767 in vbox for trunk/src

Timestamp:

Mar 27, 2025 1:08:29 PM (3 weeks ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

168194

Message:

VMM/GIC: bugref:10877 Work-in-progress CWRITER, CREADR bits and fixes to register descriptions for GICR SGI/PPI registers.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/GICAll.cpp (modified) (7 diffs)
• VMMAll/GITSAll.cpp (modified) (3 diffs)
• include/GITSInternal.h (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/GICAll.cpp

@@ -187 +187 @@
 static const char *gicReDistGetRegDescription(uint16_t offReg)
 {
+    switch (offReg)
+    {
+        case GIC_REDIST_REG_CTLR_OFF:           return "GICR_CTLR";
+        case GIC_REDIST_REG_IIDR_OFF:           return "GICR_IIDR";
+        case GIC_REDIST_REG_TYPER_OFF:          return "GICR_TYPER";
+        case GIC_REDIST_REG_TYPER_AFFINITY_OFF: return "GICR_TYPER_AFF";
+        case GIC_REDIST_REG_STATUSR_OFF:        return "GICR_STATUSR";
+        case GIC_REDIST_REG_WAKER_OFF:          return "GICR_WAKER";
+        case GIC_REDIST_REG_MPAMIDR_OFF:        return "GICR_MPAMIDR";
+        case GIC_REDIST_REG_PARTIDR_OFF:        return "GICR_PARTIDR";
+        case GIC_REDIST_REG_SETLPIR_OFF:        return "GICR_SETLPIR";
+        case GIC_REDIST_REG_CLRLPIR_OFF:        return "GICR_CLRLPIR";
+        case GIC_REDIST_REG_PROPBASER_OFF:      return "GICR_PROPBASER";
+        case GIC_REDIST_REG_PENDBASER_OFF:      return "GICR_PENDBASER";
+        case GIC_REDIST_REG_INVLPIR_OFF:        return "GICR_INVLPIR";
+        case GIC_REDIST_REG_INVALLR_OFF:        return "GICR_INVALLR";
+        case GIC_REDIST_REG_SYNCR_OFF:          return "GICR_SYNCR";
+        case GIC_REDIST_REG_PIDR2_OFF:          return "GICR_PIDR2";
+        default:
+            return "<UNKNOWN>";
+    }
+}
+
+
+/**
+ * Gets the description of an SGI/PPI redistributor register given it's register
+ * offset.
+ *
+ * @returns The register description.
+ * @param   offReg  The redistributor register offset.
+ */
+static const char *gicReDistGetSgiPpiRegDescription(uint16_t offReg)
+{
     if (GIC_IS_REG_IN_RANGE(offReg, GIC_REDIST_SGI_PPI_REG_IGROUPR0_OFF,          GIC_REDIST_SGI_PPI_REG_IGROUPRnE_RANGE_SIZE))    return "GICR_IGROUPn";
     if (GIC_IS_REG_IN_RANGE(offReg, GIC_REDIST_SGI_PPI_REG_ISENABLER0_OFF,        GIC_REDIST_SGI_PPI_REG_ISENABLERnE_RANGE_SIZE))  return "GICR_ISENABLERn";
@@ -196 +229 @@
     if (GIC_IS_REG_IN_RANGE(offReg, GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START, GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_RANGE_SIZE)) return "GICR_IPREIORITYn";
     if (GIC_IS_REG_IN_RANGE(offReg, GIC_REDIST_SGI_PPI_REG_ICFGR0_OFF,            GIC_REDIST_SGI_PPI_REG_ICFGRnE_RANGE_SIZE))      return "GICR_ICFGRn";
+    if (GIC_IS_REG_IN_RANGE(offReg, GIC_REDIST_SGI_PPI_REG_INMIR0_OFF,            GIC_REDIST_SGI_PPI_REG_INMIRnE_RANGE_SIZE))      return "GICR_INMIRn";
     switch (offReg)
     {
-        case GIC_REDIST_REG_CTLR_OFF:           return "GICR_CTLR";
-        case GIC_REDIST_REG_IIDR_OFF:           return "GICR_IIDR";
-        case GIC_REDIST_REG_TYPER_OFF:          return "GICR_TYPER";
-        case GIC_REDIST_REG_TYPER_AFFINITY_OFF: return "GICR_TYPER_AFF";
-        case GIC_REDIST_REG_STATUSR_OFF:        return "GICR_STATUSR";
-        case GIC_REDIST_REG_PIDR2_OFF:          return "GICR_PIDR2";
+        case GIC_REDIST_SGI_PPI_REG_NSACR_OFF:      return "GICR_NSACR";
+        case GIC_REDIST_SGI_PPI_REG_IGRPMODR0_OFF:  return "GICR_IGRPMODR0";
+        case GIC_REDIST_SGI_PPI_REG_IGRPMODR1E_OFF: return "GICR_IGRPMODR1E";
+        case GIC_REDIST_SGI_PPI_REG_IGRPMODR2E_OFF: return "GICR_IGRPMODR2E";
         default:
             return "<UNKNOWN>";
     }
 }
-#endif
+#endif /* LOG_ENABLED */
 
 
@@ -2388 +2420 @@
     }
 
-    AssertReleaseMsgFailed(("offReg=%#x\n",  offReg));
+    AssertReleaseMsgFailed(("offReg=%#x (%s)\n", offReg, gicReDistGetSgiPpiRegDescription(offReg)));
     *puValue = 0;
     return VINF_SUCCESS;
@@ -2415 +2447 @@
             break;
         default:
-            AssertReleaseMsgFailed(("offReg=%#x uValue=%#RX32\n", offReg, uValue));
+            AssertReleaseMsgFailed(("offReg=%#x (%s) uValue=%#RX32\n", offReg, gicReDistGetRegDescription(offReg), uValue));
             break;
     }
@@ -2510 +2542 @@
     }
 
-    AssertReleaseMsgFailed(("offReg=%#RX16\n", offReg));
+    AssertReleaseMsgFailed(("offReg=%#RX16 (%s)\n", offReg, gicReDistGetSgiPpiRegDescription(offReg)));
     return VERR_INTERNAL_ERROR_2;
 }
@@ -3021 +3053 @@
  *
  * @param   pDevIns     The device instance.
+ * @remarks This is also called during VM reset, so do NOT remove values that are
+ *          cleared to zero!
  */
 static void gicInit(PPDMDEVINS pDevIns)
@@ -3051 +3085 @@
  * @param   pDevIns     The device instance.
  * @param   pVCpu       The cross context virtual CPU structure.
+ * @remarks This is also called during VM reset, so do NOT remove values that are
+ *          cleared to zero!
  */
 static void gicInitCpu(PPDMDEVINS pDevIns, PVMCPUCC pVCpu)

trunk/src/VBox/VMM/VMMAll/GITSAll.cpp

@@ -178 +178 @@
         }
 
+        case GITS_CTRL_REG_CBASER_OFF:
+            *puValue = pGitsDev->uCmdBaseReg.s.Lo;
+            break;
+
+        case GITS_CTRL_REG_CBASER_OFF + 4:
+            *puValue = pGitsDev->uCmdBaseReg.s.Hi;
+            break;
+
         default:
             AssertReleaseMsgFailed(("offReg=%#x (%s)\n", offReg, gitsGetCtrlRegDescription(offReg)));
@@ -219 +227 @@
             break;
 
+        case GITS_CTRL_REG_CBASER_OFF:
+            pGitsDev->uCmdBaseReg.s.Lo = uValue & RT_LO_U32(GITS_CTRL_REG_CBASER_RW_MASK);
+            break;
+
+        case GITS_CTRL_REG_CBASER_OFF + 4:
+            pGitsDev->uCmdBaseReg.s.Hi = uValue & RT_HI_U32(GITS_CTRL_REG_CBASER_RW_MASK);
+            break;
+
+        case GITS_CTRL_REG_CWRITER_OFF:
+            pGitsDev->uCmdWriteReg = uValue & RT_LO_U32(GITS_CTRL_REG_CWRITER_RW_MASK);
+            break;
+
+        case GITS_CTRL_REG_CWRITER_OFF + 4:
+            /* Upper 32-bits are all reserved, ignore write. Fedora 40 arm64 writes does this and probably other guests. */
+            Assert(uValue == 0);
+            break;
+
         default:
             AssertReleaseMsgFailed(("offReg=%#x (%s) uValue=%#RX32\n", offReg, gitsGetCtrlRegDescription(offReg), uValue));
@@ -244 +269 @@
     pGitsDev->fQuiescent            = true;
     RT_ZERO(pGitsDev->aItsTableRegs);
+    pGitsDev->uCmdBaseReg.u         = 0;
 }
 

trunk/src/VBox/VMM/include/GITSInternal.h

@@ -88 +88 @@
     /** The ITS table descriptor registers. */
     RTUINT64U               aItsTableRegs[8];
+    /** The ITS command queue base registers. */
+    RTUINT64U               uCmdBaseReg;
+    /** The ITS command write register. */
+    uint32_t                uCmdWriteReg;
+    /** The ITS command read register. */
+    uint32_t                uCmdReadReg;
     /** @} */
 
@@ -107 +113 @@
 typedef GITSDEV const *PCGITSDEV;
 AssertCompileSizeAlignment(GITSDEV, 8);
+AssertCompileMemberAlignment(GITSDEV, uArchRev, 8);
 
 DECL_HIDDEN_CALLBACK(void)         gitsInit(PGITSDEV pGitsDev);