Changeset 108826 in vbox

Timestamp:

Apr 2, 2025 9:12:22 AM (5 weeks ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

168272

Message:

VMM/GIC: bugref:10877 GIC ITS work-in-progress. LPI handling.

Location:

trunk

Files:

• include/VBox/gic.h (modified) (2 diffs)
• src/VBox/VMM/VMMAll/GICAll.cpp (modified) (5 diffs)
• src/VBox/VMM/include/GICInternal.h (modified) (1 diff)

trunk/include/VBox/gic.h

@@ -419 +419 @@
 #define GIC_REDIST_REG_CTLR_OFF                         0x0000
 /** Bit 0 - Enable LPIs. */
-#define GIC_DIST_REG_CTLR_ENABLE_LPI_BIT                0
-#define GIC_DIST_REG_CTLR_ENABLE_LPI                    RT_BIT_32(0)
+#define GIC_REDIST_REG_CTLR_ENABLE_LPI_BIT              0
+#define GIC_REDIST_REG_CTLR_ENABLE_LPI                  RT_BIT_32(0)
 /** Bit 1 - Clear Enable Support. */
-#define GIC_DIST_REG_CTLR_CES_BIT                       1
-#define GIC_DIST_REG_CTLR_CES                           RT_BIT_32(1)
-#define GIC_REDIST_REG_CTLR_CES_SET(a_Ces)              (((a_Ces) << GIC_DIST_REG_CTLR_CES_BIT) & GIC_DIST_REG_CTLR_CES)
+#define GIC_REDIST_REG_CTLR_CES_BIT                     1
+#define GIC_REDIST_REG_CTLR_CES                         RT_BIT_32(1)
+#define GIC_REDIST_REG_CTLR_CES_SET(a_Ces)              (((a_Ces) << GIC_REDIST_REG_CTLR_CES_BIT) & GIC_REDIST_REG_CTLR_CES)
 /** Bit 2 - LPI invalidate registers supported. */
-#define GIC_DIST_REG_CTLR_IR_BIT                        2
-#define GIC_DIST_REG_CTLR_IR                            RT_BIT_32(2)
+#define GIC_REDIST_REG_CTLR_IR_BIT                      2
+#define GIC_REDIST_REG_CTLR_IR                          RT_BIT_32(2)
 /** Bit 3 - Register Write Pending. */
-#define GIC_DIST_REG_CTLR_RWP_BIT                       3
-#define GIC_DIST_REG_CTLR_RWP                           RT_BIT_32(3)
+#define GIC_REDIST_REG_CTLR_RWP_BIT                     3
+#define GIC_REDIST_REG_CTLR_RWP                         RT_BIT_32(3)
 /** Bit 24 - Disable Processor selection for Group 0 interrupt. */
-#define GIC_DIST_REG_CTLR_DPG0_BIT                      24
-#define GIC_DIST_REG_CTLR_DPG0                          RT_BIT_32(24)
+#define GIC_REDIST_REG_CTLR_DPG0_BIT                    24
+#define GIC_REDIST_REG_CTLR_DPG0                        RT_BIT_32(24)
 /** Bit 25 - Disable Processor selection for Group 1 non-secure interrupt. */
-#define GIC_DIST_REG_CTLR_DPG1NS_BIT                    25
-#define GIC_DIST_REG_CTLR_DPG1NS                        RT_BIT_32(25)
+#define GIC_REDIST_REG_CTLR_DPG1NS_BIT                  25
+#define GIC_REDIST_REG_CTLR_DPG1NS                      RT_BIT_32(25)
 /** Bit 26 - Disable Processor selection for Group 1 secure interrupt. */
-#define GIC_DIST_REG_CTLR_DPG1S_BIT                     26
-#define GIC_DIST_REG_CTLR_DPG1S                         RT_BIT_32(26)
+#define GIC_REDIST_REG_CTLR_DPG1S_BIT                   26
+#define GIC_REDIST_REG_CTLR_DPG1S                       RT_BIT_32(26)
 /** Bit 31 - Upstream Write Pending. */
-#define GIC_DIST_REG_CTLR_UWP_BIT                       31
-#define GIC_DIST_REG_CTLR_UWP                           RT_BIT_32(31)
+#define GIC_REDIST_REG_CTLR_UWP_BIT                     31
+#define GIC_REDIST_REG_CTLR_UWP                         RT_BIT_32(31)
 
 /** Implementer Identification Register - RO. */
@@ -555 +555 @@
 /** Redistributor LPI Pending Table Base Address Register - RW. */
 #define GIC_REDIST_REG_PENDBASER_OFF                    0x0078
+#define GIC_BF_REDIST_REG_PENDBASER_RSVD_6_0_SHIFT      0
+#define GIC_BF_REDIST_REG_PENDBASER_RSVD_6_0_MASK       UINT64_C(0x000000000000007f)
+#define GIC_BF_REDIST_REG_PENDBASER_INNER_CACHE_SHIFT   7
+#define GIC_BF_REDIST_REG_PENDBASER_INNER_CACHE_MASK    UINT64_C(0x0000000000000380)
+#define GIC_BF_REDIST_REG_PENDBASER_SHAREABILITY_SHIFT  10
+#define GIC_BF_REDIST_REG_PENDBASER_SHAREABILITY_MASK   UINT64_C(0x0000000000000c00)
+#define GIC_BF_REDIST_REG_PENDBASER_RSVD_15_12_SHIFT    12
+#define GIC_BF_REDIST_REG_PENDBASER_RSVD_15_12_MASK     UINT64_C(0x000000000000f000)
+#define GIC_BF_REDIST_REG_PENDBASER_PHYS_ADDR_SHIFT     16
+#define GIC_BF_REDIST_REG_PENDBASER_PHYS_ADDR_MASK      UINT64_C(0x000fffffffff0000)
+#define GIC_BF_REDIST_REG_PENDBASER_RSVD_55_52_SHIFT    52
+#define GIC_BF_REDIST_REG_PENDBASER_RSVD_55_52_MASK     UINT64_C(0x00f0000000000000)
+#define GIC_BF_REDIST_REG_PENDBASER_OUTER_CACHE_SHIFT   56
+#define GIC_BF_REDIST_REG_PENDBASER_OUTER_CACHE_MASK    UINT64_C(0x0700000000000000)
+#define GIC_BF_REDIST_REG_PENDBASER_RSVD_61_59_SHIFT    59
+#define GIC_BF_REDIST_REG_PENDBASER_RSVD_61_59_MASK     UINT64_C(0x3800000000000000)
+#define GIC_BF_REDIST_REG_PENDBASER_PTZ_SHIFT           62
+#define GIC_BF_REDIST_REG_PENDBASER_PTZ_MASK            UINT64_C(0x4000000000000000)
+#define GIC_BF_REDIST_REG_PENDBASER_RSVD_63_SHIFT       63
+#define GIC_BF_REDIST_REG_PENDBASER_RSVD_63_MASK        UINT64_C(0x8000000000000000)
+RT_BF_ASSERT_COMPILE_CHECKS(GIC_BF_REDIST_REG_PENDBASER_, UINT64_C(0), UINT64_MAX,
+                            (RSVD_6_0, INNER_CACHE, SHAREABILITY, RSVD_15_12, PHYS_ADDR, RSVD_55_52, OUTER_CACHE, RSVD_61_59,
+                             PTZ, RSVD_63));
+#define GIC_REDIST_REG_PENDBASER_RW_MASK                (UINT64_MAX & ~(  GIC_BF_REDIST_REG_PENDBASER_RSVD_6_0_MASK   \
+                                                                        | GIC_BF_REDIST_REG_PENDBASER_RSVD_15_12_MASK \
+                                                                        | GIC_BF_REDIST_REG_PENDBASER_RSVD_55_52_MASK \
+                                                                        | GIC_BF_REDIST_REG_PENDBASER_RSVD_61_59_MASK \
+                                                                        | GIC_BF_REDIST_REG_PENDBASER_RSVD_63_MASK))
+
 /** Redistributor Invalidate LPI Register - WO. */
 #define GIC_REDIST_REG_INVLPIR_OFF                      0x00a0

trunk/src/VBox/VMM/VMMAll/GICAll.cpp

@@ -2290 +2290 @@
 DECLINLINE(VBOXSTRICTRC) gicReDistReadRegister(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint32_t idRedist, uint16_t offReg, uint32_t *puValue)
 {
-    PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
+    PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
     AssertRelease(idRedist == pVCpu->idCpu);
     switch (offReg)
@@ -2319 +2319 @@
             break;
         case GIC_REDIST_REG_CTLR_OFF:
-            *puValue = pGicDev->fEnableLpis ? GIC_DIST_REG_CTLR_ENABLE_LPI : 0
+            *puValue = (pGicDev->fEnableLpis ? GIC_REDIST_REG_CTLR_ENABLE_LPI : 0)
                      | GIC_REDIST_REG_CTLR_CES_SET(1);
             break;
@@ -2327 +2327 @@
         case GIC_REDIST_REG_PROPBASER_OFF + 4:
             *puValue = pGicDev->uLpiConfigBaseReg.s.Hi;
+            break;
+        case GIC_REDIST_REG_PENDBASER_OFF:
+            *puValue = pGicDev->uLpiPendingBaseReg.s.Lo;
+            break;
+        case GIC_REDIST_REG_PENDBASER_OFF + 4:
+            *puValue = pGicDev->uLpiPendingBaseReg.s.Hi;
             break;
         default:
@@ -2454 +2460 @@
             Assert(uValue == 0);
             break;
+        case GIC_REDIST_REG_CTLR_OFF:
+            pGicDev->fEnableLpis = RT_BOOL(uValue & GIC_REDIST_REG_CTLR_ENABLE_LPI);
+            break;
         case GIC_REDIST_REG_PROPBASER_OFF:
             pGicDev->uLpiConfigBaseReg.s.Lo = uValue & RT_LO_U32(GIC_REDIST_REG_PROPBASER_RW_MASK);
@@ -2459 +2468 @@
         case GIC_REDIST_REG_PROPBASER_OFF + 4:
             pGicDev->uLpiConfigBaseReg.s.Hi = uValue & RT_HI_U32(GIC_REDIST_REG_PROPBASER_RW_MASK);
+            break;
+        case GIC_REDIST_REG_PENDBASER_OFF:
+            pGicDev->uLpiPendingBaseReg.s.Lo = uValue & RT_LO_U32(GIC_REDIST_REG_PENDBASER_RW_MASK);
+            break;
+        case GIC_REDIST_REG_PENDBASER_OFF + 4:
+            pGicDev->uLpiPendingBaseReg.s.Hi = uValue & RT_HI_U32(GIC_REDIST_REG_PENDBASER_RW_MASK);
             break;
         default:

trunk/src/VBox/VMM/include/GICInternal.h

@@ -141 +141 @@
     /** ITS device state. */
     GITSDEV                     Gits;
-    /** LPI config table (priority + enabled bit). */
+    /** LPI config table. */
     uint8_t                     abLpiConfig[2048];
     /** LPI pending bitmap. */
     uint32_t                    bmLpiPending[64];
-    /** The LPI config table base address register (GICR_PROPBASER). */
+    /** The LPI config table base register (GICR_PROPBASER). */
     RTUINT64U                   uLpiConfigBaseReg;
-    /** Whether LPIs are enabled (GICR_CTLR.EnableLpis) common to all
-     *  redistributors). */
+    /** The LPI pending table base register (GICR_PENDBASER). */
+    RTUINT64U                   uLpiPendingBaseReg;
+    /** Whether LPIs are enabled (GICR_CTLR.EnableLpis of all redistributors). */
     bool                        fEnableLpis;
     /** Padding. */