VirtualBox

Changeset 108827 in vbox for trunk/src


Ignore:
Timestamp:
Apr 2, 2025 9:27:14 AM (13 days ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
168273
Message:

VMM/GIC: bugref:10877 nits.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/VMMAll/GICAll.cpp

    r108826 r108827  
    272272    {
    273273        uIntId = 0;
    274         AssertReleaseFailed();
     274        AssertReleaseMsgFailed(("idxIntr=%u\n", idxIntr));
    275275    }
    276276    Assert(   GIC_IS_INTR_SGI_OR_PPI(uIntId)
     
    302302    {
    303303        idxIntr = 0;
    304         AssertReleaseFailed();
     304        AssertReleaseMsgFailed(("uIntId=%u\n", uIntId));
    305305    }
    306306    Assert(idxIntr < sizeof(GICDEV::bmIntrPending) * 8);
     
    338338    {
    339339        uIntId = 0;
    340         AssertReleaseFailed();
     340        AssertReleaseMsgFailed(("idxIntr=%u\n", idxIntr));
    341341    }
    342342    Assert(GIC_IS_INTR_SGI_OR_PPI(uIntId) || GIC_IS_INTR_EXT_PPI(uIntId));
     
    365365    {
    366366        idxIntr = 0;
    367         AssertReleaseFailed();
     367        AssertReleaseMsgFailed(("uIntId=%u\n", uIntId));
    368368    }
    369369    Assert(idxIntr < sizeof(GICCPU::bmIntrPending) * 8);
     
    828828    }
    829829    else
    830         AssertReleaseFailed();
     830        AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n"));
    831831    LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrEnabled[idxReg]));
    832832    return VINF_SUCCESS;
     
    854854    }
    855855    else
    856         AssertReleaseFailed();
     856        AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n"));
    857857    LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrEnabled[idxReg]));
    858858    return VINF_SUCCESS;
     
    899899    }
    900900    else
    901         AssertReleaseFailed();
     901        AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n"));
    902902    LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrActive[idxReg]));
    903903    return VINF_SUCCESS;
     
    925925    }
    926926    else
    927         AssertReleaseFailed();
     927        AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n"));
    928928    LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrActive[idxReg]));
    929929    return VINF_SUCCESS;
     
    954954    else
    955955    {
    956         AssertReleaseFailed();
     956        AssertReleaseMsgFailed(("Unexpected (but not illegal) read to SGI/PPI register in distributor\n"));
    957957        *puValue = 0;
    958958    }
     
    985985    }
    986986    else
    987         AssertReleaseFailed();
     987        AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n"));
    988988    return VINF_SUCCESS;
    989989}
     
    10111011    else
    10121012    {
    1013         AssertReleaseFailed();
     1013        AssertReleaseMsgFailed(("Unexpected (but not illegal) read to SGI/PPI register in distributor\n"));
    10141014        *puValue = 0;
    10151015    }
     
    10391039    }
    10401040    else
    1041         AssertReleaseFailed();
     1041        AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n"));
    10421042    LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrPending[idxReg]));
    10431043    return VINF_SUCCESS;
     
    10651065    }
    10661066    else
    1067         AssertReleaseFailed();
     1067        AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n"));
    10681068    LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrPending[idxReg]));
    10691069    return VINF_SUCCESS;
     
    10891089    }
    10901090    else
    1091         AssertReleaseFailed();
     1091        AssertReleaseMsgFailed(("Unexpected (but not illegal) read to SGI/PPI register in distributor\n"));
    10921092    LogFlowFunc(("idxReg=%#x read %#x\n", idxReg, pGicDev->bmIntrConfig[idxReg]));
    10931093    return VINF_SUCCESS;
     
    11131113    }
    11141114    else
    1115         AssertReleaseFailed();
     1115        AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n"));
    11161116    LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrConfig[idxReg]));
    11171117    return VINF_SUCCESS;
     
    11371137    }
    11381138    else
    1139         AssertReleaseFailed();
     1139        AssertReleaseMsgFailed(("Unexpected (but not illegal) read to SGI/PPI register in distributor\n"));
    11401140    LogFlowFunc(("idxReg=%#x read %#x\n", idxReg, *puValue));
    11411141    return VINF_SUCCESS;
     
    11621162    }
    11631163    else
    1164         AssertReleaseFailed();
     1164        AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n"));
    11651165    return gicDistUpdateIrqState(pVM, pGicDev);
    11661166}
     
    22902290DECLINLINE(VBOXSTRICTRC) gicReDistReadRegister(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint32_t idRedist, uint16_t offReg, uint32_t *puValue)
    22912291{
     2292    PCVMCC   pVM     = pVCpu->CTX_SUFF(pVM);
    22922293    PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
    2293     AssertRelease(idRedist == pVCpu->idCpu);
     2294    Assert(idRedist == pVCpu->idCpu);
     2295
    22942296    switch (offReg)
    22952297    {
    22962298        case GIC_REDIST_REG_TYPER_OFF:
    2297         {
    2298             PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
    22992299            *puValue = (pVCpu->idCpu == pVM->cCpus - 1 ? GIC_REDIST_REG_TYPER_LAST : 0)
    23002300                     | GIC_REDIST_REG_TYPER_CPU_NUMBER_SET(idRedist)
     
    23042304            Assert(!pGicDev->fExtPpi || pGicDev->uMaxExtPpi > 0);
    23052305            break;
    2306         }
    23072306        case GIC_REDIST_REG_WAKER_OFF:
    23082307            *puValue = 0;
     
    27442743                    VMCPUSET_ADD(&DestCpuSet, idCpuTarget);
    27452744                else
    2746                     AssertReleaseFailed();
     2745                    AssertReleaseMsgFailed(("VCPU ID out-of-bounds %RU32, must be < %u\n", idCpuTarget, cCpus));
    27472746            }
    27482747        }
     
    28792878            break;
    28802879        default:
    2881             AssertReleaseFailed();
     2880            AssertReleaseMsgFailed(("u32Reg=%#RX32\n", u32Reg));
    28822881            break;
    28832882    }
     
    30693068            break;
    30703069        default:
    3071             AssertReleaseFailed();
     3070            AssertReleaseMsgFailed(("u32Reg=%#RX32\n", u32Reg));
    30723071            break;
    30733072    }
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette