- Timestamp:
- Apr 2, 2025 9:27:14 AM (13 days ago)
- svn:sync-xref-src-repo-rev:
- 168273
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/GICAll.cpp
r108826 r108827 272 272 { 273 273 uIntId = 0; 274 AssertRelease Failed();274 AssertReleaseMsgFailed(("idxIntr=%u\n", idxIntr)); 275 275 } 276 276 Assert( GIC_IS_INTR_SGI_OR_PPI(uIntId) … … 302 302 { 303 303 idxIntr = 0; 304 AssertRelease Failed();304 AssertReleaseMsgFailed(("uIntId=%u\n", uIntId)); 305 305 } 306 306 Assert(idxIntr < sizeof(GICDEV::bmIntrPending) * 8); … … 338 338 { 339 339 uIntId = 0; 340 AssertRelease Failed();340 AssertReleaseMsgFailed(("idxIntr=%u\n", idxIntr)); 341 341 } 342 342 Assert(GIC_IS_INTR_SGI_OR_PPI(uIntId) || GIC_IS_INTR_EXT_PPI(uIntId)); … … 365 365 { 366 366 idxIntr = 0; 367 AssertRelease Failed();367 AssertReleaseMsgFailed(("uIntId=%u\n", uIntId)); 368 368 } 369 369 Assert(idxIntr < sizeof(GICCPU::bmIntrPending) * 8); … … 828 828 } 829 829 else 830 AssertRelease Failed();830 AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n")); 831 831 LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrEnabled[idxReg])); 832 832 return VINF_SUCCESS; … … 854 854 } 855 855 else 856 AssertRelease Failed();856 AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n")); 857 857 LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrEnabled[idxReg])); 858 858 return VINF_SUCCESS; … … 899 899 } 900 900 else 901 AssertRelease Failed();901 AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n")); 902 902 LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrActive[idxReg])); 903 903 return VINF_SUCCESS; … … 925 925 } 926 926 else 927 AssertRelease Failed();927 AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n")); 928 928 LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrActive[idxReg])); 929 929 return VINF_SUCCESS; … … 954 954 else 955 955 { 956 AssertRelease Failed();956 AssertReleaseMsgFailed(("Unexpected (but not illegal) read to SGI/PPI register in distributor\n")); 957 957 *puValue = 0; 958 958 } … … 985 985 } 986 986 else 987 AssertRelease Failed();987 AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n")); 988 988 return VINF_SUCCESS; 989 989 } … … 1011 1011 else 1012 1012 { 1013 AssertRelease Failed();1013 AssertReleaseMsgFailed(("Unexpected (but not illegal) read to SGI/PPI register in distributor\n")); 1014 1014 *puValue = 0; 1015 1015 } … … 1039 1039 } 1040 1040 else 1041 AssertRelease Failed();1041 AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n")); 1042 1042 LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrPending[idxReg])); 1043 1043 return VINF_SUCCESS; … … 1065 1065 } 1066 1066 else 1067 AssertRelease Failed();1067 AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n")); 1068 1068 LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrPending[idxReg])); 1069 1069 return VINF_SUCCESS; … … 1089 1089 } 1090 1090 else 1091 AssertRelease Failed();1091 AssertReleaseMsgFailed(("Unexpected (but not illegal) read to SGI/PPI register in distributor\n")); 1092 1092 LogFlowFunc(("idxReg=%#x read %#x\n", idxReg, pGicDev->bmIntrConfig[idxReg])); 1093 1093 return VINF_SUCCESS; … … 1113 1113 } 1114 1114 else 1115 AssertRelease Failed();1115 AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n")); 1116 1116 LogFlowFunc(("idxReg=%#x written %#x\n", idxReg, pGicDev->bmIntrConfig[idxReg])); 1117 1117 return VINF_SUCCESS; … … 1137 1137 } 1138 1138 else 1139 AssertRelease Failed();1139 AssertReleaseMsgFailed(("Unexpected (but not illegal) read to SGI/PPI register in distributor\n")); 1140 1140 LogFlowFunc(("idxReg=%#x read %#x\n", idxReg, *puValue)); 1141 1141 return VINF_SUCCESS; … … 1162 1162 } 1163 1163 else 1164 AssertRelease Failed();1164 AssertReleaseMsgFailed(("Unexpected (but not illegal) write to SGI/PPI register in distributor\n")); 1165 1165 return gicDistUpdateIrqState(pVM, pGicDev); 1166 1166 } … … 2290 2290 DECLINLINE(VBOXSTRICTRC) gicReDistReadRegister(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint32_t idRedist, uint16_t offReg, uint32_t *puValue) 2291 2291 { 2292 PCVMCC pVM = pVCpu->CTX_SUFF(pVM); 2292 2293 PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV); 2293 AssertRelease(idRedist == pVCpu->idCpu); 2294 Assert(idRedist == pVCpu->idCpu); 2295 2294 2296 switch (offReg) 2295 2297 { 2296 2298 case GIC_REDIST_REG_TYPER_OFF: 2297 {2298 PCVMCC pVM = pVCpu->CTX_SUFF(pVM);2299 2299 *puValue = (pVCpu->idCpu == pVM->cCpus - 1 ? GIC_REDIST_REG_TYPER_LAST : 0) 2300 2300 | GIC_REDIST_REG_TYPER_CPU_NUMBER_SET(idRedist) … … 2304 2304 Assert(!pGicDev->fExtPpi || pGicDev->uMaxExtPpi > 0); 2305 2305 break; 2306 }2307 2306 case GIC_REDIST_REG_WAKER_OFF: 2308 2307 *puValue = 0; … … 2744 2743 VMCPUSET_ADD(&DestCpuSet, idCpuTarget); 2745 2744 else 2746 AssertRelease Failed();2745 AssertReleaseMsgFailed(("VCPU ID out-of-bounds %RU32, must be < %u\n", idCpuTarget, cCpus)); 2747 2746 } 2748 2747 } … … 2879 2878 break; 2880 2879 default: 2881 AssertRelease Failed();2880 AssertReleaseMsgFailed(("u32Reg=%#RX32\n", u32Reg)); 2882 2881 break; 2883 2882 } … … 3069 3068 break; 3070 3069 default: 3071 AssertRelease Failed();3070 AssertReleaseMsgFailed(("u32Reg=%#RX32\n", u32Reg)); 3072 3071 break; 3073 3072 }
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