Changeset 109014 in vbox
- Timestamp:
- Apr 17, 2025 12:33:52 PM (3 weeks ago)
- svn:sync-xref-src-repo-rev:
- 168542
- Location:
- trunk
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/sup.h
r106998 r109014 196 196 typedef const SUPHWVIRTMSRS *PCSUPHWVIRTMSRS; 197 197 198 #if defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING) 199 /** 200 * ARM system register value. 201 */ 202 typedef struct SUPARMSYSREGVAL 203 { 204 uint32_t idReg; 205 uint32_t fFlags; 206 uint64_t uValue; 207 } SUPARMSYSREGVAL; 208 /** Pointer to an ARM system register value. */ 209 typedef SUPARMSYSREGVAL *PSUPARMSYSREGVAL; 210 /** Pointer to a const ARM system register value. */ 211 typedef SUPARMSYSREGVAL const *PCSUPARMSYSREGVAL; 212 213 /** @name SUP_ARM_SYS_REG_F_XXX - Flags for SUPR3ArmQuerySysRegs. 214 * @{ */ 215 /** Include registers with value zero (default is to skip them). */ 216 # define SUP_ARM_SYS_REG_F_INC_ZERO_REG_VAL RT_BIT_32(0) 217 /** Extended register set (special build). 218 * @note currently don't do anything. */ 219 # define SUP_ARM_SYS_REG_F_EXTENDED RT_BIT_32(1) 220 /** Valid flags for SUPR3ArmQuerySysRegs. */ 221 # define SUP_ARM_SYS_REG_F_VALID_MASK UINT32_C(0x00000003) 222 /** @} */ 223 #endif /* defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING) */ 198 224 199 225 /** … … 1936 1962 uintptr_t uArg3, uintptr_t uArg4); 1937 1963 1964 #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) || defined(DOXYGEN_RUNNING) 1965 1938 1966 /** 1939 1967 * Attempts to read the value of an MSR. … … 1946 1974 * @param pfGp Where to store the \#GP indicator for the read 1947 1975 * operation. 1976 * @note Only available on AMD64 & x86. 1948 1977 */ 1949 1978 SUPR3DECL(int) SUPR3MsrProberRead(uint32_t uMsr, RTCPUID idCpu, uint64_t *puValue, bool *pfGp); … … 1959 1988 * @param pfGp Where to store the \#GP indicator for the write 1960 1989 * operation. 1990 * @note Only available on AMD64 & x86. 1961 1991 */ 1962 1992 SUPR3DECL(int) SUPR3MsrProberWrite(uint32_t uMsr, RTCPUID idCpu, uint64_t uValue, bool *pfGp); … … 1972 2002 * @param fOrMask The bits to set before writing. 1973 2003 * @param pResult The result buffer. 2004 * @note Only available on AMD64 & x86. 1974 2005 */ 1975 2006 SUPR3DECL(int) SUPR3MsrProberModify(uint32_t uMsr, RTCPUID idCpu, uint64_t fAndMask, uint64_t fOrMask, … … 1989 2020 * SUPR3MsrProberModify. 1990 2021 * @param pResult The result buffer. 2022 * @note Only available on AMD64 & x86. 1991 2023 */ 1992 2024 SUPR3DECL(int) SUPR3MsrProberModifyEx(uint32_t uMsr, RTCPUID idCpu, uint64_t fAndMask, uint64_t fOrMask, bool fFaster, 1993 2025 PSUPMSRPROBERMODIFYRESULT pResult); 2026 2027 #endif /* defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) || defined(DOXYGEN_RUNNING) */ 2028 2029 #if defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING) 2030 /** 2031 * Gets a collection of ARM system registers useful for identify 2032 * CPU capatbilites. 2033 * 2034 * @returns VBox status code. 2035 * @param fFlags Query flags, SUP_ARM_SYS_REG_F_XXX. 2036 * @param 2037 * @param cMaxRegs Maximum number of registers @a paSysRegValues 2038 * may hold. 2039 * @param pcRegsReturned Number of registers returned. 2040 * @param pcRegsAvailable Number of registers available, optional. 2041 * If higher than @a *pcRegsReturned, try again 2042 * with an array of this size to get them all. 2043 * @param paSysRegValues Array where to store the register values and 2044 * associated info. 2045 */ 2046 SUPR3DECL(int) SUPR3ArmQuerySysRegs(uint32_t fFlags, uint32_t cMaxRegs, 2047 uint32_t *pcRegsReturned, uint32_t *pcRegsAvailable, PSUPARMSYSREGVAL paSysRegValues); 2048 #endif /* defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING) */ 1994 2049 1995 2050 /** -
trunk/src/VBox/HostDrivers/Support/SUPDrv.cpp
r106640 r109014 77 77 #include <iprt/uint128.h> 78 78 #include <iprt/x86.h> 79 #ifdef RT_ARCH_ARM64 80 # include <iprt/armv8.h> 81 #endif 79 82 80 83 #include <VBox/param.h> … … 184 187 static int supdrvIOCtl_CallServiceModule(PSUPDRVDEVEXT pDevExt, PSUPDRVSESSION pSession, PSUPCALLSERVICE pReq); 185 188 static int supdrvIOCtl_LoggerSettings(PSUPLOGGERSETTINGS pReq); 186 static int supdrvIOCtl_MsrProber(PSUPDRVDEVEXT pDevExt, PSUPMSRPROBER pReq); 189 #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) 190 static int supdrvIOCtl_X86MsrProber(PSUPDRVDEVEXT pDevExt, PSUPMSRPROBER pReq); 191 #endif 192 #if defined(RT_ARCH_ARM64) 193 static int supdrvIOCtl_ArmGetSysRegs(PSUPARMGETSYSREGS pReq, uint32_t cMaxRegs, uint32_t fFlags); 194 #endif 187 195 static int supdrvIOCtl_ResumeSuspendedKbds(void); 188 196 … … 2168 2176 /* validate */ 2169 2177 PSUPPAGEALLOCEX pReq = (PSUPPAGEALLOCEX)pReqHdr; 2170 REQ_CHECK_ EXPR(SUP_IOCTL_PAGE_ALLOC_EX, pReq->Hdr.cbIn <=SUP_IOCTL_PAGE_ALLOC_EX_SIZE_IN);2171 REQ_CHECK_SIZE S_EX(SUP_IOCTL_PAGE_ALLOC_EX, SUP_IOCTL_PAGE_ALLOC_EX_SIZE_IN, SUP_IOCTL_PAGE_ALLOC_EX_SIZE_OUT(pReq->u.In.cPages));2178 REQ_CHECK_SIZE_IN(SUP_IOCTL_PAGE_ALLOC_EX, SUP_IOCTL_PAGE_ALLOC_EX_SIZE_IN); 2179 REQ_CHECK_SIZE_OUT(SUP_IOCTL_PAGE_ALLOC_EX, SUP_IOCTL_PAGE_ALLOC_EX_SIZE_OUT(pReq->u.In.cPages)); 2172 2180 REQ_CHECK_EXPR_FMT(pReq->u.In.fKernelMapping || pReq->u.In.fUserMapping, 2173 2181 ("SUP_IOCTL_PAGE_ALLOC_EX: No mapping requested!\n")); … … 2485 2493 } 2486 2494 2495 #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) 2487 2496 case SUP_CTL_CODE_NO_SIZE(SUP_IOCTL_MSR_PROBER): 2488 2497 { … … 2493 2502 pReq->u.In.enmOp > SUPMSRPROBEROP_INVALID && pReq->u.In.enmOp < SUPMSRPROBEROP_END); 2494 2503 2495 pReqHdr->rc = supdrvIOCtl_MsrProber(pDevExt, pReq); 2504 pReqHdr->rc = supdrvIOCtl_X86MsrProber(pDevExt, pReq); 2505 2496 2506 return 0; 2497 2507 } 2508 2509 #elif defined(RT_ARCH_ARM64) 2510 case SUP_CTL_CODE_NO_SIZE(SUP_IOCTL_ARM_GET_SYSREGS): 2511 { 2512 /* validate */ 2513 PSUPARMGETSYSREGS pReq = (PSUPARMGETSYSREGS)pReqHdr; 2514 uint32_t const cMaxRegs = pReq->Hdr.cbOut <= RT_UOFFSETOF(SUPARMGETSYSREGS, u.Out.aRegs) ? 0 2515 : (pReq->Hdr.cbOut - RT_UOFFSETOF(SUPARMGETSYSREGS, u.Out.aRegs)) / sizeof(SUPARMSYSREGVAL); 2516 REQ_CHECK_SIZE_IN(SUP_IOCTL_ARM_GET_SYSREGS, SUP_IOCTL_ARM_GET_SYSREGS_SIZE_IN); 2517 2518 REQ_CHECK_SIZE_OUT(SUP_IOCTL_ARM_GET_SYSREGS, SUP_IOCTL_ARM_GET_SYSREGS_SIZE_OUT(cMaxRegs)); 2519 REQ_CHECK_EXPR_FMT(!(pReq->u.In.fFlags & SUP_ARM_SYS_REG_F_VALID_MASK), 2520 ("SUP_IOCTL_ARM_GET_SYSREGS: fFlags=%#x!\n", pReq->u.In.fFlags)); 2521 2522 pReqHdr->rc = supdrvIOCtl_ArmGetSysRegs(pReq, cMaxRegs, pReq->u.In.fFlags); 2523 if (RT_FAILURE(pReqHdr->rc)) 2524 pReqHdr->cbOut = sizeof(*pReqHdr); 2525 2526 return 0; 2527 } 2528 #endif 2498 2529 2499 2530 case SUP_CTL_CODE_NO_SIZE(SUP_IOCTL_RESUME_SUSPENDED_KBDS): … … 7162 7193 7163 7194 7195 #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) 7164 7196 /** 7165 7197 * Implements the MSR prober operations. … … 7169 7201 * @param pReq The request. 7170 7202 */ 7171 static int supdrvIOCtl_ MsrProber(PSUPDRVDEVEXT pDevExt, PSUPMSRPROBER pReq)7172 { 7173 # ifdef SUPDRV_WITH_MSR_PROBER7203 static int supdrvIOCtl_X86MsrProber(PSUPDRVDEVEXT pDevExt, PSUPMSRPROBER pReq) 7204 { 7205 # ifdef SUPDRV_WITH_MSR_PROBER 7174 7206 RTCPUID const idCpu = pReq->u.In.idCpu == UINT32_MAX ? NIL_RTCPUID : pReq->u.In.idCpu; 7175 7207 int rc; … … 7216 7248 RT_NOREF1(pDevExt); 7217 7249 return rc; 7218 # else7250 # else 7219 7251 RT_NOREF2(pDevExt, pReq); 7220 7252 return VERR_NOT_IMPLEMENTED; 7221 #endif 7222 } 7253 # endif 7254 } 7255 #endif /* RT_ARCH_AMD64 || RT_ARCH_X86 */ 7256 7257 7258 #if defined(RT_ARCH_ARM64) 7259 /** 7260 * Implements the ARM ID (and system) register getter. 7261 * 7262 * @returns VBox status code. 7263 * @param pReq The request. 7264 * @param cMaxRegs The maximum number of register we can return. 7265 * @param fFlags The request flags. 7266 */ 7267 static int supdrvIOCtl_ArmGetSysRegs(PSUPARMGETSYSREGS pReq, uint32_t const cMaxRegs, uint32_t fFlags) 7268 { 7269 /* 7270 * Reader macro. 7271 */ 7272 uint32_t idxReg = 0; 7273 # ifdef _MSC_VER 7274 # define COMPILER_READ_SYS_REG(a_u64Dst, a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \ 7275 (a_u64Dst) = (uint64_t)_ReadStatusReg(ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) & 0x7fff) 7276 # define COMPILER_READ_SYS_REG_NAMED(a_u64Dst, a_SysRegName) \ 7277 (a_u64Dst) = (uint64_t)_ReadStatusReg(RT_CONCAT(ARMV8_AARCH64_SYSREG_,a_SysRegName) & 0x7fff) 7278 # else 7279 # define COMPILER_READ_SYS_REG(a_u64Dst, a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \ 7280 __asm__ __volatile__ ("mrs %0, s" #a_Op0 "_" #a_Op1 "_c" #a_CRn "_c" #a_CRm "_" #a_Op2 : "=r" (a_u64Dst)) 7281 # define COMPILER_READ_SYS_REG_NAMED(a_u64Dst, a_SysRegName) \ 7282 __asm__ __volatile__ ("mrs %0, " #a_SysRegName : "=r" (a_u64Dst)) 7283 # endif 7284 # define READ_SYS_REG_UNDEF(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) do { \ 7285 uint64_t uTmp = 0; \ 7286 COMPILER_READ_SYS_REG(uTmp, a_Op0, a_Op1, a_CRn, a_CRm, a_Op2); \ 7287 if (uTmp != 0 || (fFlags & SUP_ARM_SYS_REG_F_INC_ZERO_REG_VAL)) \ 7288 { \ 7289 if (idxReg < cMaxRegs) \ 7290 { \ 7291 pReq->u.Out.aRegs[idxReg].uValue = uTmp; \ 7292 pReq->u.Out.aRegs[idxReg].idReg = ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2); \ 7293 pReq->u.Out.aRegs[idxReg].fFlags = 0; \ 7294 } \ 7295 idxReg += 1; \ 7296 } \ 7297 } while (0) 7298 7299 # define READ_SYS_REG_NAMED(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) do { \ 7300 AssertCompile( ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \ 7301 == RT_CONCAT(ARMV8_AARCH64_SYSREG_,a_SysRegName)); \ 7302 READ_SYS_REG_UNDEF(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2); \ 7303 } while (0) 7304 7305 # define READ_SYS_REG__TODO(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2, a_SysRegName) READ_SYS_REG_UNDEF(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) 7306 /* 7307 * Standard ID registers. 7308 */ 7309 READ_SYS_REG_NAMED(3, 0, 0, 0, 0, MIDR_EL1); 7310 READ_SYS_REG_NAMED(3, 0, 0, 0, 5, MPIDR_EL1); 7311 READ_SYS_REG_NAMED(3, 0, 0, 0, 6, REVIDR_EL1); 7312 READ_SYS_REG__TODO(3, 1, 0, 0, 0, CCSIDR_EL1); 7313 READ_SYS_REG__TODO(3, 1, 0, 0, 1, CLIDR_EL1); 7314 READ_SYS_REG__TODO(3, 1, 0, 0, 7, AIDR_EL1); 7315 READ_SYS_REG_NAMED(3, 3, 0, 0, 7, DCZID_EL0); 7316 READ_SYS_REG_NAMED(3, 3,14, 0, 0, CNTFRQ_EL0); 7317 7318 7319 READ_SYS_REG_NAMED(3, 0, 0, 4, 0, ID_AA64PFR0_EL1); 7320 READ_SYS_REG_NAMED(3, 0, 0, 4, 1, ID_AA64PFR1_EL1); 7321 READ_SYS_REG_UNDEF(3, 0, 0, 4, 2); 7322 READ_SYS_REG_UNDEF(3, 0, 0, 4, 3); 7323 READ_SYS_REG_NAMED(3, 0, 0, 4, 4, ID_AA64ZFR0_EL1); 7324 READ_SYS_REG_NAMED(3, 0, 0, 4, 5, ID_AA64SMFR0_EL1); 7325 READ_SYS_REG_UNDEF(3, 0, 0, 4, 6); 7326 READ_SYS_REG_UNDEF(3, 0, 0, 4, 7); 7327 7328 READ_SYS_REG_NAMED(3, 0, 0, 5, 0, ID_AA64DFR0_EL1); 7329 READ_SYS_REG_NAMED(3, 0, 0, 5, 1, ID_AA64DFR1_EL1); 7330 READ_SYS_REG_UNDEF(3, 0, 0, 5, 2); 7331 READ_SYS_REG_UNDEF(3, 0, 0, 5, 3); 7332 READ_SYS_REG_NAMED(3, 0, 0, 5, 4, ID_AA64AFR0_EL1); 7333 READ_SYS_REG_NAMED(3, 0, 0, 5, 5, ID_AA64AFR1_EL1); 7334 READ_SYS_REG_UNDEF(3, 0, 0, 5, 6); 7335 READ_SYS_REG_UNDEF(3, 0, 0, 5, 7); 7336 7337 READ_SYS_REG_NAMED(3, 0, 0, 6, 0, ID_AA64ISAR0_EL1); 7338 READ_SYS_REG_NAMED(3, 0, 0, 6, 1, ID_AA64ISAR1_EL1); 7339 READ_SYS_REG_NAMED(3, 0, 0, 6, 2, ID_AA64ISAR2_EL1); 7340 READ_SYS_REG__TODO(3, 0, 0, 6, 3, ID_AA64ISAR3_EL1); 7341 READ_SYS_REG_UNDEF(3, 0, 0, 6, 4); 7342 READ_SYS_REG_UNDEF(3, 0, 0, 6, 5); 7343 READ_SYS_REG_UNDEF(3, 0, 0, 6, 6); 7344 READ_SYS_REG_UNDEF(3, 0, 0, 6, 7); 7345 7346 READ_SYS_REG_NAMED(3, 0, 0, 7, 0, ID_AA64MMFR0_EL1); 7347 READ_SYS_REG_NAMED(3, 0, 0, 7, 1, ID_AA64MMFR1_EL1); 7348 READ_SYS_REG_NAMED(3, 0, 0, 7, 2, ID_AA64MMFR2_EL1); 7349 READ_SYS_REG__TODO(3, 0, 0, 7, 3, ID_AA64MMFR3_EL1); 7350 READ_SYS_REG__TODO(3, 0, 0, 7, 4, ID_AA64MMFR4_EL1); 7351 READ_SYS_REG_UNDEF(3, 0, 0, 7, 5); 7352 READ_SYS_REG_UNDEF(3, 0, 0, 7, 6); 7353 READ_SYS_REG_UNDEF(3, 0, 0, 7, 7); 7354 7355 /* AArch32 feature registers: */ 7356 /** @todo do these need to be if-aarch32-supported-guarded? */ 7357 READ_SYS_REG_NAMED(3, 0, 0, 1, 0, ID_PFR0_EL1); 7358 READ_SYS_REG_NAMED(3, 0, 0, 1, 1, ID_PFR1_EL1); 7359 7360 READ_SYS_REG_NAMED(3, 0, 0, 1, 2, ID_DFR0_EL1); 7361 7362 READ_SYS_REG_NAMED(3, 0, 0, 1, 3, ID_AFR0_EL1); 7363 7364 READ_SYS_REG_NAMED(3, 0, 0, 1, 4, ID_MMFR0_EL1); 7365 READ_SYS_REG_NAMED(3, 0, 0, 1, 5, ID_MMFR1_EL1); 7366 READ_SYS_REG_NAMED(3, 0, 0, 1, 6, ID_MMFR2_EL1); 7367 READ_SYS_REG_NAMED(3, 0, 0, 1, 7, ID_MMFR3_EL1); 7368 7369 READ_SYS_REG_NAMED(3, 0, 0, 2, 0, ID_ISAR0_EL1); 7370 READ_SYS_REG_NAMED(3, 0, 0, 2, 1, ID_ISAR1_EL1); 7371 READ_SYS_REG_NAMED(3, 0, 0, 2, 2, ID_ISAR2_EL1); 7372 READ_SYS_REG_NAMED(3, 0, 0, 2, 3, ID_ISAR3_EL1); 7373 READ_SYS_REG_NAMED(3, 0, 0, 2, 4, ID_ISAR4_EL1); 7374 READ_SYS_REG_NAMED(3, 0, 0, 2, 5, ID_ISAR5_EL1); 7375 7376 READ_SYS_REG_NAMED(3, 0, 0, 2, 6, ID_MMFR4_EL1); 7377 7378 READ_SYS_REG_NAMED(3, 0, 0, 2, 7, ID_ISAR6_EL1); 7379 7380 READ_SYS_REG_NAMED(3, 0, 0, 3, 0, MVFR0_EL1); 7381 READ_SYS_REG_NAMED(3, 0, 0, 3, 1, MVFR1_EL1); 7382 READ_SYS_REG_NAMED(3, 0, 0, 3, 2, MVFR2_EL1); 7383 7384 READ_SYS_REG_NAMED(3, 0, 0, 3, 4, ID_PFR2_EL1); 7385 7386 READ_SYS_REG_NAMED(3, 0, 0, 3, 5, ID_DFR1_EL1); 7387 7388 READ_SYS_REG_NAMED(3, 0, 0, 3, 6, ID_MMFR5_EL1); 7389 7390 /* Feature dependent registers: */ 7391 uint64_t fMmfr2; 7392 COMPILER_READ_SYS_REG_NAMED(fMmfr2, ID_AA64MMFR2_EL1); 7393 if ((fMmfr2 & (UINT32_C(15) << 20) /*CCIDX*/) == RT_BIT_32(20)) 7394 READ_SYS_REG__TODO(3, 1, 0, 0, 2, CCSIDR2_EL1); /*?*/ 7395 7396 uint64_t fPfr0; 7397 COMPILER_READ_SYS_REG_NAMED(fPfr0, ID_AA64PFR0_EL1); 7398 if (fPfr0 & ARMV8_ID_AA64PFR0_EL1_RAS_MASK) 7399 READ_SYS_REG_NAMED(3, 0, 5, 3, 0, ERRIDR_EL1); 7400 7401 uint64_t fPfr1; 7402 COMPILER_READ_SYS_REG_NAMED(fPfr1, ID_AA64PFR1_EL1); 7403 if ((fPfr1 & ARMV8_ID_AA64PFR1_EL1_MTE_MASK) >= (ARMV8_ID_AA64PFR1_EL1_MTE_FULL << ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT)) 7404 READ_SYS_REG__TODO(3, 1, 0, 0, 4, GMID_EL1); 7405 if ((fPfr0 & ARMV8_ID_AA64PFR0_EL1_MPAM_MASK) || (fPfr1 & ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK)) 7406 { 7407 READ_SYS_REG__TODO(3, 0, 10, 4, 4, MPAMIDR_EL1); 7408 uint64_t fMpamidr; 7409 COMPILER_READ_SYS_REG(fMpamidr, 3, 0, 10, 4, 4); 7410 if (fMpamidr & RT_BIT_64(56) /*HAS_BW_CTRL*/) 7411 READ_SYS_REG__TODO(3, 0, 10, 4, 5, MPAMBWIDR_EL1); 7412 } 7413 7414 uint64_t fDfr0; 7415 COMPILER_READ_SYS_REG_NAMED(fDfr0, ID_AA64DFR0_EL1); 7416 if (fDfr0 & (UINT64_C(15) << 32) /*PMSVer*/) 7417 { 7418 READ_SYS_REG__TODO(3, 0, 9, 10, 7, PMBIDR_EL1); 7419 READ_SYS_REG__TODO(3, 0, 9, 8, 7, PMSIDR_EL1); 7420 } 7421 if (fDfr0 & (UINT64_C(15) << 44) /*TraceBuffer*/) 7422 READ_SYS_REG__TODO(3, 0, 9, 11, 7, TRBIDR_EL1); 7423 7424 /** @todo FEAT_ETE: READ_SYS_REG(TRCIDR0); */ 7425 /** @todo FEAT_ETE: READ_SYS_REG(TRCIDR1); */ 7426 /** @todo FEAT_ETE: READ_SYS_REG(TRCIDR2); */ 7427 /** @todo FEAT_ETE: READ_SYS_REG(TRCIDR3); */ 7428 /** @todo FEAT_ETE: READ_SYS_REG(TRCIDR4); */ 7429 /** @todo FEAT_ETE: READ_SYS_REG(TRCIDR5); */ 7430 /** @todo FEAT_ETE: READ_SYS_REG(TRCIDR6); */ 7431 /** @todo FEAT_ETE: READ_SYS_REG(TRCIDR7); */ 7432 /** @todo FEAT_ETE: READ_SYS_REG(TRCIDR8); */ 7433 /** @todo FEAT_ETE: READ_SYS_REG(TRCIDR9); */ 7434 7435 7436 # undef READ_SYS_REG 7437 # undef COMPILER_READ_SYS_REG 7438 7439 /* 7440 * Complete the request output. 7441 */ 7442 pReq->u.Out.cRegsAvailable = idxReg; 7443 if (idxReg > cMaxRegs) 7444 idxReg = cMaxRegs; 7445 pReq->u.Out.cRegs = idxReg; 7446 pReq->Hdr.cbOut = SUP_IOCTL_ARM_GET_SYSREGS_SIZE_OUT(idxReg); 7447 return VINF_SUCCESS; 7448 } 7449 #endif /* RT_ARCH_ARM64 */ 7223 7450 7224 7451 -
trunk/src/VBox/HostDrivers/Support/SUPDrvIOC.h
r107091 r109014 1433 1433 1434 1434 1435 #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) || defined(DOXYGEN_RUNNING) 1435 1436 /** @name SUP_IOCTL_MSR_PROBER 1436 1437 * MSR probing interface, not available in normal builds. 1437 1438 * 1438 * @{ 1439 */ 1440 #define SUP_IOCTL_MSR_PROBER SUP_CTL_CODE_SIZE(34, SUP_IOCTL_MSR_PROBER_SIZE) 1441 #define SUP_IOCTL_MSR_PROBER_SIZE sizeof(SUPMSRPROBER) 1442 #define SUP_IOCTL_MSR_PROBER_SIZE_IN sizeof(SUPMSRPROBER) 1443 #define SUP_IOCTL_MSR_PROBER_SIZE_OUT sizeof(SUPMSRPROBER) 1439 * @note X86 specific. 1440 * 1441 * @{ 1442 */ 1443 # define SUP_IOCTL_MSR_PROBER SUP_CTL_CODE_SIZE(34, SUP_IOCTL_MSR_PROBER_SIZE) 1444 # define SUP_IOCTL_MSR_PROBER_SIZE sizeof(SUPMSRPROBER) 1445 # define SUP_IOCTL_MSR_PROBER_SIZE_IN sizeof(SUPMSRPROBER) 1446 # define SUP_IOCTL_MSR_PROBER_SIZE_OUT sizeof(SUPMSRPROBER) 1444 1447 1445 1448 typedef enum SUPMSRPROBEROP … … 1537 1540 AssertCompileMembersSameSizeAndOffset(SUPMSRPROBER, u.In, SUPMSRPROBER, u.Out); 1538 1541 /** @} */ 1542 #endif /* defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) || defined(DOXYGEN_RUNNING) */ 1543 1544 #if defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING) 1545 /** @name SUP_IOCTL_ARM_GET_SYSREGS 1546 * Interface for getting ID register and in special builds some additional 1547 * system register values. 1548 * 1549 * @note ARM specific. 1550 * 1551 * @{ 1552 */ 1553 # define SUP_IOCTL_ARM_GET_SYSREGS SUP_CTL_CODE_BIG(34) 1554 # define SUP_IOCTL_ARM_GET_SYSREGS_SIZE(cRegs) ((uint32_t)RT_UOFFSETOF_FLEX_ARRAY(SUPARMGETSYSREGS, u.Out.aRegs, (cRegs))) 1555 # define SUP_IOCTL_ARM_GET_SYSREGS_SIZE_IN (RT_UOFFSETOF(SUPARMGETSYSREGS, u.In) + RT_SIZEOFMEMB(SUPARMGETSYSREGS, u.In)) 1556 # define SUP_IOCTL_ARM_GET_SYSREGS_SIZE_OUT(cRegs) SUP_IOCTL_ARM_GET_SYSREGS_SIZE(cRegs) 1557 1558 typedef struct SUPARMGETSYSREGS 1559 { 1560 /** The header. */ 1561 SUPREQHDR Hdr; 1562 1563 /** Input/output union. */ 1564 union 1565 { 1566 /** Inputs. */ 1567 struct 1568 { 1569 /** SUP_ARM_SYS_REG_F_XXX */ 1570 uint32_t fFlags; 1571 } In; 1572 1573 /** Outputs. */ 1574 struct 1575 { 1576 /** Number of registers returned. */ 1577 uint32_t cRegs; 1578 /** Number of registers available. 1579 * If larger than cRegs, then retry with larger structure. */ 1580 uint32_t cRegsAvailable; 1581 1582 /** Array of registers and their values. */ 1583 SUPARMSYSREGVAL aRegs[1]; 1584 } Out; 1585 } u; 1586 } SUPARMGETSYSREGS, *PSUPARMGETSYSREGS; 1587 AssertCompileMemberAlignment(SUPARMGETSYSREGS, u, 8); 1588 AssertCompileMemberAlignment(SUPARMGETSYSREGS, u.Out.aRegs, 8); 1589 /** @} */ 1590 #endif /* defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING) */ 1591 1539 1592 1540 1593 /** @name SUP_IOCTL_RESUME_SUSPENDED_KBDS -
trunk/src/VBox/HostDrivers/Support/SUPLib.cpp
r108724 r109014 2242 2242 } 2243 2243 2244 #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) 2244 2245 2245 2246 SUPR3DECL(int) SUPR3MsrProberRead(uint32_t uMsr, RTCPUID idCpu, uint64_t *puValue, bool *pfGp) … … 2330 2331 } 2331 2332 2333 #endif /* RT_ARCH_AMD64 || RT_ARCH_X86 */ 2334 2335 #ifdef RT_ARCH_ARM64 2336 SUPR3DECL(int) SUPR3ArmQuerySysRegs(uint32_t fFlags, uint32_t cMaxRegs, 2337 uint32_t *pcRegsReturned, uint32_t *pcRegsAvailable, PSUPARMSYSREGVAL paSysRegValues) 2338 { 2339 /* 2340 * Validate input. 2341 */ 2342 AssertPtr(pcRegsReturned); 2343 *pcRegsReturned = 0; 2344 if (pcRegsAvailable) 2345 *pcRegsAvailable = 0; 2346 AssertReturn(cMaxRegs < _64K, VERR_OUT_OF_RANGE); 2347 AssertReturn(!(fFlags & SUP_ARM_SYS_REG_F_VALID_MASK), VERR_INVALID_FLAGS); 2348 2349 /* 2350 * Allocate temporary request. 2351 */ 2352 uint32_t cbReq = SUP_IOCTL_ARM_GET_SYSREGS_SIZE(cMaxRegs); 2353 PSUPARMGETSYSREGS pReq = (PSUPARMGETSYSREGS)RTMemTmpAllocZ(cbReq); 2354 AssertReturn(pReq, VERR_NO_TMP_MEMORY); 2355 2356 pReq->Hdr.u32Cookie = g_u32Cookie; 2357 pReq->Hdr.u32SessionCookie = g_u32SessionCookie; 2358 pReq->Hdr.cbIn = SUP_IOCTL_ARM_GET_SYSREGS_SIZE_IN; 2359 pReq->Hdr.cbOut = SUP_IOCTL_ARM_GET_SYSREGS_SIZE_OUT(cMaxRegs); 2360 pReq->Hdr.fFlags = SUPREQHDR_FLAGS_DEFAULT; 2361 pReq->Hdr.rc = VERR_INTERNAL_ERROR; 2362 2363 pReq->u.In.fFlags = fFlags; 2364 2365 int rc = suplibOsIOCtl(&g_supLibData, SUP_IOCTL_ARM_GET_SYSREGS, pReq, cbReq); 2366 if (RT_SUCCESS(rc)) 2367 rc = pReq->Hdr.rc; 2368 if (RT_SUCCESS(rc)) 2369 { 2370 uint32_t const cRetRegs = RT_MIN(cMaxRegs, pReq->u.Out.cRegs); /* paranoia */ 2371 AssertCompile(sizeof(paSysRegValues[0]) == sizeof(pReq->u.Out.aRegs[0])); 2372 memcpy(paSysRegValues, pReq->u.Out.aRegs, sizeof(pReq->u.Out.aRegs[0]) * cRetRegs); 2373 *pcRegsReturned = cRetRegs; 2374 if (pcRegsAvailable) 2375 *pcRegsAvailable = pReq->u.Out.cRegsAvailable; 2376 } 2377 2378 RTMemTmpFree(pReq); 2379 return rc; 2380 } 2381 #endif /* RT_ARCH_ARM64 */ 2332 2382 2333 2383 SUPR3DECL(int) SUPR3ResumeSuspendedKeyboards(void)
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