Changeset 109029 in vbox for trunk/include

Timestamp:

Apr 20, 2025 2:48:56 AM (2 weeks ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

168558

Message:

SUP,VBoxCpuReport,VMM/CPUM: Deal with core variations on arm CPUs when generating reports for them. jiraref:VBP-1598

Location:

trunk/include/VBox

Files:

• sup.h (modified) (2 diffs)
• vmm/cpum.h (modified) (3 diffs)

trunk/include/VBox/sup.h

@@ -2038 +2038 @@
  *
  * @returns VBox status code.
+ * @param   idCpu               The CPU to query the registers on, NIL_RTCPUID
+ *                              if any will do.
  * @param   fFlags              Query flags, SUP_ARM_SYS_REG_F_XXX.
  * @param   cMaxRegs            Maximum number of registers @a paSysRegValues
@@ -2048 +2050 @@
  *                              associated info.
  */
-SUPR3DECL(int) SUPR3ArmQuerySysRegs(uint32_t fFlags, uint32_t cMaxRegs,
+SUPR3DECL(int) SUPR3ArmQuerySysRegs(RTCPUID idCpu, uint32_t fFlags, uint32_t cMaxRegs,
                                     uint32_t *pcRegsReturned, uint32_t *pcRegsAvailable, PSUPARMSYSREGVAL paSysRegValues);
 #endif /* defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING) */

trunk/include/VBox/vmm/cpum.h

@@ -295 +295 @@
     kCpumMicroarch_Apple_M1 = kCpumMicroarch_Apple_First,
     kCpumMicroarch_Apple_M2,
+    kCpumMicroarch_Apple_M3,
+    kCpumMicroarch_Apple_M4,
     kCpumMicroarch_Apple_End,
+
+    kCpumMicroarch_Qualcomm_First,
+    kCpumMicroarch_Qualcomm_Kyro = kCpumMicroarch_Qualcomm_First,
+    kCpumMicroarch_Qualcomm_Oryon,
+    kCpumMicroarch_Qualcomm_End,
 
     /*
@@ -1701 +1708 @@
 
 
+/** CPU core type. */
+typedef enum CPUMCORETYPE
+{
+    kCpumCoreType_Invalid = 0,
+    kCpumCoreType_Unknown,
+    kCpumCoreType_Performance,
+    kCpumCoreType_Efficiency,
+    kCpumCoreType_End,
+    kCpumCoreType_32BitHack = 0x7fffffff,
+} CPUMCORETYPE;
+
+
 /**
  * CPU database entry for x86.
@@ -1748 +1767 @@
 {
     /** The common parts. */
-    CPUMDBENTRY         Core;
-
-    /** The implementer value from MIDR_EL1. */
-    uint8_t             bImplementer;
-    /** The revision number from MIDR_EL1. */
-    uint8_t             bRevision;
-    /** The part number value from MIDR_EL1. */
-    uint16_t            uPartNum;
-
-    /** Number of entries in the table paSysRegVals points to. */
-    uint32_t            cSysRegVals;
-    /** System register values. */
-    struct SUPARMSYSREGVAL const *paSysRegVals;
+    CPUMDBENTRY                     Core;
+
+    /** System register values common to all the core variations. */
+    struct SUPARMSYSREGVAL const   *paSysRegCmnVals;
+    /** Number of entries in the table paSysRegCmnVals points to. */
+    uint32_t                        cSysRegCmnVals;
+    /** Number of core variants in aVariants below. */
+    uint32_t                        cVariants;
+
+    /** CPU core variation details. */
+    struct
+    {
+        /** The name of this CPU core variation. */
+        const char                     *pszName;
+        /** MIDR_EL1 for this CPU core variation. */
+        union
+        {
+            struct
+            {
+                /** CPU revision. */
+                uint32_t                u4Revision    :  4;
+                /** Part number. */
+                uint32_t                u12PartNum    : 12;
+                /** ARM architecture indicator. */
+                uint32_t                u4Arch        :  4;
+                /** Implementer specific variant. */
+                uint32_t                u4Variant     :  4;
+                /** The implementer. */
+                uint32_t                u8Implementer :  8;
+            } s;
+            uint64_t                    u64;
+        } Midr;
+        /** The CPU core type. */
+        CPUMCORETYPE                    enmCoreType;
+        /** Number of entries in the table paSysRegVals points to. */
+        uint32_t                        cSysRegVals;
+        /** System register values specific to this CPU core variant. */
+        struct SUPARMSYSREGVAL const   *paSysRegVals;
+    } aVariants[2];
 } CPUMDBENTRYARM;
 /** Pointer to a const ARM CPU database entry. */