Changeset 11199 in vbox for trunk/src/VBox
- Timestamp:
- Aug 6, 2008 11:02:45 PM (17 years ago)
- svn:sync-xref-src-repo-rev:
- 34235
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Network/DevPCNet.cpp
r11163 r11199 1 1 /* $Id$ */ 2 2 /** @file 3 * AMD PCnet-PCI II / PCnet-FAST III (Am79C970A / Am79C973) Ethernet Controller Emulation. 3 * DevPCNet - AMD PCnet-PCI II / PCnet-FAST III (Am79C970A / Am79C973) Ethernet Controller Emulation. 4 * 5 * This software was written to be compatible with the specifications: 6 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet 7 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 8 * and 9 * todo 4 10 */ 5 11 … … 43 49 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 44 50 * THE SOFTWARE. 45 */46 47 /* This software was written to be compatible with the specification:48 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet49 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 200050 51 */ 51 52 … … 68 69 #endif 69 70 70 #include " Builtins.h"71 #include "../Builtins.h" 71 72 72 73 /* Enable this to catch writes to the ring descriptors instead of using excessive polling */ … … 111 112 PCIDEVICE PciDev; 112 113 #ifndef PCNET_NO_POLLING 113 /** Poll timer (address for host context) */ 114 R3R0PTRTYPE(PTMTIMER) pTimerPollHC; 115 /** Poll timer (address for guest context) */ 116 RCPTRTYPE(PTMTIMER) pTimerPollGC; 114 /** Poll timer - R3. */ 115 PTMTIMERR3 pTimerPollR3; 116 /** Poll timer - R0. */ 117 PTMTIMERR0 pTimerPollR0; 118 /** Poll timer - RC. */ 119 PTMTIMERRC pTimerPollRC; 117 120 #endif 118 121 … … 121 124 #endif 122 125 123 /** Software Interrupt timer (address for host context) */ 124 R3R0PTRTYPE(PTMTIMER) pTimerSoftIntHC; 125 /** Software Interrupt timer (address for guest context) */ 126 RCPTRTYPE(PTMTIMER) pTimerSoftIntGC; 126 /** Software Interrupt timer - R3. */ 127 PTMTIMERR3 pTimerSoftIntR3; 128 /** Software Interrupt timer - R0. */ 129 PTMTIMERR0 pTimerSoftIntR0; 130 /** Software Interrupt timer - RC. */ 131 PTMTIMERRC pTimerSoftIntRC; 127 132 128 133 /** Register Address Pointer */ … … 165 170 RTGCPHYS32 GCUpperPhys; 166 171 167 /** Transmit signaller */ 168 RCPTRTYPE(PPDMQUEUE) pXmitQueueGC; 169 R3R0PTRTYPE(PPDMQUEUE) pXmitQueueHC; 170 171 /** Receive signaller */ 172 R3R0PTRTYPE(PPDMQUEUE) pCanRxQueueHC; 173 RCPTRTYPE(PPDMQUEUE) pCanRxQueueGC; 174 /** Pointer to the device instance. */ 175 RCPTRTYPE(PPDMDEVINS) pDevInsGC; 176 /** Pointer to the device instance. */ 177 R3R0PTRTYPE(PPDMDEVINS) pDevInsHC; 172 /** Transmit signaller - RC. */ 173 RCPTRTYPE(PPDMQUEUE) pXmitQueueRC; 174 /** Transmit signaller - R3. */ 175 R3PTRTYPE(PPDMQUEUE) pXmitQueueR3; 176 /** Transmit signaller - R0. */ 177 R0PTRTYPE(PPDMQUEUE) pXmitQueueR0; 178 179 /** Receive signaller - R3. */ 180 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; 181 /** Receive signaller - R0. */ 182 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; 183 /** Receive signaller - RC. */ 184 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; 185 /** Pointer to the device instance - RC. */ 186 PPDMDEVINSRC pDevInsRC; 187 /** Pointer to the device instance - R3. */ 188 PPDMDEVINSR3 pDevInsR3; 189 /** Pointer to the device instance - R0. */ 190 PPDMDEVINSR0 pDevInsR0; 178 191 /** Restore timer. 179 192 * This is used to disconnect and reconnect the link after a restore. */ … … 234 247 uint32_t cbRDRAOld; 235 248 236 DECL GCCALLBACKMEMBER(int, pfnEMInterpretInstructionGC, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize));249 DECLRCCALLBACKMEMBER(int, pfnEMInterpretInstructionRC, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)); 237 250 DECLR0CALLBACKMEMBER(int, pfnEMInterpretInstructionR0, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)); 238 251 #endif 239 252 240 /** The host context of the shared memory used for the private interface. */ 241 R3R0PTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIOHC; 242 /** The hypervisor/guest context of the shared memory used for the private interface. */ 243 RCPTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIOGC; 253 /** The shared memory used for the private interface - R3. */ 254 R3PTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIOR3; 255 /** The shared memory used for the private interface - R0. */ 256 R0PTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIOR0; 257 /** The shared memory used for the private interface - RC. */ 258 RCPTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIORC; 244 259 245 260 #if HC_ARCH_BITS == 64 … … 255 270 256 271 #ifdef PCNET_QUEUE_SEND_PACKETS 257 #define PCNET_MAX_XMIT_SLOTS128258 #define PCNET_MAX_XMIT_SLOTS_MASK (PCNET_MAX_XMIT_SLOTS-1)272 # define PCNET_MAX_XMIT_SLOTS 128 273 # define PCNET_MAX_XMIT_SLOTS_MASK (PCNET_MAX_XMIT_SLOTS - 1) 259 274 260 275 uint32_t iXmitRingBufProd; 261 276 uint32_t iXmitRingBufCons; 262 /* XXX currently atomic operations on this variable are overkill */277 /** @todo XXX currently atomic operations on this variable are overkill */ 263 278 volatile int32_t cXmitRingBufPending; 264 279 uint16_t cbXmitRingBuffer[PCNET_MAX_XMIT_SLOTS]; … … 315 330 }; 316 331 317 #define PCNETSTATE_2_DEVINS(pPCNet) ((pPCNet)->CTX SUFF(pDevIns))332 #define PCNETSTATE_2_DEVINS(pPCNet) ((pPCNet)->CTX_SUFF(pDevIns)) 318 333 #define PCIDEV_2_PCNETSTATE(pPciDev) ((PCNetState *)(pPciDev)) 319 334 #define PCNET_INST_NR (PCNETSTATE_2_DEVINS(pData)->iInstance) … … 619 634 { 620 635 /* RX/TX descriptors shared between host and guest => direct copy */ 621 uint8_t *pv = (uint8_t*)pData->CTX SUFF(pSharedMMIO)636 uint8_t *pv = (uint8_t*)pData->CTX_SUFF(pSharedMMIO) 622 637 + (addr - pData->GCTDRA) 623 + pData->CTX SUFF(pSharedMMIO)->V.V1.offTxDescriptors;638 + pData->CTX_SUFF(pSharedMMIO)->V.V1.offTxDescriptors; 624 639 if (!(pv[7] & 0x80) && fRetIfNotOwn) 625 640 return false; … … 681 696 { 682 697 /* RX/TX descriptors shared between host and guest => direct copy */ 683 uint8_t *pv = (uint8_t*)pData->CTX SUFF(pSharedMMIO)698 uint8_t *pv = (uint8_t*)pData->CTX_SUFF(pSharedMMIO) 684 699 + (addr - pData->GCTDRA) 685 + pData->CTX SUFF(pSharedMMIO)->V.V1.offTxDescriptors;700 + pData->CTX_SUFF(pSharedMMIO)->V.V1.offTxDescriptors; 686 701 memcpy(pv, tmd, 16); 687 702 pv[7] &= ~0x80; … … 738 753 { 739 754 /* RX/TX descriptors shared between host and guest => direct copy */ 740 uint8_t *pb = (uint8_t*)pData->CTX SUFF(pSharedMMIO)755 uint8_t *pb = (uint8_t*)pData->CTX_SUFF(pSharedMMIO) 741 756 + (addr - pData->GCRDRA) 742 + pData->CTX SUFF(pSharedMMIO)->V.V1.offRxDescriptors;757 + pData->CTX_SUFF(pSharedMMIO)->V.V1.offRxDescriptors; 743 758 if (!(pb[7] & 0x80) && fRetIfNotOwn) 744 759 return false; … … 798 813 { 799 814 /* RX/TX descriptors shared between host and guest => direct copy */ 800 uint8_t *pv = (uint8_t*)pData->CTX SUFF(pSharedMMIO)815 uint8_t *pv = (uint8_t*)pData->CTX_SUFF(pSharedMMIO) 801 816 + (addr - pData->GCRDRA) 802 + pData->CTX SUFF(pSharedMMIO)->V.V1.offRxDescriptors;817 + pData->CTX_SUFF(pSharedMMIO)->V.V1.offRxDescriptors; 803 818 memcpy(pv, rmd, 16); 804 819 pv[7] &= ~0x80; … … 853 868 #define ETH_ALEN 6 854 869 #pragma pack(1) 855 struct ether_header 870 struct ether_header /** @todo Use RTNETETHERHDR */ 856 871 { 857 872 uint8_t ether_dhost[ETH_ALEN]; /**< destination ethernet address */ … … 885 900 { 886 901 /* Clear the entire block for pcnetReset usage. */ 887 memset(pData->pSharedMMIO HC, 0, PCNET_GUEST_SHARED_MEMORY_SIZE);888 889 pData->pSharedMMIO HC->u32Version = PCNET_GUEST_INTERFACE_VERSION;902 memset(pData->pSharedMMIOR3, 0, PCNET_GUEST_SHARED_MEMORY_SIZE); 903 904 pData->pSharedMMIOR3->u32Version = PCNET_GUEST_INTERFACE_VERSION; 890 905 uint32_t off = 2048; /* Leave some space for more fields within the header */ 891 906 … … 893 908 * The Descriptor arrays. 894 909 */ 895 pData->pSharedMMIO HC->V.V1.offTxDescriptors = off;910 pData->pSharedMMIOR3->V.V1.offTxDescriptors = off; 896 911 off = RT_ALIGN(off + PCNET_GUEST_TX_DESCRIPTOR_SIZE * PCNET_GUEST_MAX_TX_DESCRIPTORS, 32); 897 912 898 pData->pSharedMMIO HC->V.V1.offRxDescriptors = off;913 pData->pSharedMMIOR3->V.V1.offRxDescriptors = off; 899 914 off = RT_ALIGN(off + PCNET_GUEST_RX_DESCRIPTOR_SIZE * PCNET_GUEST_MAX_RX_DESCRIPTORS, 32); 900 915 … … 908 923 #if 0 909 924 /* Don't allocate TX buffers since Windows guests cannot use it */ 910 pData->pSharedMMIO HC->V.V1.offTxBuffers = off;925 pData->pSharedMMIOR3->V.V1.offTxBuffers = off; 911 926 off = RT_ALIGN(off + PCNET_GUEST_NIC_BUFFER_SIZE * PCNET_GUEST_MAX_TX_DESCRIPTORS, 32); 912 927 #endif 913 928 914 pData->pSharedMMIO HC->V.V1.offRxBuffers = off;915 pData->pSharedMMIO HC->fFlags = PCNET_GUEST_FLAGS_ADMIT_HOST;929 pData->pSharedMMIOR3->V.V1.offRxBuffers = off; 930 pData->pSharedMMIOR3->fFlags = PCNET_GUEST_FLAGS_ADMIT_HOST; 916 931 off = RT_ALIGN(off + PCNET_GUEST_NIC_BUFFER_SIZE * PCNET_GUEST_MAX_RX_DESCRIPTORS, 32); 917 932 AssertRelease(off <= PCNET_GUEST_SHARED_MEMORY_SIZE); 918 933 919 934 /* Update the header with the final size. */ 920 pData->pSharedMMIO HC->cbUsed = off;935 pData->pSharedMMIOR3->cbUsed = off; 921 936 } 922 937 … … 1380 1395 static void pcnetEnablePrivateIf(PCNetState *pData) 1381 1396 { 1382 bool fPrivIfEnabled = pData->pSharedMMIO HC1383 && !!(pData->CTX SUFF(pSharedMMIO)->fFlags & PCNET_GUEST_FLAGS_ADMIT_GUEST);1397 bool fPrivIfEnabled = pData->pSharedMMIOR3 1398 && !!(pData->CTX_SUFF(pSharedMMIO)->fFlags & PCNET_GUEST_FLAGS_ADMIT_GUEST); 1384 1399 if (fPrivIfEnabled != pData->fPrivIfEnabled) 1385 1400 { … … 1662 1677 pcnetWakeupReceive(PCNETSTATE_2_DEVINS(pData)); 1663 1678 #else 1664 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc( CTXSUFF(pData->pCanRxQueue));1679 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pData->CTX_SUFF(pCanRxQueue)); 1665 1680 if (pItem) 1666 PDMQueueInsert( CTXSUFF(pData->pCanRxQueue), pItem);1681 PDMQueueInsert(pData->CTX_SUFF(pCanRxQueue), pItem); 1667 1682 #endif 1668 1683 } … … 1857 1872 if (pData->fPrivIfEnabled) 1858 1873 { 1859 uint8_t *pb = (uint8_t*)pData->CTX SUFF(pSharedMMIO)1860 + rbadr - pData->GCRDRA + pData->CTX SUFF(pSharedMMIO)->V.V1.offRxDescriptors;1874 uint8_t *pb = (uint8_t*)pData->CTX_SUFF(pSharedMMIO) 1875 + rbadr - pData->GCRDRA + pData->CTX_SUFF(pSharedMMIO)->V.V1.offRxDescriptors; 1861 1876 memcpy(pb, src, count); 1862 1877 } … … 1896 1911 if (pData->fPrivIfEnabled) 1897 1912 { 1898 uint8_t *pb = (uint8_t*)pData->CTX SUFF(pSharedMMIO)1899 + rbadr - pData->GCRDRA + pData->CTX SUFF(pSharedMMIO)->V.V1.offRxDescriptors;1913 uint8_t *pb = (uint8_t*)pData->CTX_SUFF(pSharedMMIO) 1914 + rbadr - pData->GCRDRA + pData->CTX_SUFF(pSharedMMIO)->V.V1.offRxDescriptors; 1900 1915 memcpy(pb, src, count); 1901 1916 } … … 2021 2036 pData->pvSendFrame = pData->abSendBuf; 2022 2037 #endif 2023 PDMDevHlpPhysRead(pData->CTX SUFF(pDevIns), GCPhysFrame, pData->pvSendFrame, cbFrame);2038 PDMDevHlpPhysRead(pData->CTX_SUFF(pDevIns), GCPhysFrame, pData->pvSendFrame, cbFrame); 2024 2039 pData->cbSendFrame = cbFrame; 2025 2040 } … … 2032 2047 { 2033 2048 Assert(pData->cbSendFrame + cbFrame <= MAX_FRAME); 2034 PDMDevHlpPhysRead(pData->CTX SUFF(pDevIns), GCPhysFrame, pData->pvSendFrame + pData->cbSendFrame, cbFrame);2049 PDMDevHlpPhysRead(pData->CTX_SUFF(pDevIns), GCPhysFrame, pData->pvSendFrame + pData->cbSendFrame, cbFrame); 2035 2050 pData->cbSendFrame += cbFrame; 2036 2051 } … … 2123 2138 DECLINLINE(void) pcnetXmitFlushFrames(PCNetState *pData) 2124 2139 { 2125 pcnetXmitQueueConsumer( CTXSUFF(pData->pDevIns), NULL);2140 pcnetXmitQueueConsumer(pData->CTX_SUFF(pDevIns), NULL); 2126 2141 } 2127 2142 … … 2160 2175 #else 2161 2176 # if 1 2162 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc( CTXSUFF(pData->pXmitQueue));2177 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pData->CTX_SUFF(pXmitQueue)); 2163 2178 if (RT_UNLIKELY(pItem)) 2164 PDMQueueInsert( CTXSUFF(pData->pXmitQueue), pItem);2179 PDMQueueInsert(pData->CTX_SUFF(pXmitQueue), pItem); 2165 2180 # else 2166 2181 if (ASMAtomicIncU32(&pData->cPendingSends) < 16) 2167 2182 { 2168 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc( CTXSUFF(pData->pXmitQueue));2183 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pData->CTX_SUFF(pXmitQueue)); 2169 2184 if (RT_UNLIKELY(pItem)) 2170 PDMQueueInsert( CTXSUFF(pData->pXmitQueue), pItem);2185 PDMQueueInsert(pData->CTX_SUFF(pXmitQueue), pItem); 2171 2186 } 2172 2187 else 2173 PDMQueueFlush( CTXSUFF(pData->pXmitQueue));2188 PDMQueueFlush(pData->CTX_SUFF(pXmitQueue)); 2174 2189 # endif 2175 2190 #endif … … 2540 2555 static void pcnetPollTimerStart(PCNetState *pData) 2541 2556 { 2542 TMTimerSetMillies(pData->CTX SUFF(pTimerPoll), 2);2557 TMTimerSetMillies(pData->CTX_SUFF(pTimerPoll), 2); 2543 2558 } 2544 2559 … … 2595 2610 pcnetPollRxTx(pData); 2596 2611 #else 2597 uint64_t u64Now = TMTimerGet(pData->CTX SUFF(pTimerPoll));2612 uint64_t u64Now = TMTimerGet(pData->CTX_SUFF(pTimerPoll)); 2598 2613 if (RT_UNLIKELY(u64Now - pData->u64LastPoll > 200000)) 2599 2614 { … … 2601 2616 pcnetPollRxTx(pData); 2602 2617 } 2603 if (!TMTimerIsActive(pData->CTX SUFF(pTimerPoll)))2618 if (!TMTimerIsActive(pData->CTX_SUFF(pTimerPoll))) 2604 2619 pcnetPollTimerStart(pData); 2605 2620 #endif … … 2910 2925 pData->aBCR[BCR_STVAL] = val; 2911 2926 if (pData->fAm79C973) 2912 TMTimerSetNano(pData->CTX SUFF(pTimerSoftInt), 12800U * val);2927 TMTimerSetNano(pData->CTX_SUFF(pTimerSoftInt), 12800U * val); 2913 2928 break; 2914 2929 … … 3703 3718 pData->aCSR[7] |= 0x0800; /* STINT */ 3704 3719 pcnetUpdateIrq(pData); 3705 TMTimerSetNano(pData->CTX SUFF(pTimerSoftInt), 12800U * (pData->aBCR[BCR_STVAL] & 0xffff));3720 TMTimerSetNano(pData->CTX_SUFF(pTimerSoftInt), 12800U * (pData->aBCR[BCR_STVAL] & 0xffff)); 3706 3721 } 3707 3722 … … 4139 4154 return VINF_SUCCESS; 4140 4155 #else 4141 rc = TMR3TimerSave(pData->CTX SUFF(pTimerPoll), pSSMHandle);4156 rc = TMR3TimerSave(pData->CTX_SUFF(pTimerPoll), pSSMHandle); 4142 4157 if (VBOX_FAILURE(rc)) 4143 4158 return rc; 4144 4159 #endif 4145 4160 if (pData->fAm79C973) 4146 rc = TMR3TimerSave(pData->CTX SUFF(pTimerSoftInt), pSSMHandle);4161 rc = TMR3TimerSave(pData->CTX_SUFF(pTimerSoftInt), pSSMHandle); 4147 4162 return rc; 4148 4163 } … … 4215 4230 SSMR3GetU32(pSSMHandle, &pData->u32LinkSpeed); 4216 4231 #ifndef PCNET_NO_POLLING 4217 TMR3TimerLoad(pData->CTX SUFF(pTimerPoll), pSSMHandle);4232 TMR3TimerLoad(pData->CTX_SUFF(pTimerPoll), pSSMHandle); 4218 4233 #endif 4219 4234 if (pData->fAm79C973) … … 4221 4236 if ( SSM_VERSION_MAJOR(u32Version) > 0 4222 4237 || SSM_VERSION_MINOR(u32Version) >= 8) 4223 TMR3TimerLoad(pData->CTX SUFF(pTimerSoftInt), pSSMHandle);4238 TMR3TimerLoad(pData->CTX_SUFF(pTimerSoftInt), pSSMHandle); 4224 4239 } 4225 4240 … … 4334 4349 ASMAtomicXchgBool(&pData->fMaybeOutOfSpace, true); 4335 4350 STAM_PROFILE_START(&pData->StatRxOverflow, a); 4336 while (RT_LIKELY(PDMDevHlpVMState(pData->CTX SUFF(pDevIns)) == VMSTATE_RUNNING))4351 while (RT_LIKELY(PDMDevHlpVMState(pData->CTX_SUFF(pDevIns)) == VMSTATE_RUNNING)) 4337 4352 { 4338 4353 int rc2 = pcnetCanReceive(pData); … … 4524 4539 pcnetTimerRestore(pDevIns, pData->pTimerRestore); 4525 4540 } 4526 if (pData->pSharedMMIO HC)4541 if (pData->pSharedMMIOR3) 4527 4542 pcnetInitSharedMemory(pData); 4528 4543 … … 4538 4553 { 4539 4554 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *); 4540 pData->pDevIns GC = PDMDEVINS_2_GCPTR(pDevIns);4541 pData->pXmitQueue GC = PDMQueueGCPtr(pData->pXmitQueueHC);4542 pData->pCanRxQueue GC = PDMQueueGCPtr(pData->pCanRxQueueHC);4543 if (pData->pSharedMMIO HC)4544 pData->pSharedMMIO GC += offDelta;4555 pData->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 4556 pData->pXmitQueueRC = PDMQueueRCPtr(pData->pXmitQueueR3); 4557 pData->pCanRxQueueRC = PDMQueueRCPtr(pData->pCanRxQueueR3); 4558 if (pData->pSharedMMIOR3) 4559 pData->pSharedMMIORC += offDelta; 4545 4560 #ifdef PCNET_NO_POLLING 4546 *(RTHCUINTPTR *)&pData->pfnEMInterpretInstructionGC += offDelta;4561 pData->pfnEMInterpretInstructionRC += offDelta; 4547 4562 #else 4548 pData->pTimerPoll GC = TMTimerGCPtr(pData->pTimerPollHC);4563 pData->pTimerPollRC = TMTimerRCPtr(pData->pTimerPollR3); 4549 4564 #endif 4550 4565 if (pData->fAm79C973) 4551 pData->pTimerSoftInt GC = TMTimerGCPtr(pData->pTimerSoftIntHC);4566 pData->pTimerSoftIntRC = TMTimerRCPtr(pData->pTimerSoftIntR3); 4552 4567 } 4553 4568 … … 4616 4631 4617 4632 /* 4633 * Init what's required to make the destructor safe. 4634 */ 4635 pData->hEventOutOfRxSpace = NIL_RTSEMEVENT; 4636 pData->hSendEventSem = NIL_RTSEMEVENT; 4637 4638 /* 4618 4639 * Validate configuration. 4619 4640 */ 4620 if (!CFGMR3AreValuesValid(pCfgHandle, "MAC\0 CableConnected\0Am79C973\0LineSpeed\0GCEnabled\0R0Enabled\0PrivIfEnabled\0"))4641 if (!CFGMR3AreValuesValid(pCfgHandle, "MAC\0" "CableConnected\0" "Am79C973\0" "LineSpeed\0" "GCEnabled\0" "R0Enabled\0" "PrivIfEnabled\0")) 4621 4642 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, 4622 4643 N_("Invalid configuraton for pcnet device")); … … 4629 4650 return PDMDEV_SET_ERROR(pDevIns, rc, 4630 4651 N_("Configuration error: Failed to get the \"MAC\" value")); 4631 rc = CFGMR3QueryBool(pCfgHandle, "CableConnected", &pData->fLinkUp); 4632 if (rc == VERR_CFGM_VALUE_NOT_FOUND) 4633 pData->fLinkUp = true; 4634 else if (VBOX_FAILURE(rc)) 4652 rc = CFGMR3QueryBoolDef(pCfgHandle, "CableConnected", &pData->fLinkUp, true); 4653 if (VBOX_FAILURE(rc)) 4635 4654 return PDMDEV_SET_ERROR(pDevIns, rc, 4636 4655 N_("Configuration error: Failed to get the \"CableConnected\" value")); 4637 4656 4638 rc = CFGMR3QueryBool(pCfgHandle, "Am79C973", &pData->fAm79C973); 4639 if (rc == VERR_CFGM_VALUE_NOT_FOUND) 4640 pData->fAm79C973 = false; 4641 else if (VBOX_FAILURE(rc)) 4657 rc = CFGMR3QueryBoolDef(pCfgHandle, "Am79C973", &pData->fAm79C973, false); 4658 if (VBOX_FAILURE(rc)) 4642 4659 return PDMDEV_SET_ERROR(pDevIns, rc, 4643 4660 N_("Configuration error: Failed to get the \"Am79C973\" value")); 4644 4661 4645 rc = CFGMR3QueryU32(pCfgHandle, "LineSpeed", &pData->u32LinkSpeed); 4646 if (rc == VERR_CFGM_VALUE_NOT_FOUND) 4647 pData->u32LinkSpeed = 1000000; /* 1GBit/s (in kbps units)*/ 4648 else if (VBOX_FAILURE(rc)) 4662 rc = CFGMR3QueryU32Def(pCfgHandle, "LineSpeed", &pData->u32LinkSpeed, 1000000); /* 1GBit/s (in kbps units)*/ 4663 if (VBOX_FAILURE(rc)) 4649 4664 return PDMDEV_SET_ERROR(pDevIns, rc, 4650 4665 N_("Configuration error: Failed to get the \"LineSpeed\" value")); 4651 4666 4652 4667 #ifdef PCNET_GC_ENABLED 4653 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &pData->fGCEnabled); 4654 if (rc == VERR_CFGM_VALUE_NOT_FOUND) 4655 pData->fGCEnabled = true; 4656 else if (VBOX_FAILURE(rc)) 4668 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &pData->fGCEnabled, true); 4669 if (VBOX_FAILURE(rc)) 4657 4670 return PDMDEV_SET_ERROR(pDevIns, rc, 4658 4671 N_("Configuration error: Failed to get the \"GCEnabled\" value")); 4659 4672 4660 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &pData->fR0Enabled); 4661 if (rc == VERR_CFGM_VALUE_NOT_FOUND) 4662 pData->fR0Enabled = true; 4663 else if (VBOX_FAILURE(rc)) 4673 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &pData->fR0Enabled, true); 4674 if (VBOX_FAILURE(rc)) 4664 4675 return PDMDEV_SET_ERROR(pDevIns, rc, 4665 4676 N_("Configuration error: Failed to get the \"R0Enabled\" value")); … … 4674 4685 * Initialize data (most of it anyway). 4675 4686 */ 4676 pData->pDevInsHC = pDevIns; 4677 pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns); 4687 pData->pDevInsR3 = pDevIns; 4688 pData->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 4689 pData->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 4678 4690 pData->Led.u32Magic = PDMLED_MAGIC; 4679 4691 /* IBase */ … … 4745 4757 if (fPrivIfEnabled) 4746 4758 { 4747 RTRCPTR pRCMapping;4748 4749 4759 /* 4750 4760 * Initialize shared memory between host and guest for descriptors and RX buffers. Most guests 4751 4761 * should not care if there is an additional PCI ressource but just in case we made this configurable. 4752 4762 */ 4753 rc = PDMDevHlpMMIO2Register(pDevIns, 2, PCNET_GUEST_SHARED_MEMORY_SIZE, 0, (void **)&pData->pSharedMMIO HC, "PCNetShMem");4763 rc = PDMDevHlpMMIO2Register(pDevIns, 2, PCNET_GUEST_SHARED_MEMORY_SIZE, 0, (void **)&pData->pSharedMMIOR3, "PCNetShMem"); 4754 4764 if (VBOX_FAILURE(rc)) 4755 4765 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, 4756 4766 N_("Failed to allocate %u bytes of memory for the PCNet device"), PCNET_GUEST_SHARED_MEMORY_SIZE); 4757 rc = PDMDevHlpMMHyperMapMMIO2(pDevIns, 2, 0, 8192, "PCNetShMem", &p RCMapping);4767 rc = PDMDevHlpMMHyperMapMMIO2(pDevIns, 2, 0, 8192, "PCNetShMem", &pData->pSharedMMIORC); 4758 4768 if (VBOX_FAILURE(rc)) 4759 4769 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, 4760 4770 N_("Failed to map 8192 bytes of memory for the PCNet device into the hyper memory")); 4761 pData->pSharedMMIOGC = pRCMapping; 4771 pData->pSharedMMIOR0 = (uintptr_t)pData->pSharedMMIOR3; /** @todo #1865: Map MMIO2 into ring-0. */ 4772 4762 4773 pcnetInitSharedMemory(pData); 4763 4774 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, PCNET_GUEST_SHARED_MEMORY_SIZE, … … 4768 4779 4769 4780 #ifdef PCNET_NO_POLLING 4781 /* 4782 * Resolve the R0 and RC handlers. 4783 */ 4770 4784 rc = PDMR3GetSymbolR0Lazy(PDMDevHlpGetVM(pDevIns), NULL, "EMInterpretInstruction", &pData->pfnEMInterpretInstructionR0); 4771 4785 if (VBOX_SUCCESS(rc)) 4772 { 4773 /* 4774 * Resolve the GC handler. 4775 */ 4776 RTGCPTR pfnHandlerGC; 4777 rc = PDMR3GetSymbolGCLazy(PDMDevHlpGetVM(pDevIns), NULL, "EMInterpretInstruction", (RTGCPTR *)&pData->pfnEMInterpretInstructionGC); 4778 } 4779 if (VBOX_FAILURE(rc)) 4780 { 4781 AssertMsgFailed(("PDMR3GetSymbolGCLazy -> %Vrc\n", rc)); 4782 return rc; 4783 } 4786 rc = PDMR3GetSymbolGCLazy(PDMDevHlpGetVM(pDevIns), NULL, "EMInterpretInstruction", (RTGCPTR *)&pData->pfnEMInterpretInstructionRC); 4787 AssertLogRelMsgRCReturn(rc, ("PDMR3GetSymbolGCLazy(EMInterpretInstruction) -> %Vrc\n", rc), rc); 4784 4788 #else 4785 4789 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimer, 4786 "PCNet Poll Timer", &pData->pTimerPoll HC);4790 "PCNet Poll Timer", &pData->pTimerPollR3); 4787 4791 if (VBOX_FAILURE(rc)) 4788 {4789 AssertMsgFailed(("pfnTMTimerCreate pcnetTimer -> %Vrc\n", rc));4790 4792 return rc; 4791 } 4793 pData->pTimerPollR0 = TMTimerR0Ptr(pData->pTimerPollR3); 4794 pData->pTimerPollRC = TMTimerRCPtr(pData->pTimerPollR3); 4792 4795 #endif 4793 4796 if (pData->fAm79C973) … … 4795 4798 /* Software Interrupt timer */ 4796 4799 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimerSoftInt, 4797 "PCNet SoftInt Timer", &pData->pTimerSoftIntHC); 4798 if (VBOX_FAILURE(rc)) 4799 { 4800 AssertMsgFailed(("pfnTMTimerCreate pcnetTimerSoftInt -> %Vrc\n", rc)); 4800 "PCNet SoftInt Timer", &pData->pTimerSoftIntR3); 4801 if (RT_FAILURE(rc)) 4801 4802 return rc; 4802 } 4803 pData->pTimerSoftIntR0 = TMTimerR0Ptr(pData->pTimerSoftIntR3); 4804 pData->pTimerSoftIntRC = TMTimerRCPtr(pData->pTimerSoftIntR3); 4803 4805 } 4804 4806 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimerRestore, 4805 4807 "PCNet Restore Timer", &pData->pTimerRestore); 4806 if (VBOX_FAILURE(rc)) 4807 { 4808 AssertMsgFailed(("pfnTMTimerCreate pcnetTimerRestore -> %Vrc\n", rc)); 4808 if (RT_FAILURE(rc)) 4809 4809 return rc; 4810 } 4810 4811 4811 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4812 4812 PCNET_SAVEDSTATE_VERSION, sizeof(*pData), … … 4818 4818 /* 4819 4819 * Initialize critical section. 4820 * This must of course be done before attaching drivers or anything else which can call us back. .4820 * This must of course be done before attaching drivers or anything else which can call us back. 4821 4821 */ 4822 4822 char szName[24]; … … 4833 4833 */ 4834 4834 rc = PDMDevHlpPDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 4835 pcnetXmitQueueConsumer, true, &pData->pXmitQueue HC);4835 pcnetXmitQueueConsumer, true, &pData->pXmitQueueR3); 4836 4836 if (VBOX_FAILURE(rc)) 4837 4837 return rc; 4838 pData->pXmitQueueGC = PDMQueueGCPtr(pData->pXmitQueueHC); 4838 pData->pXmitQueueR0 = PDMQueueR0Ptr(pData->pXmitQueueR3); 4839 pData->pXmitQueueRC = PDMQueueRCPtr(pData->pXmitQueueR3); 4839 4840 4840 4841 /* … … 4842 4843 */ 4843 4844 rc = PDMDevHlpPDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0, 4844 pcnetCanRxQueueConsumer, true, &pData->pCanRxQueue HC);4845 pcnetCanRxQueueConsumer, true, &pData->pCanRxQueueR3); 4845 4846 if (VBOX_FAILURE(rc)) 4846 4847 return rc; 4847 pData->pCanRxQueueGC = PDMQueueGCPtr(pData->pCanRxQueueHC); 4848 pData->pCanRxQueueR0 = PDMQueueR0Ptr(pData->pCanRxQueueR3); 4849 pData->pCanRxQueueRC = PDMQueueRCPtr(pData->pCanRxQueueR3); 4848 4850 4849 4851 /* … … 4908 4910 AssertRCReturn(rc, rc); 4909 4911 4910 unsigned i;4911 NOREF(i);4912 4913 4912 #ifdef PCNET_QUEUE_SEND_PACKETS 4914 4913 pData->apXmitRingBuffer[0] = (uint8_t *)RTMemAlloc(PCNET_MAX_XMIT_SLOTS * MAX_FRAME); 4915 for ( i = 1; i < PCNET_MAX_XMIT_SLOTS; i++)4914 for (unsigned i = 1; i < PCNET_MAX_XMIT_SLOTS; i++) 4916 4915 pData->apXmitRingBuffer[i] = pData->apXmitRingBuffer[0] + i*MAX_FRAME; 4917 4916 #endif … … 4948 4947 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatTmdStoreHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet TmdStore in HC", "/Devices/PCNet%d/TmdStoreHC", iInstance); 4949 4948 4950 for (i = 0; i < ELEMENTS(pData->aStatXmitFlush) - 1; i++) 4949 unsigned i; 4950 for (i = 0; i < RT_ELEMENTS(pData->aStatXmitFlush) - 1; i++) 4951 4951 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitFlushIrq/%d", iInstance, i + 1); 4952 4952 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitFlushIrq/%d+", iInstance, i + 1); 4953 4953 4954 for (i = 0; i < ELEMENTS(pData->aStatXmitChainCounts) - 1; i++)4954 for (i = 0; i < RT_ELEMENTS(pData->aStatXmitChainCounts) - 1; i++) 4955 4955 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitChainCounts/%d", iInstance, i + 1); 4956 4956 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitChainCounts/%d+", iInstance, i + 1); -
trunk/src/VBox/Devices/testcase/tstDeviceStructSizeGC.cpp
r11197 r11199 321 321 GEN_CHECK_OFF(PCNetState, PciDev); 322 322 #ifndef PCNET_NO_POLLING 323 GEN_CHECK_OFF(PCNetState, pTimerPollHC); 324 GEN_CHECK_OFF(PCNetState, pTimerPollGC); 325 #endif 326 GEN_CHECK_OFF(PCNetState, pTimerSoftIntHC); 327 GEN_CHECK_OFF(PCNetState, pTimerSoftIntGC); 323 GEN_CHECK_OFF(PCNetState, pTimerPollR3); 324 GEN_CHECK_OFF(PCNetState, pTimerPollR0); 325 GEN_CHECK_OFF(PCNetState, pTimerPollRC); 326 #endif 327 GEN_CHECK_OFF(PCNetState, pTimerSoftIntR3); 328 GEN_CHECK_OFF(PCNetState, pTimerSoftIntR0); 329 GEN_CHECK_OFF(PCNetState, pTimerSoftIntRC); 328 330 GEN_CHECK_OFF(PCNetState, u32RAP); 329 331 GEN_CHECK_OFF(PCNetState, iISR); … … 348 350 GEN_CHECK_OFF(PCNetState, iLog2DescSize); 349 351 GEN_CHECK_OFF(PCNetState, GCUpperPhys); 350 GEN_CHECK_OFF(PCNetState, pXmitQueueHC); 351 GEN_CHECK_OFF(PCNetState, pXmitQueueGC); 352 GEN_CHECK_OFF(PCNetState, pCanRxQueueHC); 353 GEN_CHECK_OFF(PCNetState, pCanRxQueueGC); 352 GEN_CHECK_OFF(PCNetState, pXmitQueueR3); 353 GEN_CHECK_OFF(PCNetState, pXmitQueueR0); 354 GEN_CHECK_OFF(PCNetState, pXmitQueueRC); 355 GEN_CHECK_OFF(PCNetState, pCanRxQueueR3); 356 GEN_CHECK_OFF(PCNetState, pCanRxQueueR0); 357 GEN_CHECK_OFF(PCNetState, pCanRxQueueRC); 354 358 GEN_CHECK_OFF(PCNetState, pTimerRestore); 355 GEN_CHECK_OFF(PCNetState, pDevInsHC); 356 GEN_CHECK_OFF(PCNetState, pDevInsGC); 359 GEN_CHECK_OFF(PCNetState, pDevInsR3); 360 GEN_CHECK_OFF(PCNetState, pDevInsR0); 361 GEN_CHECK_OFF(PCNetState, pDevInsRC); 357 362 GEN_CHECK_OFF(PCNetState, pDrv); 358 363 GEN_CHECK_OFF(PCNetState, pDrvBase); … … 381 386 GEN_CHECK_OFF(PCNetState, pfnEMInterpretInstructionR0 382 387 #endif 383 GEN_CHECK_OFF(PCNetState, pSharedMMIOHC); 384 GEN_CHECK_OFF(PCNetState, pSharedMMIOGC); 388 GEN_CHECK_OFF(PCNetState, pSharedMMIOR3); 389 GEN_CHECK_OFF(PCNetState, pSharedMMIOR0); 390 GEN_CHECK_OFF(PCNetState, pSharedMMIORC); 385 391 GEN_CHECK_OFF(PCNetState, fPrivIfEnabled); 386 392 GEN_CHECK_OFF(PCNetState, fGCEnabled);
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