Changeset 11261 in vbox for trunk/src/VBox/Devices/PC
- Timestamp:
- Aug 8, 2008 3:46:17 PM (16 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/PC/DevPIC.cpp
r10202 r11261 1 1 /* $Id$ */ 2 2 /** @file 3 * Intel 8259 Programmable Interrupt Controller (PIC) Device.3 * DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device. 4 4 */ 5 5 … … 28 28 #include <iprt/assert.h> 29 29 30 #include " vl_vbox.h"30 #include "../vl_vbox.h" 31 31 32 32 … … 40 40 #define PIC_LOCK(pThis, rc) \ 41 41 do { \ 42 int rc2 = (pThis)->CTX ALLSUFF(pPicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \42 int rc2 = (pThis)->CTX_SUFF(pPicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \ 43 43 if (rc2 != VINF_SUCCESS) \ 44 44 return rc2; \ 45 45 } while (0) 46 46 #define PIC_UNLOCK(pThis) \ 47 (pThis)->CTX ALLSUFF(pPicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))47 (pThis)->CTX_SUFF(pPicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns)) 48 48 49 49 … … 111 111 uint8_t elcr; /* PIIX edge/trigger selection*/ 112 112 uint8_t elcr_mask; 113 /** Pointer to the device instance, HCPtr. */114 R3R0PTRTYPE(PPDMDEVINS) pDevInsHC;115 /** Pointer to the device instance, GCPtr. */116 RCPTRTYPE(PPDMDEVINS) pDevInsGC;117 #if HC_ARCH_BITS == 64 118 RTRCPTR Alignment0;119 #endif 113 /** Pointer to the device instance, R3 Ptr. */ 114 PPDMDEVINSR3 pDevInsR3; 115 /** Pointer to the device instance, R0 Ptr. */ 116 PPDMDEVINSR0 pDevInsR0; 117 /** Pointer to the device instance, RC Ptr. */ 118 PPDMDEVINSRC pDevInsRC; 119 RTRCPTR Alignment0; /**< Structure size alignment. */ 120 120 } PicState; 121 121 … … 127 127 /** The two interrupt controllers. */ 128 128 PicState aPics[2]; 129 /** Pointer to the device instance - R3 Ptr. */ 130 PPDMDEVINSR3 pDevInsR3; 129 131 /** Pointer to the PIC R3 helpers. */ 130 132 PCPDMPICHLPR3 pPicHlpR3; 133 /** Pointer to the device instance - R0 Ptr. */ 134 PPDMDEVINSR0 pDevInsR0; 131 135 /** Pointer to the PIC R0 helpers. */ 132 136 PCPDMPICHLPR0 pPicHlpR0; 133 /** Pointer to the PIC GC helpers. */ 134 PCPDMPICHLPGC pPicHlpGC; 135 #if HC_ARCH_BITS == 32 136 uint32_t Alignmnet1; 137 #endif 138 /** Pointer to the device instance - GC Ptr. */ 139 RCPTRTYPE(PPDMDEVINS) pDevInsGC; 140 /** Pointer to the device instance - GC Ptr. */ 141 R3R0PTRTYPE(PPDMDEVINS) pDevInsHC; 137 /** Pointer to the device instance - RC Ptr. */ 138 PPDMDEVINSRC pDevInsRC; 139 /** Pointer to the PIC RC helpers. */ 140 PCPDMPICHLPRC pPicHlpRC; 142 141 #ifdef VBOX_WITH_STATISTICS 143 142 STAMCOUNTER StatSetIrqGC; … … 154 153 static inline void DumpPICState(PicState *s, const char *szFn) 155 154 { 156 PDEVPIC pData = PDMINS2DATA( CTXSUFF(s->pDevIns), PDEVPIC);155 PDEVPIC pData = PDMINS2DATA(s->CTX_SUFF(pDevIns), PDEVPIC); 157 156 158 157 Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n", … … 213 212 static int pic_get_irq(PicState *s) 214 213 { 215 PicState *pics = &(PDMINS2DATA( CTXSUFF(s->pDevIns), PDEVPIC))->aPics[0];214 PicState *pics = &(PDMINS2DATA(s->CTX_SUFF(pDevIns), PDEVPIC))->aPics[0]; 216 215 int mask, cur_priority, priority; 217 216 Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr)); … … 272 271 Log(("pic: cpu_interrupt\n")); 273 272 #endif 274 pData->CTX ALLSUFF(pPicHlp)->pfnSetInterruptFF(pData->CTXSUFF(pDevIns));273 pData->CTX_SUFF(pPicHlp)->pfnSetInterruptFF(pData->CTX_SUFF(pDevIns)); 275 274 } 276 275 else … … 281 280 282 281 /* if this was the only pending irq, then we must clear the interrupt ff flag */ 283 pData->CTX ALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));282 pData->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pData->CTX_SUFF(pDevIns)); 284 283 285 284 /** @note Is this correct? */ … … 295 294 296 295 /* we must clear the interrupt ff flag */ 297 pData->CTX ALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));296 pData->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pData->CTX_SUFF(pDevIns)); 298 297 } 299 298 return VINF_SUCCESS; … … 339 338 340 339 Log(("pic_update_imr: clear pending interrupt %d\n", intno)); 341 pData->CTX ALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));340 pData->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pData->CTX_SUFF(pDevIns)); 342 341 } 343 342 } … … 354 353 { 355 354 PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC); 356 Assert(pData->CTX SUFF(pDevIns) == pDevIns);357 Assert(pData->aPics[0].CTX SUFF(pDevIns) == pDevIns);358 Assert(pData->aPics[1].CTX SUFF(pDevIns) == pDevIns);355 Assert(pData->CTX_SUFF(pDevIns) == pDevIns); 356 Assert(pData->aPics[0].CTX_SUFF(pDevIns) == pDevIns); 357 Assert(pData->aPics[1].CTX_SUFF(pDevIns) == pDevIns); 359 358 AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq)); 360 359 … … 449 448 static void pic_reset(PicState *s) 450 449 { 451 R3R0PTRTYPE(PPDMDEVINS) pDevInsHC = s->pDevInsHC;452 RCPTRTYPE(PPDMDEVINS) pDevInsGC = s->pDevInsGC;453 int tmp, tmp2;454 455 tmp = s->elcr_mask;456 tmp2 = s->elcr; 450 PPDMDEVINSR3 pDevInsR3 = s->pDevInsR3; 451 PPDMDEVINSR0 pDevInsR0 = s->pDevInsR0; 452 PPDMDEVINSRC pDevInsRC = s->pDevInsRC; 453 int elcr_mask = s->elcr_mask; 454 int elcr = s->elcr; 455 457 456 memset(s, 0, sizeof(PicState)); 458 s->elcr_mask = tmp; 459 s->elcr = tmp2; 460 s->pDevInsHC = pDevInsHC; 461 s->pDevInsGC = pDevInsGC; 457 458 s->elcr = elcr; 459 s->elcr_mask = elcr_mask; 460 s->pDevInsRC = pDevInsRC; 461 s->pDevInsR0 = pDevInsR0; 462 s->pDevInsR3 = pDevInsR3; 462 463 } 463 464 … … 466 467 { 467 468 PicState *s = (PicState*)opaque; 468 PDEVPIC pData = PDMINS2DATA( CTXSUFF(s->pDevIns), PDEVPIC);469 PDEVPIC pData = PDMINS2DATA(s->CTX_SUFF(pDevIns), PDEVPIC); 469 470 int rc = VINF_SUCCESS; 470 471 int priority, cmd, irq; … … 477 478 pic_reset(s); 478 479 /* deassert a pending interrupt */ 479 pData->CTX ALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));480 pData->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pData->CTX_SUFF(pDevIns)); 480 481 481 482 s->init_state = 1; … … 586 587 static uint32_t pic_poll_read (PicState *s, uint32_t addr1) 587 588 { 588 PDEVPIC pData = PDMINS2DATA( CTXSUFF(s->pDevIns), PDEVPIC);589 PDEVPIC pData = PDMINS2DATA(s->CTX_SUFF(pDevIns), PDEVPIC); 589 590 PicState *pics = &pData->aPics[0]; 590 591 int ret; … … 902 903 unsigned i; 903 904 904 pData->pDevIns GC = PDMDEVINS_2_GCPTR(pDevIns);905 pData->pPicHlp GC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);906 for (i = 0; i < ELEMENTS(pData->aPics); i++)907 pData->aPics[i].pDevIns GC = PDMDEVINS_2_GCPTR(pDevIns);905 pData->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 906 pData->pPicHlpRC = pData->pPicHlpR3->pfnGetRCHelpers(pDevIns); 907 for (i = 0; i < RT_ELEMENTS(pData->aPics); i++) 908 pData->aPics[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 908 909 } 909 910 … … 947 948 */ 948 949 Assert(ELEMENTS(pData->aPics) == 2); 949 pData->pDevInsHC = pDevIns; 950 pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns); 950 pData->pDevInsR3 = pDevIns; 951 pData->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 952 pData->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 951 953 pData->aPics[0].elcr_mask = 0xf8; 952 954 pData->aPics[1].elcr_mask = 0xde; 953 pData->aPics[0].pDevInsHC = pDevIns; 954 pData->aPics[1].pDevInsHC = pDevIns; 955 pData->aPics[0].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns); 956 pData->aPics[1].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns); 955 pData->aPics[0].pDevInsR3 = pDevIns; 956 pData->aPics[1].pDevInsR3 = pDevIns; 957 pData->aPics[0].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 958 pData->aPics[1].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns); 959 pData->aPics[0].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 960 pData->aPics[1].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns); 957 961 958 962 /* 959 * Register PIC, I/O ports and save state.963 * Register us as the PIC with PDM. 960 964 */ 961 965 PicReg.u32Version = PDM_PICREG_VERSION; 962 PicReg.pfnSetIrqHC = picSetIrq; 963 PicReg.pfnGetInterruptHC = picGetInterrupt; 966 PicReg.pfnSetIrqR3 = picSetIrq; 967 PicReg.pfnGetInterruptR3 = picGetInterrupt; 968 964 969 if (fGCEnabled) 965 970 { 966 PicReg.pszSetIrq GC = "picSetIrq";967 PicReg.pszGetInterrupt GC = "picGetInterrupt";971 PicReg.pszSetIrqRC = "picSetIrq"; 972 PicReg.pszGetInterruptRC = "picGetInterrupt"; 968 973 } 969 974 else 970 975 { 971 PicReg.pszSetIrq GC = NULL;972 PicReg.pszGetInterrupt GC = NULL;976 PicReg.pszSetIrqRC = NULL; 977 PicReg.pszGetInterruptRC = NULL; 973 978 } 974 979 … … 986 991 Assert(pDevIns->pDevHlp->pfnPICRegister); 987 992 rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pData->pPicHlpR3); 988 if (VBOX_FAILURE(rc)) 989 { 990 AssertMsgFailed(("PICRegister -> %Vrc\n", rc)); 991 return rc; 992 } 993 AssertLogRelMsgRCReturn(rc, ("PICRegister -> %Vrc\n", rc), rc); 993 994 if (fGCEnabled) 994 pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns); 995 pData->pPicHlpRC = pData->pPicHlpR3->pfnGetRCHelpers(pDevIns); 996 if (fR0Enabled) 997 pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns); 998 999 1000 /* 1001 * Register I/O ports and save state. 1002 */ 995 1003 rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0"); 996 1004 if (VBOX_FAILURE(rc)) … … 1010 1018 if (fR0Enabled) 1011 1019 { 1012 pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns);1013 1014 1020 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0"); 1015 1021 if (VBOX_FAILURE(rc))
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