Changeset 11525 in vbox for trunk/src/VBox/VMM

Timestamp:

Aug 21, 2008 9:07:51 AM (16 years ago)

Author:

vboxsync

Message:

Added support for PSE-36.

Location:

trunk/src/VBox/VMM

Files:

• CPUM.cpp (modified) (2 diffs)
• PGM.cpp (modified) (4 diffs)
• PGMGst.h (modified) (3 diffs)
• PGMInternal.h (modified) (2 diffs)
• VMMAll/PGMAllBth.h (modified) (7 diffs)
• VMMAll/PGMAllGst.h (modified) (3 diffs)
• VMMAll/PGMAllPhys.cpp (modified) (1 diff)

trunk/src/VBox/VMM/CPUM.cpp

@@ -264 +264 @@
                                        | X86_CPUID_FEATURE_EDX_CMOV
                                        | X86_CPUID_FEATURE_EDX_PAT
-                                       //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
+                                       | X86_CPUID_FEATURE_EDX_PSE36
                                        //| X86_CPUID_FEATURE_EDX_PSN   - no serial number.
                                        | X86_CPUID_FEATURE_EDX_CLFSH
@@ -311 +311 @@
                                        | X86_CPUID_AMD_FEATURE_EDX_CMOV
                                        | X86_CPUID_AMD_FEATURE_EDX_PAT
-                                       //| X86_CPUID_AMD_FEATURE_EDX_PSE36  - not virtualized.
+                                       | X86_CPUID_AMD_FEATURE_EDX_PSE36
                                        //| X86_CPUID_AMD_FEATURE_EDX_NX     - not virtualized, requires PAE.
                                        //| X86_CPUID_AMD_FEATURE_EDX_AXMMX

trunk/src/VBox/VMM/PGM.cpp

@@ -1821 +1821 @@
     LogFlow(("PGMR3Relocate\n"));
 
+    /* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total); Intel only goes up to 36 bits, so
+     * we stick to 36 as well.
+     *
+     * @todo How to test for the 40 bits support? Long mode seems to be the test criterium.
+     */
+    uint32_t u32Dummy, u32Features;
+    CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
+
+    if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
+        pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
+    else
+        pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
+
+    LogRel(("PGMR3Relocate: 4 MB PSE mask %VGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
+
+
     /*
      * Paging stuff.
@@ -2549 +2565 @@
                                 "%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
                                 iPD,
-                                PdeSrc.u & X86_PDE_PG_MASK,
+                                pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
                                 PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
             }
@@ -2557 +2573 @@
                                 "%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
                                 iPD,
-                                PdeSrc.u & X86_PDE4M_PG_MASK,
+                                PdeSrc.u & X86_PDE_PG_MASK,
                                 PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
             }
@@ -3927 +3943 @@
                      Pde.u & RT_BIT(10)     ? '1' : '0',
                      Pde.u & RT_BIT(11)     ? '1' : '0',
-                     Pde.u & X86_PDE4M_PG_MASK));
+                     pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
             /** @todo PhysSearch */
             else

trunk/src/VBox/VMM/PGMGst.h

@@ -43 +43 @@
 #undef GST_CR3_PAGE_MASK
 #undef GST_PDPE_ENTRIES
+#undef GST_GET_PDE_BIG_PG_GCPHYS
 
 #if PGM_GST_TYPE == PGM_TYPE_32BIT \
@@ -59 +60 @@
 # define GST_PDE_PG_MASK            X86_PDE_PG_MASK
 # define GST_PDE_BIG_PG_MASK        X86_PDE4M_PG_MASK
+# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst)  pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeGst)
 # define GST_PD_SHIFT               X86_PD_SHIFT
 # define GST_PD_MASK                X86_PD_MASK
@@ -80 +82 @@
 # define GST_PDE_PG_MASK            X86_PDE_PAE_PG_MASK
 # define GST_PDE_BIG_PG_MASK        X86_PDE2M_PAE_PG_MASK
+# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst)  (PdeGst.u & GST_PDE_BIG_PG_MASK)
 # define GST_PD_SHIFT               X86_PD_PAE_SHIFT
 # define GST_PD_MASK                X86_PD_PAE_MASK

trunk/src/VBox/VMM/PGMInternal.h

@@ -2224 +2224 @@
     RTHCPHYS                        aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
 
+    /** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
+    RTGCPHYS                        GCPhys4MBPSEMask;
+
     /** A20 gate mask.
      * Our current approach to A20 emulation is to let REM do it and don't bother
@@ -3242 +3245 @@
 }
 
+/**
+ * Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
+ * Takes PSE-36 into account.
+ *
+ * @returns guest physical address
+ * @param   pPGM        Pointer to the PGM instance data.
+ * @param   Pde         Guest Pde
+ */
+DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
+{
+    RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
+    GCPhys |= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
+
+    return GCPhys & pPGM->GCPhys4MBPSEMask;
+}
 
 /**

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -326 +326 @@
         if (    PdeSrc.b.u1Size
             &&  fBigPagesSupported)
-            GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
+            GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
                     | ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
         else
@@ -1211 +1211 @@
             /* Before freeing the page, check if anything really changed. */
             PPGMPOOLPAGE    pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
-            RTGCPHYS        GCPhys   = PdeSrc.u & GST_PDE_BIG_PG_MASK;
+            RTGCPHYS        GCPhys   = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
 # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
             /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
@@ -1591 +1591 @@
     else
     {
-        GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
+        GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
 # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
         /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
@@ -1706 +1706 @@
                  */
                 /* Calculate the GC physical address of this 4KB shadow page. */
-                RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) | ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
+                RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) | ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
                 /* Find ram range. */
                 PPGMPAGE pPage;
@@ -2355 +2355 @@
         else
         {
-            GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
+            GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
 # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
             /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
@@ -3335 +3335 @@
                             else
                             {
-                                GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
+                                GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
 #  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
                                 /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
@@ -3853 +3853 @@
                         }
 # endif
-                        GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
+                        GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
 # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
                         GCPhysGst |= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -47 +47 @@
 #undef GST_PDPT_MASK
 #undef GST_PDPE_PG_MASK
+#undef GST_GET_PDE_BIG_PG_GCPHYS
 
 #if PGM_GST_TYPE == PGM_TYPE_REAL \
@@ -72 +73 @@
 # define GST_PDE_PG_MASK            X86_PDE_PG_MASK
 # define GST_PDE_BIG_PG_MASK        X86_PDE4M_PG_MASK
+# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst)  pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeGst)
 # define GST_PD_SHIFT               X86_PD_SHIFT
 # define GST_PD_MASK                X86_PD_MASK
@@ -93 +95 @@
 # define GST_PDE_PG_MASK            X86_PDE_PAE_PG_MASK_FULL
 # define GST_PDE_BIG_PG_MASK        X86_PDE2M_PAE_PG_MASK
+# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst)  (PdeGst.u & GST_PDE_BIG_PG_MASK)
 # define GST_PD_SHIFT               X86_PD_PAE_SHIFT
 # define GST_PD_MASK                X86_PD_PAE_MASK

trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp

@@ -1002 +1002 @@
                 if ((fFlags & X86_CR4_PSE) && Pde.b.u1Size)
                 {   /* (big page) */
-                    rc = PGMPhysGCPhys2HCPtr(pVM, (Pde.u & X86_PDE4M_PG_MASK) | ((RTGCUINTPTR)GCPtr & X86_PAGE_4M_OFFSET_MASK), 1 /* we always stay within one page */, pHCPtr);
+                    rc = PGMPhysGCPhys2HCPtr(pVM, pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde) | ((RTGCUINTPTR)GCPtr & X86_PAGE_4M_OFFSET_MASK), 1 /* we always stay within one page */, pHCPtr);
                 }
                 else