Changeset 11798 in vbox

Timestamp:

Aug 29, 2008 9:48:49 AM (17 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

35616

Message:

Fixing backwards compatibility for CPUMCTX.

Location:

trunk

Files:

• include/VBox/cpum.h (modified) (1 diff)
• include/VBox/types.h (modified) (2 diffs)
• src/VBox/VMM/CPUM.cpp (modified) (4 diffs)

trunk/include/VBox/cpum.h

@@ -363 +363 @@
  */
 #define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
+
+
+/**
+ * Selector hidden registers. (version 1.6)
+ */
+typedef struct CPUMSELREGHID_VER1_6
+{
+    /** Base register. */
+    uint32_t    u32Base;
+    /** Limit (expanded). */
+    uint32_t    u32Limit;
+    /** Flags.
+     * This is the high 32-bit word of the descriptor entry.
+     * Only the flags, dpl and type are used. */
+    X86DESCATTR Attr;
+} CPUMSELREGHID_VER1_6;
+
+/**
+ * CPU context. (Version 1.6)
+ */
+#pragma pack(1)
+typedef struct CPUMCTX_VER1_6
+{
+    /** FPU state. (16-byte alignment)
+     * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
+     *       actual format or convert it (waste of time).  */
+    X86FXSTATE      fpu;
+
+    /** CPUMCTXCORE Part.
+     * @{ */
+    union
+    {
+        uint32_t        edi;
+        uint64_t        rdi;
+    };
+    union
+    {
+        uint32_t        esi;
+        uint64_t        rsi;
+    };
+    union
+    {
+        uint32_t        ebp;
+        uint64_t        rbp;
+    };
+    union
+    {
+        uint32_t        eax;
+        uint64_t        rax;
+    };
+    union
+    {
+        uint32_t        ebx;
+        uint64_t        rbx;
+    };
+    union
+    {
+        uint32_t        edx;
+        uint64_t        rdx;
+    };
+    union
+    {
+        uint32_t        ecx;
+        uint64_t        rcx;
+    };
+    /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
+    uint32_t        esp;
+    RTSEL           ss;
+    RTSEL           ssPadding;
+    /* Note: no overlap with esp here. */
+    uint64_t        rsp;
+
+    RTSEL           gs;
+    RTSEL           gsPadding;
+    RTSEL           fs;
+    RTSEL           fsPadding;
+    RTSEL           es;
+    RTSEL           esPadding;
+    RTSEL           ds;
+    RTSEL           dsPadding;
+    RTSEL           cs;
+    RTSEL           csPadding[3];  /* 3 words to force 8 byte alignment for the remainder */
+
+    union
+    {
+        X86EFLAGS       eflags;
+        X86RFLAGS       rflags;
+    };
+    union
+    {
+        uint32_t        eip;
+        uint64_t        rip;
+    };
+
+    uint64_t            r8;
+    uint64_t            r9;
+    uint64_t            r10;
+    uint64_t            r11;
+    uint64_t            r12;
+    uint64_t            r13;
+    uint64_t            r14;
+    uint64_t            r15;
+
+    /** Hidden selector registers.
+     * @{ */
+    CPUMSELREGHID_VER1_6   esHid;
+    CPUMSELREGHID_VER1_6   csHid;
+    CPUMSELREGHID_VER1_6   ssHid;
+    CPUMSELREGHID_VER1_6   dsHid;
+    CPUMSELREGHID_VER1_6   fsHid;
+    CPUMSELREGHID_VER1_6   gsHid;
+    /** @} */
+
+    /** @} */
+
+    /** Control registers.
+     * @{ */
+    uint64_t        cr0;
+    uint64_t        cr2;
+    uint64_t        cr3;
+    uint64_t        cr4;
+    uint64_t        cr8;
+    /** @} */
+
+    /** Debug registers.
+     * @{ */
+    uint64_t        dr0;
+    uint64_t        dr1;
+    uint64_t        dr2;
+    uint64_t        dr3;
+    uint64_t        dr4; /**< @todo remove dr4 and dr5. */
+    uint64_t        dr5;
+    uint64_t        dr6;
+    uint64_t        dr7;
+    /* DR8-15 are currently not supported */
+    /** @} */
+
+    /** Global Descriptor Table register. */
+    VBOXGDTR_VER1_6 gdtr;
+    uint16_t        gdtrPadding;
+    uint32_t        gdtrPadding64;/** @todo fix this hack */
+    /** Interrupt Descriptor Table register. */
+    VBOXIDTR_VER1_6 idtr;
+    uint16_t        idtrPadding;
+    uint32_t        idtrPadding64;/** @todo fix this hack */
+    /** The task register.
+     * Only the guest context uses all the members. */
+    RTSEL           ldtr;
+    RTSEL           ldtrPadding;
+    /** The task register.
+     * Only the guest context uses all the members. */
+    RTSEL           tr;
+    RTSEL           trPadding;
+
+    /** The sysenter msr registers.
+     * This member is not used by the hypervisor context. */
+    CPUMSYSENTER    SysEnter;
+
+    /** System MSRs.
+     * @{ */
+    uint64_t        msrEFER;
+    uint64_t        msrSTAR;
+    uint64_t        msrPAT;
+    uint64_t        msrLSTAR;
+    uint64_t        msrCSTAR;
+    uint64_t        msrSFMASK;
+    uint64_t        msrFSBASE;
+    uint64_t        msrGSBASE;
+    uint64_t        msrKERNELGSBASE;
+    /** @} */
+
+    /** Hidden selector registers.
+     * @{ */
+    CPUMSELREGHID_VER1_6   ldtrHid;
+    CPUMSELREGHID_VER1_6   trHid;
+    /** @} */
+
+    /* padding to get 32byte aligned size */
+    uint32_t        padding[2];
+} CPUMCTX_VER1_6;
+#pragma pack()
 
 /**

trunk/include/VBox/types.h

@@ -375 +375 @@
 } VBOXIDTR, *PVBOXIDTR;
 #pragma pack()
+
+#pragma pack(1)
+/** IDTR from version 1.6 */
+typedef struct VBOXIDTR_VER1_6
+{
+    /** Size of the IDT. */
+    uint16_t    cbIdt;
+    /** Address of the IDT. */
+    uint32_t     pIdt;
+} VBOXIDTR_VER1_6, *PVBOXIDTR_VER1_6;
+#pragma pack()
+
 /** @} */
 
@@ -397 +409 @@
 /** Pointer to GDTR. */
 typedef VBOXGDTR *PVBOXGDTR;
+
+#pragma pack(1)
+/** GDTR from version 1.6 */
+typedef struct VBOXGDTR_VER1_6
+{
+    /** Size of the GDT. */
+    uint16_t    cbGdt;
+    /** Address of the GDT. */
+    uint32_t    pGdt;
+} VBOXGDTR_VER1_6;
+#pragma pack()
 
 /** @} */

trunk/src/VBox/VMM/CPUM.cpp

@@ -64 +64 @@
 *******************************************************************************/
 /** The saved state version. */
-#define CPUM_SAVED_STATE_VERSION    8
+#define CPUM_SAVED_STATE_VERSION_VER1_6     6
+#define CPUM_SAVED_STATE_VERSION            8
 
 
@@ -752 +753 @@
 }
 
+/**
+ * Load a version 1.6 CPUMCTX structure.
+ *
+ * @returns VBox status code.
+ * @param   pVM             VM Handle.
+ * @param   pCpumctx16      Version 1.6 CPUMCTX
+ */
+static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
+{
+#define CPUMCTX16_LOADREG(regname)      pVM->cpum.s.Guest.regname = pCpumctx16->regname;
+
+#define CPUMCTX16_LOADHIDREG(regname)                                                   \
+    pVM->cpum.s.Guest.regname##Hid.u64Base      = pCpumctx16->regname##Hid.u32Base;     \
+    pVM->cpum.s.Guest.regname##Hid.u32Limit     = pCpumctx16->regname##Hid.u32Limit;    \
+    pVM->cpum.s.Guest.regname##Hid.Attr         = pCpumctx16->regname##Hid.Attr;
+
+#define CPUMCTX16_LOADSEGREG(regname)                                                   \
+    pVM->cpum.s.Guest.regname                   = pCpumctx16->regname;                  \
+    CPUMCTX16_LOADHIDREG(regname);
+
+    pVM->cpum.s.Guest.fpu               = pCpumctx16->fpu;
+
+    CPUMCTX16_LOADREG(rax);
+    CPUMCTX16_LOADREG(rbx);
+    CPUMCTX16_LOADREG(rcx);
+    CPUMCTX16_LOADREG(rdx);
+    CPUMCTX16_LOADREG(rdi);
+    CPUMCTX16_LOADREG(rsi);
+    CPUMCTX16_LOADREG(rbp);
+    CPUMCTX16_LOADREG(rsp);
+    CPUMCTX16_LOADREG(rip);
+    CPUMCTX16_LOADREG(rflags);
+
+    CPUMCTX16_LOADSEGREG(cs);
+    CPUMCTX16_LOADSEGREG(ds);
+    CPUMCTX16_LOADSEGREG(es);
+    CPUMCTX16_LOADSEGREG(fs);
+    CPUMCTX16_LOADSEGREG(gs);
+    CPUMCTX16_LOADSEGREG(ss);
+
+    CPUMCTX16_LOADREG(r8);
+    CPUMCTX16_LOADREG(r9);
+    CPUMCTX16_LOADREG(r10);
+    CPUMCTX16_LOADREG(r11);
+    CPUMCTX16_LOADREG(r12);
+    CPUMCTX16_LOADREG(r13);
+    CPUMCTX16_LOADREG(r14);
+    CPUMCTX16_LOADREG(r15);
+
+    CPUMCTX16_LOADREG(cr0);
+    CPUMCTX16_LOADREG(cr2);
+    CPUMCTX16_LOADREG(cr3);
+    CPUMCTX16_LOADREG(cr4);
+
+    CPUMCTX16_LOADREG(dr0);
+    CPUMCTX16_LOADREG(dr1);
+    CPUMCTX16_LOADREG(dr2);
+    CPUMCTX16_LOADREG(dr3);
+    CPUMCTX16_LOADREG(dr4);
+    CPUMCTX16_LOADREG(dr5);
+    CPUMCTX16_LOADREG(dr6);
+    CPUMCTX16_LOADREG(dr7);
+
+    pVM->cpum.s.Guest.gdtr.cbGdt   = pCpumctx16->gdtr.cbGdt;
+    pVM->cpum.s.Guest.gdtr.pGdt    = pCpumctx16->gdtr.pGdt;
+    pVM->cpum.s.Guest.idtr.cbIdt   = pCpumctx16->idtr.cbIdt;
+    pVM->cpum.s.Guest.idtr.pIdt    = pCpumctx16->idtr.pIdt;
+
+    CPUMCTX16_LOADREG(ldtr);
+    CPUMCTX16_LOADREG(tr);
+
+    pVM->cpum.s.Guest.SysEnter     = pCpumctx16->SysEnter;
+
+    CPUMCTX16_LOADREG(msrEFER);
+    CPUMCTX16_LOADREG(msrSTAR);
+    CPUMCTX16_LOADREG(msrPAT);
+    CPUMCTX16_LOADREG(msrLSTAR);
+    CPUMCTX16_LOADREG(msrCSTAR);
+    CPUMCTX16_LOADREG(msrSFMASK);
+    CPUMCTX16_LOADREG(msrKERNELGSBASE);
+
+    CPUMCTX16_LOADHIDREG(ldtr);
+    CPUMCTX16_LOADHIDREG(tr);
+
+#undef CPUMCTX16_LOADHIDREG
+#undef CPUMCTX16_LOADSEGREG
+#undef CPUMCTX16_LOADREG
+}
 
 /**
@@ -766 +855 @@
      * Validate version.
      */
-    if (u32Version != CPUM_SAVED_STATE_VERSION)
+    if (    u32Version != CPUM_SAVED_STATE_VERSION
+        &&  u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
     {
         AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
@@ -780 +870 @@
     pVM->cpum.s.Hyper.cr3 = uCR3;
     pVM->cpum.s.Hyper.esp = uESP;
-    SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
+    if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
+    {
+        CPUMCTX_VER1_6 cpumctx16;
+        memset(&pVM->cpum.s.Guest, 0, sizeof(pVM->cpum.s.Guest));
+        SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
+        
+        /* Save the old cpumctx state into the new one. */
+        cpumR3LoadCPUM1_6(pVM, &cpumctx16);
+    }
+    else
+        SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
+
     SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
     SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);