Changeset 12588 in vbox

Timestamp:

Sep 18, 2008 5:47:53 PM (16 years ago)

Author:

vboxsync

Message:

reworked APIC structures layout - hopefully not broken smth accidentally

Location:

trunk/src/VBox

Files:

• Devices/PC/DevAPIC.cpp (modified) (57 diffs)
• Devices/testcase/tstDeviceStructSize.cpp (modified) (1 diff)
• Devices/testcase/tstDeviceStructSizeGC.cpp (modified) (1 diff)
• Main/ConsoleImpl2.cpp (modified) (1 diff)

trunk/src/VBox/Devices/PC/DevAPIC.cpp

@@ -78 +78 @@
 #define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
 
+/**  @def FIRST_LAPIC
+ * Return address of first LAPIC state. If this macro is use - it's probably
+ * something wrong or fishy with the code using it, unless explained. */ 
+#define FIRST_LAPIC(pThis) ((APICState*)(pThis)->CTX_SUFF(pLapics))
 
 #endif /* VBOX */
@@ -181 +185 @@
     QEMUTimer *timer;
     struct APICState *next_apic;
-#else /* VBOX */
-#ifdef VBOX_WITH_SMP_GUESTS
-    //struct APICState *next_apic;
-#endif
-    /** The device instance - R3 Ptr. */
-    PPDMDEVINSR3    pDevInsR3;
-    /** The APIC helpers - R3 Ptr. */
-    PCPDMAPICHLPR3  pApicHlpR3;
-    /** The APIC timer - R3 Ptr. */
-    PTMTIMERR3      pTimerR3;
-
-    /** The device instance - R0 Ptr. */
-    PPDMDEVINSR0    pDevInsR0;
-    /** The APIC helpers - R0 Ptr. */
-    PCPDMAPICHLPR0  pApicHlpR0;
-    /** The APIC timer - R0 Ptr. */
-    PTMTIMERR0      pTimerR0;
-
-    /** The device instance - RC Ptr. */
-    PPDMDEVINSRC    pDevInsRC;
-    /** The APIC helpers - RC Ptr. */
-    PCPDMAPICHLPRC  pApicHlpRC;
-    /** The APIC timer - RC Ptr. */
-    PTMTIMERRC      pTimerRC;
-
-    /** Number of attempts made to optimize TPR accesses. */
-    uint32_t        ulTPRPatchAttempts;
-
-# ifdef VBOX_WITH_STATISTICS
-    STAMCOUNTER     StatMMIOReadGC;
-    STAMCOUNTER     StatMMIOReadHC;
-    STAMCOUNTER     StatMMIOWriteGC;
-    STAMCOUNTER     StatMMIOWriteHC;
-    STAMCOUNTER     StatClearedActiveIrq;
-# endif
 #endif /* VBOX */
 } APICState;
@@ -255 +224 @@
 #ifdef VBOX
 typedef struct IOAPICState IOAPICState;
+
+typedef struct
+{
+    /** The device instance - R3 Ptr. */
+    PPDMDEVINSR3    pDevInsR3;
+    /** The APIC helpers - R3 Ptr. */
+    PCPDMAPICHLPR3  pApicHlpR3;
+    /** The APIC timer - R3 Ptr. */
+    PTMTIMERR3      pTimerR3;
+    /** LAPICs states - R3 Ptr */
+    RTR3PTR         pLapicsR3; 
+
+    /** The device instance - R0 Ptr. */
+    PPDMDEVINSR0    pDevInsR0;
+    /** The APIC helpers - R0 Ptr. */
+    PCPDMAPICHLPR0  pApicHlpR0;
+    /** The APIC timer - R0 Ptr. */
+    PTMTIMERR0      pTimerR0;
+    /** LAPICs states - R0 Ptr */
+    RTR0PTR         pLapicsR0; 
+
+    /** The device instance - RC Ptr. */
+    PPDMDEVINSRC    pDevInsRC;
+    /** The APIC helpers - RC Ptr. */
+    PCPDMAPICHLPRC  pApicHlpRC;
+    /** The APIC timer - RC Ptr. */
+    PTMTIMERRC      pTimerRC;
+     /** LAPICs states - RC Ptr */
+    RTRCPTR         pLapicsRC; 
+
+    /** Number of attempts made to optimize TPR accesses. */
+    uint32_t        ulTPRPatchAttempts;
+    
+    /** Number of LAPICs on the system (same as CPU count). */
+    uint32_t        cCpus;
+
+# ifdef VBOX_WITH_STATISTICS
+    STAMCOUNTER     StatMMIOReadGC;
+    STAMCOUNTER     StatMMIOReadHC;
+    STAMCOUNTER     StatMMIOWriteGC;
+    STAMCOUNTER     StatMMIOWriteHC;
+    STAMCOUNTER     StatClearedActiveIrq;
+# endif
+} APICDeviceInfo;
+
+DECLINLINE(APICState*) getLAPIC(APICDeviceInfo* dev)
+{
+    uint32_t id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
+    return FIRST_LAPIC(dev) + id;
+}
+
 #endif /* VBOX */
 
@@ -265 +285 @@
 
 static void apic_init_ipi(APICState *s);
-static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
-static bool apic_update_irq(APICState *s);
+static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
+static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
 
 #ifdef VBOX
@@ -286 +306 @@
 PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
 
-static void apic_update_tpr(APICState *s, uint32_t val);
+static void apic_update_tpr(APICDeviceInfo *dev, APICState* s, uint32_t val);
 __END_DECLS
 #endif /* VBOX */
@@ -297 +317 @@
     APICState *apic_iter;
 #else /* VBOX */
-static void apic_bus_deliver(APICState *s, uint32_t deliver_bitmask, uint8_t delivery_mode,
+static void apic_bus_deliver(APICDeviceInfo* dev,
+                             APICState *s, uint32_t deliver_bitmask, uint8_t delivery_mode,
                              uint8_t vector_num, uint8_t polarity,
                              uint8_t trigger_mode)
@@ -336 +357 @@
 #ifdef VBOX
     if (deliver_bitmask & (1 << s->id))
-        apic_set_irq (s, vector_num, trigger_mode);
+        apic_set_irq (dev, s, vector_num, trigger_mode);
 #else  /* VBOX */
     for (apic_iter = first_local_apic; apic_iter != NULL;
@@ -366 +387 @@
 PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    APICState *s = getLAPIC(dev);
     Log(("cpu_set_apic_base: %016RX64\n", val));
 
@@ -378 +400 @@
 
         /* Clear any pending APIC interrupt action flag. */
-        s->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(s->CTX_SUFF(pDevIns));
-        s->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, false);
+        dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns));
+        dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, false);
     }
 }
@@ -448 +470 @@
 PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    APICState *s = getLAPIC(dev);
     Log(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
     return s->apicbase;
@@ -455 +478 @@
 PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    APICState *s = getLAPIC(dev);
     LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, (val & 0x0f) << 4));
-    apic_update_tpr(s, (val & 0x0f) << 4);
+    apic_update_tpr(dev, s, (val & 0x0f) << 4);
 }
 
 PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    APICState *s = getLAPIC(dev);
     Log2(("apicGetTPR: returns %#x\n", s->tpr >> 4));
     return s->tpr >> 4;
@@ -475 +500 @@
                                            uint8_t u8TriggerMode)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    APICState *s = getLAPIC(dev);
     LogFlow(("apicBusDeliverCallback: s=%p pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
              s, pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
-    apic_bus_deliver(s, apic_get_delivery_bitmask(s, u8Dest, u8DestMode),
+    apic_bus_deliver(dev, s, apic_get_delivery_bitmask(s, u8Dest, u8DestMode),
                      u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
 }
@@ -533 +559 @@
 
 /* signal the CPU if an irq is pending */
-static bool apic_update_irq(APICState *s)
+static bool apic_update_irq(APICDeviceInfo *dev, APICState* s)
 {
     int irrv, ppr;
@@ -540 +566 @@
     {
         /* Clear any pending APIC interrupt action flag. */
-        s->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(s->CTX_SUFF(pDevIns));
+        dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns));
         return false;
     }
@@ -555 +581 @@
     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 #else
-    s->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(s->CTX_SUFF(pDevIns));
+    dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns));
     return true;
 #endif
@@ -566 +592 @@
 {
     int irrv, ppr;
-
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
-    if (!s)
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    if (!dev)
         return false;
+    APICState *s = getLAPIC(dev);
 
     irrv = get_highest_priority_int(s->irr);
@@ -582 +608 @@
 }
 
-static void apic_update_tpr(APICState *s, uint32_t val)
+static void apic_update_tpr(APICDeviceInfo *dev, APICState* s, uint32_t val)
 {
     bool fIrqIsActive = false;
     bool fIrqWasActive = false;
 
-    fIrqWasActive = apic_update_irq(s);
+    fIrqWasActive = apic_update_irq(dev, s);
     s->tpr        = val;
-    fIrqIsActive  = apic_update_irq(s);
+    fIrqIsActive  = apic_update_irq(dev, s);
 
     /* If an interrupt is pending and now masked, then clear the FF flag. */
@@ -595 +621 @@
     {
         Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
-        STAM_COUNTER_INC(&s->StatClearedActiveIrq);
-        s->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(s->CTX_SUFF(pDevIns));
-    }
-}
-#endif
-
-static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
+        STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
+        dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns));
+    }
+}
+#endif
+
+static void apic_set_irq(APICDeviceInfo *dev,  APICState* s, int vector_num, int trigger_mode)
 {
     LogFlow(("apic_set_irq vector=%x, trigger_mode=%x\n", vector_num, trigger_mode));
@@ -609 +635 @@
     else
         reset_bit(s->tmr, vector_num);
-    apic_update_irq(s);
-}
-
-static void apic_eoi(APICState *s)
+    apic_update_irq(dev, s);
+}
+
+static void apic_eoi(APICDeviceInfo *dev, APICState* s)
 {
     int isrv;
@@ -622 +648 @@
     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
             set the remote IRR bit for level triggered interrupts. */
-    apic_update_irq(s);
+    apic_update_irq(dev, s);
 }
 
@@ -683 +709 @@
 }
 
-static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
+static void apic_deliver(APICDeviceInfo* dev, APICState *s, 
+                         uint8_t dest, uint8_t dest_mode,
                          uint8_t delivery_mode, uint8_t vector_num,
                          uint8_t polarity, uint8_t trigger_mode)
@@ -757 +784 @@
                      trigger_mode);
 #else /* VBOX */
-    apic_bus_deliver(s, deliver_bitmask, delivery_mode, vector_num, polarity,
+    apic_bus_deliver(dev, s, deliver_bitmask, delivery_mode, vector_num, polarity,
                      trigger_mode);
 #endif /* VBOX */
@@ -769 +796 @@
 PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    APICState *s = getLAPIC(dev);
 #endif /* VBOX */
     int intno;
@@ -796 +824 @@
     reset_bit(s->irr, intno);
     set_bit(s->isr, intno);
-    apic_update_irq(s);
+    apic_update_irq(dev, s);
     LogFlow(("apic_get_interrupt: returns %d\n", intno));
     return intno;
 }
 
-static uint32_t apic_get_current_count(APICState *s)
+static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s)
 {
     int64_t d;
@@ -809 +837 @@
         s->count_shift;
 #else /* VBOX */
-    d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
+    d = (TMTimerGet(dev->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
         s->count_shift;
 #endif /* VBOX */
@@ -824 +852 @@
 }
 
-static void apic_timer_update(APICState *s, int64_t current_time)
+static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
 {
     int64_t next_time, d;
@@ -842 +870 @@
         qemu_mod_timer(s->timer, next_time);
 #else
-        TMTimerSet(s->CTX_SUFF(pTimer), next_time);
+        TMTimerSet(dev->CTX_SUFF(pTimer), next_time);
 #endif
         s->next_time = next_time;
@@ -850 +878 @@
         qemu_del_timer(s->timer);
 #else
-        TMTimerStop(s->CTX_SUFF(pTimer));
+        TMTimerStop(dev->CTX_SUFF(pTimer));
 #endif
     }
@@ -863 +891 @@
 static DECLCALLBACK(void) apicTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
-    s->pApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    APICState *s = getLAPIC(dev);
+    dev->pApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
 #endif /* VBOX */
 
     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
         LogFlow(("apic_timer: trigger irq\n"));
-        apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
-    }
-    apic_timer_update(s, s->next_time);
-
-#ifdef VBOX
-    APIC_UNLOCK(s);
+        apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
+    }
+    apic_timer_update(dev, s, s->next_time);
+
+#ifdef VBOX
+    APIC_UNLOCK(dev);
 #endif
 }
@@ -884 +913 @@
     return 0;
 }
-
 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 {
@@ -906 +934 @@
     APICState *s;
 #else /* VBOX */
-static uint32_t apic_mem_readl(APICState *s, target_phys_addr_t addr)
+static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
 {
 #endif /* VBOX */
@@ -997 +1025 @@
         break;
     case 0x39:
-        val = apic_get_current_count(s);
+        val = apic_get_current_count(dev, s);
         break;
     case 0x3e:
@@ -1020 +1048 @@
     APICState *s;
 #else /* VBOX */
-static int apic_mem_writel(APICState *s, target_phys_addr_t addr, uint32_t val)
+static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
 {
 #endif /* VBOX */
@@ -1046 +1074 @@
     case 0x08:
 #ifdef VBOX
-        apic_update_tpr(s, val);
+        apic_update_tpr(dev, s, val);
 #else
         s->tpr = val;
@@ -1057 +1085 @@
         break;
     case 0x0b: /* EOI */
-        apic_eoi(s);
+        apic_eoi(dev, s);
         break;
     case 0x0d:
@@ -1067 +1095 @@
     case 0x0f:
         s->spurious_vec = val & 0x1ff;
-        apic_update_irq(s);
+        apic_update_irq(dev, s);
         break;
 #ifndef VBOX
@@ -1085 +1113 @@
     case 0x30:
         s->icr[0] = val;
-        apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
+        apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
@@ -1104 +1132 @@
                 apic_timer_update(s, qemu_get_clock(vm_clock));
 #else /* VBOX */
-                apic_timer_update(s, TMTimerGet(s->CTX_SUFF(pTimer)));
+                apic_timer_update(dev, s, TMTimerGet(dev->CTX_SUFF(pTimer)));
 #endif /* VBOX*/
         }
@@ -1113 +1141 @@
         s->initial_count_load_time = qemu_get_clock(vm_clock);
 #else /* VBOX */
-        s->initial_count_load_time = TMTimerGet(s->CTX_SUFF(pTimer));
+        s->initial_count_load_time = TMTimerGet(dev->CTX_SUFF(pTimer));
 #endif /* VBOX*/
-        apic_timer_update(s, s->initial_count_load_time);
+        apic_timer_update(dev, s, s->initial_count_load_time);
         break;
     case 0x39:
@@ -1212 +1240 @@
     return 0;
 }
-
+#ifndef VBOX
 static void apic_reset(void *opaque)
 {
     APICState *s = (APICState*)opaque;
-#ifdef VBOX
-    TMTimerStop(s->CTX_SUFF(pTimer));
-
-    /* malc, I've removed the initing duplicated in apic_init_ipi(). This
-     * arb_id was left over.. */
-    s->arb_id = 0;
-
-    /* Reset should re-enable the APIC. */
-    s->apicbase = 0xfee00000 | MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
-    s->pApicHlpR3->pfnChangeFeature(s->pDevInsR3, true);
-
-#endif /* VBOX */
     apic_init_ipi(s);
 }
+#endif
 
 #endif /* IN_RING3 */
@@ -1543 +1560 @@
 PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    APICState *s = getLAPIC(dev);
 
 #ifdef VBOX_WITH_SMP_GUESTS
@@ -1549 +1567 @@
 #endif
 
-    STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
+    STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
     switch (cb)
     {
@@ -1579 +1597 @@
 #endif
 #endif /* experimental */
-            APIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
-            *(uint32_t *)pv = apic_mem_readl(s, GCPhysAddr);
-            APIC_UNLOCK(s);
+            APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
+            *(uint32_t *)pv = apic_mem_readl(dev, s, GCPhysAddr);
+            APIC_UNLOCK(dev);
             break;
         }
@@ -1593 +1611 @@
 PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
-
-    STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    APICState *s = getLAPIC(dev);
+
+    STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
     switch (cb)
     {
@@ -1606 +1625 @@
         {
             int rc;
-            APIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
-            rc = apic_mem_writel(s, GCPhysAddr, *(uint32_t *)pv);
-            APIC_UNLOCK(s);
+            APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
+            rc = apic_mem_writel(dev, s, GCPhysAddr, *(uint32_t *)pv);
+            APIC_UNLOCK(dev);
             return rc;
         }
@@ -1626 +1645 @@
 static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    /* @todo: process all LAPICS */
+    APICState* s = FIRST_LAPIC(dev);
     apic_save(pSSMHandle, s);
-    return TMR3TimerSave(s->CTX_SUFF(pTimer), pSSMHandle);
+    /* @todo: save CPU count? */
+    return TMR3TimerSave(dev->CTX_SUFF(pTimer), pSSMHandle);
 }
 
@@ -1636 +1658 @@
 static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
+    APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    /* @todo: process all LAPICS */
+    APICState* s = FIRST_LAPIC(dev);
     if (apic_load(pSSMHandle, s, u32Version)) {
         AssertFailed();
         return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
     }
-    return TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSMHandle);
+     /* @todo: restore CPU count? */
+    return TMR3TimerLoad(dev->CTX_SUFF(pTimer), pSSMHandle);
 }
 
@@ -1649 +1674 @@
 static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
 {
-    APICState *s = PDMINS_2_DATA(pDevIns, APICState *);
-    s->pApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
-    apic_reset(s);
+    APICDeviceInfo* dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    dev->pApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
+
+    TMTimerStop(dev->CTX_SUFF(pTimer));
+
+     /* @todo: process all LAPICS? Or only one? */
+    APICState* s = FIRST_LAPIC(dev);
+
+    apic_init_ipi(s);
+    /* malc, I've removed the initing duplicated in apic_init_ipi(). This
+     * arb_id was left over.. */
+    s->arb_id = 0;
+    /* Reset should re-enable the APIC. */
+    s->apicbase = 0xfee00000 | MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
+    dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, true);
     /* Clear any pending APIC interrupt action flag. */
-    s->pApicHlpR3->pfnClearInterruptFF(pDevIns);
-    APIC_UNLOCK(s);
+    dev->pApicHlpR3->pfnClearInterruptFF(pDevIns);
+    APIC_UNLOCK(dev);
 }
 
@@ -1662 +1699 @@
 static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
 {
-    APICState *pThis = PDMINS_2_DATA(pDevIns, APICState *);
+    APICDeviceInfo *pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    
     pThis->pDevInsRC  = PDMDEVINS_2_RCPTR(pDevIns);
     pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
     pThis->pTimerRC   = TMTimerRCPtr(pThis->CTX_SUFF(pTimer));
+}
+
+DECLINLINE(void) initAPIC(APICState* apic, uint8_t id)
+{
+    int i;
+    ::memset(apic, 0, sizeof(*apic));
+    apic->apicbase  = UINT32_C(0xfee00000) | MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
+    for (i = 0; i < APIC_LVT_NB; i++)
+        apic->lvt[i] = 1 << 16; /* mask LVT */
+    apic->spurious_vec = 0xff;
+    apic->id = id;
 }
 
@@ -1673 +1722 @@
 static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
 {
-    APICState      *pThis = PDMINS_2_DATA(pDevIns, APICState *);
     PDMAPICREG      ApicReg;
     int             rc;
-    int             i;
+    uint32_t        i;
     bool            fIOAPIC;
     bool            fGCEnabled;
     bool            fR0Enabled;
-
-#ifndef VBOX_WITH_SMP_GUESTS
+    APICDeviceInfo  *pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
+    uint32_t        cCpus;
+
+    /* 
+     * Only single device instance.
+     */
     Assert(iInstance == 0);
-#else
-    LogRel(("[SMP] apicConstruct: %d %p\n", iInstance, pDevIns));
-#endif
 
     /*
      * Validate configuration.
      */
-    if (!CFGMR3AreValuesValid(pCfgHandle, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
+    if (!CFGMR3AreValuesValid(pCfgHandle, 
+                              "IOAPIC\0" 
+                              "GCEnabled\0" 
+                              "R0Enabled\0"
+                              "NumCPUs\0"))
         return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
 
@@ -1707 +1760 @@
         return PDMDEV_SET_ERROR(pDevIns, rc,
                                 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
-    Log(("APIC: fR0Enabled=%RTbool fGCEnabled=%RTbool fIOAPIC=%RTbool\n", fR0Enabled, fGCEnabled, fIOAPIC));
+    
+    rc = CFGMR3QueryU32Def(pCfgHandle, "NumCPUs", &cCpus, 1);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("Configuration error: Failed to query integer value \"NumCPUs\""));
+
+    Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIOAPIC=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIOAPIC));
 
     /*
@@ -1715 +1774 @@
     pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
     pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
-    pThis->apicbase  = UINT32_C(0xfee00000) | MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
-    for (i = 0; i < APIC_LVT_NB; i++)
-        pThis->lvt[i] = 1 << 16; /* mask LVT */
-    pThis->spurious_vec = 0xff;
-
+
+    PVM pVM = PDMDevHlpGetVM(pDevIns);
+    
+    /* 
+     * We are not freeing this memory, as it's automatically released when guest exits.
+     */
+    rc = MMHyperAlloc(pVM, cCpus*sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pThis->pLapicsR3);
+    if (RT_FAILURE(rc))
+        return VERR_NO_MEMORY;
+    pThis->pLapicsR0 = MMHyperR3ToR0(pVM, pThis->pLapicsR3);
+    pThis->pLapicsRC = MMHyperR3ToRC(pVM, pThis->pLapicsR3);
+
+    for (i = 0; i < cCpus; i++)
+    {
+        initAPIC((APICState*)pThis->pLapicsR3+i, i);
+    }
 
     /*
@@ -1797 +1867 @@
     /*
      * Register the MMIO range.
+     * @todo: may need to rethink for cases when different LAPICs mapped to different address
+     *        (see IA32_APIC_BASE_MSR)
      */
-    rc = PDMDevHlpMMIORegister(pDevIns, pThis->apicbase & ~0xfff, 0x1000, pThis,
+    rc = PDMDevHlpMMIORegister(pDevIns, FIRST_LAPIC(pThis)->apicbase & ~0xfff, 0x1000, pThis,
                                apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
     if (RT_FAILURE(rc))
@@ -1806 +1878 @@
         pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
 
-        rc = PDMDevHlpMMIORegisterGC(pDevIns, pThis->apicbase & ~0xfff, 0x1000, 0,
+        rc = PDMDevHlpMMIORegisterGC(pDevIns, FIRST_LAPIC(pThis)->apicbase & ~0xfff, 0x1000, 0,
                                      "apicMMIOWrite", "apicMMIORead", NULL);
         if (RT_FAILURE(rc))
@@ -1815 +1887 @@
         pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
 
-        rc = PDMDevHlpMMIORegisterR0(pDevIns, pThis->apicbase & ~0xfff, 0x1000, 0,
+        rc = PDMDevHlpMMIORegisterR0(pDevIns, FIRST_LAPIC(pThis)->apicbase & ~0xfff, 0x1000, 0,
                                      "apicMMIOWrite", "apicMMIORead", NULL);
         if (RT_FAILURE(rc))
@@ -1834 +1906 @@
      * Saved state.
      */
-    rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
+    rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 2 /* version */,
                               sizeof(*pThis), NULL, apicSaveExec, NULL, NULL, apicLoadExec, NULL);
     if (RT_FAILURE(rc))
@@ -1874 +1946 @@
     PDM_DEVREG_CLASS_PIC,
     /* cMaxInstances */
-#ifdef VBOX_WITH_SMP_GUESTS
-    8,
-#else
     1,
-#endif
     /* cbInstance */
     sizeof(APICState),

trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp

@@ -224 +224 @@
 //    CHECK_MEMBER_ALIGNMENT(PCNetState, StatMMIOReadGC, 8);
     CHECK_MEMBER_ALIGNMENT(DEVPIC, StatSetIrqGC, 8);
-    CHECK_MEMBER_ALIGNMENT(APICState, StatMMIOReadGC, 8);
+    CHECK_MEMBER_ALIGNMENT(APICDeviceInfo, StatMMIOReadGC, 8);
     CHECK_MEMBER_ALIGNMENT(IOAPICState, StatMMIOReadGC, 8);
     CHECK_MEMBER_ALIGNMENT(IOAPICState, StatMMIOReadGC, 8);

trunk/src/VBox/Devices/testcase/tstDeviceStructSizeGC.cpp

@@ -567 +567 @@
     GEN_CHECK_OFF(APICState, initial_count_load_time);
     GEN_CHECK_OFF(APICState, next_time);
-    GEN_CHECK_OFF(APICState, pDevInsR3);
-    GEN_CHECK_OFF(APICState, pApicHlpR3);
-    GEN_CHECK_OFF(APICState, pTimerR3);
-    GEN_CHECK_OFF(APICState, pDevInsR0);
-    GEN_CHECK_OFF(APICState, pApicHlpR0);
-    GEN_CHECK_OFF(APICState, pTimerR0);
-    GEN_CHECK_OFF(APICState, pDevInsRC);
-    GEN_CHECK_OFF(APICState, pApicHlpRC);
-    GEN_CHECK_OFF(APICState, pTimerRC);
-    GEN_CHECK_OFF(APICState, ulTPRPatchAttempts);
+
+    GEN_CHECK_SIZE(APICDeviceInfo);
+    GEN_CHECK_OFF(APICDeviceInfo, pDevInsR3);
+    GEN_CHECK_OFF(APICDeviceInfo, pApicHlpR3);
+    GEN_CHECK_OFF(APICDeviceInfo, pTimerR3);
+    GEN_CHECK_OFF(APICDeviceInfo, pDevInsR0);
+    GEN_CHECK_OFF(APICDeviceInfo, pApicHlpR0);
+    GEN_CHECK_OFF(APICDeviceInfo, pTimerR0);
+    GEN_CHECK_OFF(APICDeviceInfo, pDevInsRC);
+    GEN_CHECK_OFF(APICDeviceInfo, pApicHlpRC);
+    GEN_CHECK_OFF(APICDeviceInfo, pTimerRC);
+    GEN_CHECK_OFF(APICDeviceInfo, ulTPRPatchAttempts);
 #ifdef VBOX_WITH_STATISTICS
-    GEN_CHECK_OFF(APICState, StatMMIOReadGC);
-    GEN_CHECK_OFF(APICState, StatMMIOWriteHC);
+    GEN_CHECK_OFF(APICDeviceInfo, StatMMIOReadGC);
+    GEN_CHECK_OFF(APICDeviceInfo, StatMMIOWriteHC);
 #endif
 

trunk/src/VBox/Main/ConsoleImpl2.cpp

@@ -499 +499 @@
     /*
      * Advanced Programmable Interrupt Controller.
-     * SMP: Each CPU has a LAPIC (cross-calls).
+     * SMP: Each CPU has a LAPIC, but we have a single device representing all LAPICs states,
+     *      thus only single insert
      */
     rc = CFGMR3InsertNode(pDevices, "apic", &pDev);                                 RC_CHECK();
-    for (unsigned iCpu = 0; iCpu < cCpus; iCpu++)
-    {
-        rc = CFGMR3InsertNodeF(pDev, &pInst, "%u", iCpu);                           RC_CHECK();
-        rc = CFGMR3InsertInteger(pInst, "Trusted",          1);     /* boolean */   RC_CHECK();
-        rc = CFGMR3InsertNode(pInst,    "Config", &pCfg);                           RC_CHECK();
-        rc = CFGMR3InsertInteger(pCfg,  "IOAPIC", fIOAPIC);                         RC_CHECK();
-    }
-
+    rc = CFGMR3InsertNode(pDev, "0", &pInst);                                       RC_CHECK();
+    rc = CFGMR3InsertInteger(pInst, "Trusted",              1);     /* boolean */   RC_CHECK();
+    rc = CFGMR3InsertNode(pInst,    "Config", &pCfg);                               RC_CHECK();
+    rc = CFGMR3InsertInteger(pCfg,  "IOAPIC", fIOAPIC);                             RC_CHECK();
+    rc = CFGMR3InsertInteger(pCfg,  "NumCPUs", cCpus);                              RC_CHECK();
+
+    /* SMP: @todo: IOAPIC may be required for SMP configs */
     if (fIOAPIC)
     {