Index: /trunk/include/VBox/cpum.h
===================================================================
--- /trunk/include/VBox/cpum.h	(revision 12656)
+++ /trunk/include/VBox/cpum.h	(revision 12657)
@@ -350,6 +350,8 @@
     /** @} */
 
-    /* padding to get 32byte aligned size */
-////    uint32_t        padding[6];
+#if 0
+    /*& Padding to align the size on a 64 byte boundrary. */
+    uint32_t        padding[6];
+#endif
 } CPUMCTX;
 #pragma pack()
@@ -363,4 +365,5 @@
 /**
  * Selector hidden registers. (version 1.6)
+ * @todo move to CPUMInteral.h
  */
 typedef struct CPUMSELREGHID_VER1_6
@@ -378,4 +381,5 @@
 /**
  * CPU context. (Version 1.6)
+ * @todo move to CPUMInteral.h
  */
 #pragma pack(1)
@@ -582,5 +586,5 @@
 } CPUMCPUIDFEATURE;
 
-/*
+/**
  * CPU Vendor.
  */
@@ -688,4 +692,9 @@
  * @{  */
 
+
+CPUMDECL(bool)      CPUMIsGuestIn16BitCode(PVM pVM);
+CPUMDECL(bool)      CPUMIsGuestIn32BitCode(PVM pVM);
+CPUMDECL(CPUMCPUVENDOR) CPUMGetCPUVendor(PVM pVM);
+
 /**
  * Tests if the guest is running in real mode or not.
@@ -742,20 +751,4 @@
     return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
 }
-
-/**
- * Tests if the guest is running in 16 bits paged protected or not.
- *
- * @returns true if in paged protected mode, otherwise false.
- * @param   pVM     The VM handle.
- */
-CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
-
-/**
- * Tests if the guest is running in 32 bits paged protected or not.
- *
- * @returns true if in paged protected mode, otherwise false.
- * @param   pVM     The VM handle.
- */
-CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
 
 /**
@@ -789,15 +782,5 @@
 }
 
-/**
- * Gets the CPU vendor
- *
- * @returns CPU vendor
- * @param   pVM     The VM handle.
- */
-CPUMDECL(CPUMCPUVENDOR) CPUMGetCPUVendor(PVM pVM);
-
-
 /** @} */
-
 
 
@@ -868,125 +851,17 @@
 /** @} */
 
-CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
-
-/**
- * Sets or resets an alternative hypervisor context core.
- *
- * This is called when we get a hypervisor trap set switch the context
- * core with the trap frame on the stack. It is called again to reset
- * back to the default context core when resuming hypervisor execution.
- *
- * @param   pVM         The VM handle.
- * @param   pCtxCore    Pointer to the alternative context core or NULL
- *                      to go back to the default context core.
- */
-CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
-
-
-/**
- * Queries the pointer to the internal CPUMCTX structure
- *
- * @returns VBox status code.
- * @param   pVM         Handle to the virtual machine.
- * @param   ppCtx       Receives the CPUMCTX pointer when successful.
- */
-CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
-
-/**
- * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
- *
- * @returns VBox status code.
- * @param   pVM         Handle to the virtual machine.
- * @param   ppCtx       Receives the hyper CPUMCTX pointer when successful.
- */
-CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
-
-
-/**
- * Gets the pointer to the internal CPUMCTXCORE structure.
- * This is only for reading in order to save a few calls.
- *
- * @param   pVM         Handle to the virtual machine.
- */
+CPUMDECL(void)      CPUMPushHyper(PVM pVM, uint32_t u32);
+CPUMDECL(void)      CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
+CPUMDECL(int)       CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
+CPUMDECL(int)       CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
 CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
-
-/**
- * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
- * This is only for reading in order to save a few calls.
- *
- * @param   pVM         Handle to the virtual machine.
- */
 CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
-
-/**
- * Sets the guest context core registers.
- *
- * @param   pVM         Handle to the virtual machine.
- * @param   pCtxCore    The new context core values.
- */
-CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
-
-
-/**
- * Transforms the guest CPU state to raw-ring mode.
- *
- * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
- *
- * @returns VBox status. (recompiler failure)
- * @param   pVM         VM handle.
- * @param   pCtxCore    The context core (for trap usage).
- * @see     @ref pg_raw
- */
-CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
-
-/**
- * Transforms the guest CPU state from raw-ring mode to correct values.
- *
- * This function will change any selector registers with DPL=1 to DPL=0.
- *
- * @returns Adjusted rc.
- * @param   pVM         VM handle.
- * @param   rc          Raw mode return code
- * @param   pCtxCore    The context core (for trap usage).
- * @see     @ref pg_raw
- */
-CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
-
-/**
- * Gets the EFLAGS while we're in raw-mode.
- *
- * @returns The eflags.
- * @param   pVM         The VM handle.
- * @param   pCtxCore    The context core.
- */
-CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
-
-/**
- * Updates the EFLAGS while we're in raw-mode.
- *
- * @param   pVM         The VM handle.
- * @param   pCtxCore    The context core.
- * @param   eflags      The new EFLAGS value.
- */
-CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
-
-/**
- * Lazily sync in the FPU/XMM state
- *
- * This function will change any selector registers with DPL=1 to DPL=0.
- *
- * @returns VBox status code.
- * @param   pVM         VM handle.
- */
-CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
-
-
-/**
- * Restore host FPU/XMM state
- *
- * @returns VBox status code.
- * @param   pVM         VM handle.
- */
-CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
+CPUMDECL(void)      CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
+CPUMDECL(int)       CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
+CPUMDECL(int)       CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
+CPUMDECL(uint32_t)  CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
+CPUMDECL(void)      CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
+CPUMDECL(int)       CPUMHandleLazyFPU(PVM pVM);
+CPUMDECL(int)       CPUMRestoreHostFPUState(PVM pVM);
 
 /** @name Changed flags
@@ -1011,97 +886,16 @@
 /** @} */
 
-/**
- * Gets and resets the changed flags (CPUM_CHANGED_*).
- *
- * @returns The changed flags.
- * @param   pVM     VM handle.
- */
-CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
-
-/**
- * Sets the specified changed flags (CPUM_CHANGED_*).
- *
- * @param   pVM     The VM handle.
- */
-CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
-
-/**
- * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
- * @returns true if supported.
- * @returns false if not supported.
- * @param   pVM     The VM handle.
- */
-CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
-
-/**
- * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
- * @returns true if used.
- * @returns false if not used.
- * @param   pVM     The VM handle.
- */
-CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
-
-/**
- * Checks if the host OS uses the SYSCALL / SYSRET instructions.
- * @returns true if used.
- * @returns false if not used.
- * @param   pVM     The VM handle.
- */
-CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
-
-/**
- * Checks if we activated the FPU/XMM state of the guest OS
- * @returns true if we did.
- * @returns false if not.
- * @param   pVM     The VM handle.
- */
-CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
-
-/**
- * Deactivate the FPU/XMM state of the guest OS
- * @param   pVM     The VM handle.
- */
-CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
-
-/**
- * Checks if the guest debug state is active
- *
- * @returns boolean
- * @param   pVM         VM handle.
- */
-CPUMDECL(bool) CPUMIsGuestDebugStateActive(PVM pVM);
-
-/**
- * Mark the guest's debug state as inactive
- *
- * @returns boolean
- * @param   pVM         VM handle.
- */
-CPUMDECL(void) CPUMDeactivateGuestDebugtate(PVM pVM);
-
-
-/**
- * Checks if the hidden selector registers are valid
- * @returns true if they are.
- * @returns false if not.
- * @param   pVM     The VM handle.
- */
-CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
-
-/**
- * Checks if the hidden selector registers are valid
- * @param   pVM     The VM handle.
- * @param   fValid  Valid or not
- */
-CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
-
-/**
- * Get the current privilege level of the guest.
- *
- * @returns cpl
- * @param   pVM         VM Handle.
- * @param   pRegFrame   Trap register frame.
- */
-CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
+CPUMDECL(unsigned)  CPUMGetAndClearChangedFlagsREM(PVM pVM);
+CPUMDECL(void)      CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
+CPUMDECL(bool)      CPUMSupportsFXSR(PVM pVM);
+CPUMDECL(bool)      CPUMIsHostUsingSysEnter(PVM pVM);
+CPUMDECL(bool)      CPUMIsHostUsingSysCall(PVM pVM);
+CPUMDECL(bool)      CPUMIsGuestFPUStateActive(PVM pVM);
+CPUMDECL(void)      CPUMDeactivateGuestFPUState(PVM pVM);
+CPUMDECL(bool)      CPUMIsGuestDebugStateActive(PVM pVM);
+CPUMDECL(void)      CPUMDeactivateGuestDebugState(PVM pVM);
+CPUMDECL(bool)      CPUMAreHiddenSelRegsValid(PVM pVM);
+CPUMDECL(void)      CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
+CPUMDECL(uint32_t)  CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
 
 /**
@@ -1120,13 +914,5 @@
 } CPUMMODE;
 
-/**
- * Gets the current guest CPU mode.
- *
- * If paging mode is what you need, check out PGMGetGuestMode().
- *
- * @returns The CPU mode.
- * @param   pVM         The VM handle.
- */
-CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
+CPUMDECL(CPUMMODE)  CPUMGetGuestMode(PVM pVM);
 
 
@@ -1137,75 +923,16 @@
  */
 
-/**
- * Initializes the CPUM.
- *
- * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- */
-CPUMR3DECL(int) CPUMR3Init(PVM pVM);
-
-/**
- * Applies relocations to data and code managed by this
- * component. This function will be called at init and
- * whenever the VMM need to relocate it self inside the GC.
- *
- * The CPUM will update the addresses used by the switcher.
- *
- * @param   pVM     The VM.
- */
-CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
-
-/**
- * Terminates the CPUM.
- *
- * Termination means cleaning up and freeing all resources,
- * the VM it self is at this point powered off or suspended.
- *
- * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- */
-CPUMR3DECL(int) CPUMR3Term(PVM pVM);
-
-/**
- * Resets the CPU.
- *
- * @param   pVM         The VM handle.
- */
-CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
-
-/**
- * Queries the pointer to the internal CPUMCTX structure
- *
- * @returns VBox status code.
- * @param   pVM         Handle to the virtual machine.
- * @param   ppCtx       Receives the CPUMCTX GC pointer when successful.
- */
-CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx);
-
-
-#ifdef DEBUG
-/**
- * Debug helper - Saves guest context on raw mode entry (for fatal dump)
- *
- * @internal
- */
-CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
-#endif
-
-/**
- * API for controlling a few of the CPU features found in CR4.
- *
- * Currently only X86_CR4_TSD is accepted as input.
- *
- * @returns VBox status code.
- *
- * @param   pVM     The VM handle.
- * @param   fOr     The CR4 OR mask.
- * @param   fAnd    The CR4 AND mask.
- */
-CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
+CPUMR3DECL(int)     CPUMR3Init(PVM pVM);
+CPUMR3DECL(void)    CPUMR3Relocate(PVM pVM);
+CPUMR3DECL(int)     CPUMR3Term(PVM pVM);
+CPUMR3DECL(void)    CPUMR3Reset(PVM pVM);
+CPUMR3DECL(int)     CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx);
+# ifdef DEBUG
+CPUMR3DECL(void)    CPUMR3SaveEntryCtx(PVM pVM);
+# endif
+CPUMR3DECL(int)     CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
 
 /** @} */
-#endif
+#endif /* IN_RING3 */
 
 #ifdef IN_GC
@@ -1227,20 +954,10 @@
  *
  * This function does not return!
- *
- */
-DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler, uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
-
-/**
- * Performs an iret to V86 code
- * Assumes a trap stack frame has already been setup on the guest's stack!
- *
- * @param   pRegFrame   Original trap/interrupt context
- *
- * This function does not return!
- */
-CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
+ */
+DECLASM(void)       CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler, uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
+CPUMGCDECL(void)    CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
 
 /** @} */
-#endif
+#endif /* IN_GC */
 
 #ifdef IN_RING0
@@ -1249,56 +966,12 @@
  * @{
  */
-
-/**
- * Does Ring-0 CPUM initialization.
- *
- * This is mainly to check that the Host CPU mode is compatible
- * with VBox.
- *
- * @returns VBox status code.
- * @param   pVM         The VM to operate on.
- */
 CPUMR0DECL(int) CPUMR0Init(PVM pVM);
-
-/**
- * Lazily sync in the FPU/XMM state
- *
- * @returns VBox status code.
- * @param   pVM         VM handle.
- * @param   pCtx        CPU context
- */
 CPUMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PCPUMCTX pCtx);
-
-/**
- * Save guest FPU/XMM state
- *
- * @returns VBox status code.
- * @param   pVM         VM handle.
- * @param   pCtx        CPU context
- */
 CPUMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PCPUMCTX pCtx);
-
-/**
- * Save guest debug state
- *
- * @returns VBox status code.
- * @param   pVM         VM handle.
- * @param   pCtx        CPU context
- * @param   fDR6        Include DR6 or not
- */
 CPUMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6);
-
-/**
- * Lazily sync in the debug state
- *
- * @returns VBox status code.
- * @param   pVM         VM handle.
- * @param   pCtx        CPU context
- * @param   fDR6        Include DR6 or not
- */
 CPUMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6);
 
 /** @} */
-#endif
+#endif /* IN_RING0 */
 
 /** @} */
Index: /trunk/include/VBox/cpumdis.h
===================================================================
--- /trunk/include/VBox/cpumdis.h	(revision 12656)
+++ /trunk/include/VBox/cpumdis.h	(revision 12657)
@@ -44,49 +44,16 @@
 
 #ifdef IN_RING3
-
-/**
- * Disassemble an instruction and return the information in the provided structure.
- *
- * @returns VBox status code.
- * @param   pVM         VM Handle
- * @param   pCtx        CPU context
- * @param   GCPtrPC     Program counter (relative to CS) to disassemble from.
- * @param   pCpu        Disassembly state
- * @param   pszPrefix   String prefix for logging (debug only)
- *
- */
 CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix);
 
 # ifdef DEBUG
-/**
- * Disassemble an instruction and dump it to the log
- *
- * @returns VBox status code.
- * @param   pVM         VM Handle
- * @param   pCtx        CPU context
- * @param   pc          GC instruction pointer
- * @param   prefix      String prefix for logging
- *
- * @deprecated  Use DBGFR3DisasInstrCurrentLog().
- */
+/** @deprecated  Use DBGFR3DisasInstrCurrentLog().  */
 CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix);
-
-/**
- * Disassemble an instruction and dump it to the log
- *
- * @returns VBox status code.
- * @param   pVM         VM Handle
- * @param   pCtx        CPU context
- * @param   pc          GC instruction pointer
- * @param   prefix      String prefix for logging
- * @param   nrInstructions
- *
- * @deprecated  Create new DBGFR3Disas function to do this.
- */
+/** @deprecated  Create new DBGFR3Disas function to do this. */
 CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions);
-
 # else
-#  define CPUMR3DisasmInstr(pVM, pCtx, pc, prefix)
-#  define CPUMR3DisasmBlock(pVM, pCtx, pc, prefix, nrInstructions)
+/** @deprecated  Use DBGFR3DisasInstrCurrentLog(). */
+#  define CPUMR3DisasmInstr(pVM, pCtx, pc, prefix)  do {} while (0)
+/** @deprecated  Create new DBGFR3Disas function to do this. */
+#  define CPUMR3DisasmBlock(pVM, pCtx, pc, prefix, nrInstructions) do {} while (0)
 # endif
 
Index: /trunk/include/VBox/vm.h
===================================================================
--- /trunk/include/VBox/vm.h	(revision 12656)
+++ /trunk/include/VBox/vm.h	(revision 12657)
@@ -466,6 +466,8 @@
     STAMPROFILEADV      StatSwitcherTSS;
 
+/** @todo Realign everything on 64 byte boundraries to better match the
+ *        cache-line size. */
     /* padding - the unions must be aligned on 32 bytes boundraries. */
-    uint32_t            padding[HC_ARCH_BITS == 32 ? 4 : 6];
+    uint32_t            padding[HC_ARCH_BITS == 32 ? 4+8 : 6];
 
     /** CPUM part. */
@@ -635,8 +637,6 @@
     } rem;
 
-#if HC_ARCH_BITS == 64
     /** Padding for aligning the cpu array on a 64 byte boundrary. */
-    uint32_t u32Reserved2[HC_ARCH_BITS == 32 ? 0 : 8];
-#endif
+    uint32_t u32Reserved2[8];
 
     /**
Index: /trunk/include/VBox/vm.mac
===================================================================
--- /trunk/include/VBox/vm.mac	(revision 12656)
+++ /trunk/include/VBox/vm.mac	(revision 12657)
@@ -93,5 +93,5 @@
     .StatSwitcherTSS      resb STAMPROFILEADV_size
 
-    alignb 32
+    alignb 64
     .cpum                 resb 4416
     .vmm                  resb 1024
Index: /trunk/src/VBox/VMM/CPUM.cpp
===================================================================
--- /trunk/src/VBox/VMM/CPUM.cpp	(revision 12656)
+++ /trunk/src/VBox/VMM/CPUM.cpp	(revision 12657)
@@ -28,8 +28,8 @@
  * There are three CPU contexts, the most important one is the guest one (GC).
  * When running in raw-mode (RC) there is a special hyper context for the VMM
- * that floats around inside the guest address space. When running in raw-mode
- * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
- * context for saving and restoring registers accross world switches. This latter
- * is done in cooperation with the world switcher (@see pg_vmm).
+ * part that floats around inside the guest address space. When running in
+ * raw-mode, CPUM also maintains a host context for saving and restoring
+ * registers accross world switches. This latter is done in cooperation with the
+ * world switcher (@see pg_vmm).
  */
 
@@ -65,6 +65,7 @@
 *******************************************************************************/
 /** The saved state version. */
+#define CPUM_SAVED_STATE_VERSION            8
+/** The saved state version of 1.6, used for backwards compatability. */
 #define CPUM_SAVED_STATE_VERSION_VER1_6     6
-#define CPUM_SAVED_STATE_VERSION            8
 
 
@@ -85,4 +86,5 @@
 /** Pointer to a cpu info dump type. */
 typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
+
 
 /*******************************************************************************
@@ -119,6 +121,4 @@
      * Setup any fixed pointers and offsets.
      */
-    pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
-    pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
     pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
     pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
@@ -130,5 +130,4 @@
      * Check that the CPU supports the minimum features we require.
      */
-    /** @todo check the contract! */
     if (!ASMHasCpuId())
     {
@@ -510,4 +509,6 @@
      * Load CPUID overrides from configuration.
      */
+    /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
+     * Overloads the CPUID leaf values. */
     PCPUMCPUID  pCpuId = &pCPUM->aGuestCpuIdStd[0];
     uint32_t    cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
@@ -603,7 +604,6 @@
      * Switcher pointers.
      */
-    pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
-    pVM->cpum.s.pHyperCoreGC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
-    Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
+    pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
+    Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
 }
 
@@ -714,5 +714,5 @@
     pCtx->fpu.FCW                   = 0x37f;
 
-    /* Intel® 64 and IA-32 Architectures Software Developers Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
+    /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
     pCtx->fpu.MXCSR                 = 0x1F80;
 
@@ -765,4 +765,5 @@
 }
 
+
 /**
  * Load a version 1.6 CPUMCTX structure.
@@ -774,18 +775,20 @@
 static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
 {
-#define CPUMCTX16_LOADREG(regname)      pVM->cpum.s.Guest.regname = pCpumctx16->regname;
-
-#define CPUMCTX16_LOADDRXREG(regname)   pVM->cpum.s.Guest.dr[regname] = pCpumctx16->dr##regname;
-
-#define CPUMCTX16_LOADHIDREG(regname)                                                   \
-    pVM->cpum.s.Guest.regname##Hid.u64Base      = pCpumctx16->regname##Hid.u32Base;     \
-    pVM->cpum.s.Guest.regname##Hid.u32Limit     = pCpumctx16->regname##Hid.u32Limit;    \
-    pVM->cpum.s.Guest.regname##Hid.Attr         = pCpumctx16->regname##Hid.Attr;
-
-#define CPUMCTX16_LOADSEGREG(regname)                                                   \
-    pVM->cpum.s.Guest.regname                   = pCpumctx16->regname;                  \
-    CPUMCTX16_LOADHIDREG(regname);
-
-    pVM->cpum.s.Guest.fpu               = pCpumctx16->fpu;
+#define CPUMCTX16_LOADREG(RegName) \
+        pVM->cpum.s.Guest.RegName = pCpumctx16->RegName;
+
+#define CPUMCTX16_LOADDRXREG(RegName) \
+        pVM->cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
+
+#define CPUMCTX16_LOADHIDREG(RegName) \
+        pVM->cpum.s.Guest.RegName##Hid.u64Base  = pCpumctx16->RegName##Hid.u32Base; \
+        pVM->cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
+        pVM->cpum.s.Guest.RegName##Hid.Attr     = pCpumctx16->RegName##Hid.Attr;
+
+#define CPUMCTX16_LOADSEGREG(RegName) \
+        pVM->cpum.s.Guest.RegName = pCpumctx16->RegName; \
+        CPUMCTX16_LOADHIDREG(RegName);
+
+    pVM->cpum.s.Guest.fpu = pCpumctx16->fpu;
 
     CPUMCTX16_LOADREG(rax);
@@ -851,8 +854,10 @@
     CPUMCTX16_LOADHIDREG(tr);
 
+#undef CPUMCTX16_LOADSEGREG
 #undef CPUMCTX16_LOADHIDREG
-#undef CPUMCTX16_LOADSEGREG
+#undef CPUMCTX16_LOADDRXREG
 #undef CPUMCTX16_LOADREG
 }
+
 
 /**
@@ -977,5 +982,5 @@
      * Format the flags.
      */
-    static struct
+    static const struct
     {
         const char *pszSet; const char *pszClear; uint32_t fFlag;
@@ -1039,5 +1044,4 @@
         case CPUMDUMPTYPE_TERSE:
             if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
-            {
                 pHlp->pfnPrintf(pHlp,
                     "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
@@ -1053,5 +1057,4 @@
                     pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
                     pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
-            }
             else
                 pHlp->pfnPrintf(pHlp,
@@ -1067,5 +1070,4 @@
         case CPUMDUMPTYPE_DEFAULT:
             if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
-            {
                 pHlp->pfnPrintf(pHlp,
                     "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
@@ -1085,5 +1087,4 @@
                     pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
                     pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
-            }
             else
                 pHlp->pfnPrintf(pHlp,
@@ -1103,5 +1104,4 @@
         case CPUMDUMPTYPE_VERBOSE:
             if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
-            {
                 pHlp->pfnPrintf(pHlp,
                     "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
@@ -1141,5 +1141,4 @@
                     pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
                     pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
-            }
             else
                 pHlp->pfnPrintf(pHlp,
@@ -1181,5 +1180,4 @@
                 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
 
-
             pHlp->pfnPrintf(pHlp,
                 "MSR:\n"
@@ -1198,5 +1196,4 @@
                 pszPrefix, pCtx->msrSFMASK,
                 pszPrefix, pCtx->msrKERNELGSBASE);
-
             break;
     }
@@ -1276,4 +1273,5 @@
     cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
 }
+
 
 /**
@@ -2260,13 +2258,13 @@
  * @param   pc          GC instruction pointer
  * @param   prefix      String prefix for logging
+ *
  * @deprecated  Use DBGFR3DisasInstrCurrentLog().
- *
  */
 CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
 {
-    DISCPUSTATE cpu;
-
-    CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
-}
+    DISCPUSTATE Cpu;
+    CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, prefix);
+}
+
 
 /**
@@ -2280,8 +2278,9 @@
  * @param   nrInstructions
  *
+ * @deprecated  Create new DBGFR3Disas function to do this.
  */
 CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
 {
-    for(int i=0;i<nrInstructions;i++)
+    for (int i = 0; i < nrInstructions; i++)
     {
         DISCPUSTATE cpu;
@@ -2292,18 +2291,16 @@
 }
 
+
+/**
+ * Debug helper - Saves guest context on raw mode entry (for fatal dump)
+ *
+ * @internal
+ */
+CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
+{
+    pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
+}
+
 #endif /* DEBUG */
-
-#ifdef DEBUG
-/**
- * Debug helper - Saves guest context on raw mode entry (for fatal dump)
- *
- * @internal
- */
-CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
-{
-    pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
-}
-#endif /* DEBUG */
-
 
 /**
Index: /trunk/src/VBox/VMM/CPUMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/CPUMInternal.h	(revision 12656)
+++ /trunk/src/VBox/VMM/CPUMInternal.h	(revision 12657)
@@ -85,5 +85,5 @@
 
 /**
- * The save host CPU state.
+ * The saved host CPU state.
  *
  * @remark  The special VBOX_WITH_HYBIRD_32BIT_KERNEL checks here are for the 10.4.x series
@@ -189,6 +189,6 @@
     CPUMSYSENTER    SysEnter;
 
-    /* padding to get 32byte aligned size */
-    uint8_t         auPadding[24];
+    /* padding to get 64byte aligned size */
+    uint8_t         auPadding[24+32];
 
 #elif HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
@@ -236,7 +236,7 @@
     /* padding to get 32byte aligned size */
 # ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
-    uint8_t         auPadding[16];
+    uint8_t         auPadding[16+32];
 # else
-    uint8_t         auPadding[8];
+    uint8_t         auPadding[8+32];
 # endif
 
@@ -244,13 +244,7 @@
 # error HC_ARCH_BITS not defined
 #endif
-} CPUMHOSTCTX, *PCPUMHOSTCTX;
-
-
-/**
- * Converts a CPUM pointer into a VM pointer.
- * @returns Pointer to the VM structure the CPUM is part of.
- * @param   pCPUM   Pointer to CPUM instance data.
- */
-#define CPUM2VM(pCPUM)  ( (PVM)((char*)pCPUM - pCPUM->offVM) )
+} CPUMHOSTCTX;
+/** Pointer to the saved host CPU state. */
+typedef CPUMHOSTCTX *PCPUMHOSTCTX;
 
 
@@ -258,34 +252,23 @@
  * CPUM Data (part of VM)
  */
-#pragma pack(1)
 typedef struct CPUM
 {
-    /** Offset to the VM structure. */
-    RTUINT          offVM;
-    /** Pointer to CPU structure in GC. */
-    RCPTRTYPE(struct CPUM *) pCPUMGC;
-    /** Pointer to CPU structure in HC. */
-    R3R0PTRTYPE(struct CPUM *) pCPUMHC;
-
-    /** Force 32byte alignment of the next member. */
-    uint32_t        padding[4 + (HC_ARCH_BITS == 32)];
-
     /**
      * Saved host context. Only valid while inside GC.
-     * Must be aligned on 16 byte boundrary.
-     */
-    CPUMHOSTCTX     Host;
+     * Aligned on a 64-byte boundrary.
+     */
+    CPUMHOSTCTX             Host;
 
     /**
      * Hypervisor context.
-     * Must be aligned on 16 byte boundrary.
-     */
-    CPUMCTX         Hyper;
+     * Aligned on a 64-byte boundrary.
+     */
+    CPUMCTX                 Hyper;
 
     /**
      * Guest context.
-     * Must be aligned on 16 byte boundrary.
-     */
-    CPUMCTX         Guest;
+     * Aligned on a 64-byte boundrary.
+     */
+    CPUMCTX                 Guest;
 
 
@@ -294,11 +277,11 @@
     /** Pointer to the current hypervisor core context - R3Ptr. */
     R0PTRTYPE(PCPUMCTXCORE) pHyperCoreR0;
-    /** Pointer to the current hypervisor core context - GCPtr. */
-    RCPTRTYPE(PCPUMCTXCORE) pHyperCoreGC;
+    /** Pointer to the current hypervisor core context - RCPtr. */
+    RCPTRTYPE(PCPUMCTXCORE) pHyperCoreRC;
 
     /** Use flags.
      * These flags indicates both what is to be used and what have been used.
      */
-    uint32_t        fUseFlags;
+    uint32_t                fUseFlags;
 
     /** Changed flags.
@@ -307,10 +290,10 @@
      * See the CPUM_CHANGED_* defines for what we keep track of.
      */
-    uint32_t        fChanged;
+    uint32_t                fChanged;
 
     /** Hidden selector registers state.
      *  Valid (hw accelerated raw mode) or not (normal raw mode)
      */
-    uint32_t        fValidHiddenSelRegs;
+    uint32_t                fValidHiddenSelRegs;
 
     /** Host CPU Features - ECX */
@@ -321,13 +304,13 @@
         /** ecx part */
         X86CPUIDFEATECX     ecx;
-    }   CPUFeatures;
+    } CPUFeatures;
     /** Host extended CPU features. */
     struct
     {
         /** edx part */
-        uint32_t     edx;
+        uint32_t            edx;
         /** ecx part */
-        uint32_t     ecx;
-    }   CPUFeaturesExt;
+        uint32_t            ecx;
+    } CPUFeaturesExt;
 
     /* CPU manufacturer. */
@@ -337,6 +320,6 @@
     struct
     {
-        uint32_t AndMask;
-        uint32_t OrMask;
+        uint32_t            AndMask;
+        uint32_t            OrMask;
     } CR4;
 
@@ -354,15 +337,15 @@
     CPUMCPUID               GuestCpuIdDef;
 
+    /** Align the next member, and thereby the structure, on a 64-byte boundrary. */
+    uint8_t                 abPadding2[HC_ARCH_BITS == 32 ? 56 : 44];
+
     /**
      * Guest context on raw mode entry.
-     * This a debug feature.
-     */
-    CPUMCTX         GuestEntry;
-} CPUM, *PCPUM;
-#pragma pack()
-
-#ifdef IN_RING3
-
-#endif
+     * This a debug feature, see CPUMR3SaveEntryCtx.
+     */
+    CPUMCTX                 GuestEntry;
+} CPUM;
+/** Pointer to the CPUM instance data residing in the shared VM structure. */
+typedef CPUM *PCPUM;
 
 __BEGIN_DECLS
@@ -384,2 +367,3 @@
 
 #endif
+
Index: /trunk/src/VBox/VMM/CPUMInternal.mac
===================================================================
--- /trunk/src/VBox/VMM/CPUMInternal.mac	(revision 12656)
+++ /trunk/src/VBox/VMM/CPUMInternal.mac	(revision 12657)
@@ -1,5 +1,5 @@
 ; $Id$
 ;; @file
-; CPUM - Internal header file.
+; CPUM - Internal header file (asm).
 ;
 
@@ -37,7 +37,7 @@
 %define CPUM_HANDLER_CTXCORE_IN_EBP     RT_BIT(31)
 
-%define VMMGCRET_USED_FPU       040000000h
-
-%define FPUSTATE_SIZE           512
+%define VMMGCRET_USED_FPU               040000000h
+
+%define FPUSTATE_SIZE                   512
 
 ;; if anyone figures how to do %if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL) in
@@ -50,13 +50,7 @@
 
 struc CPUM
-    .offVM          resd           1
-    .pCPUMGC        RTGCPTR32_RES  1          ; Guest Context pointer
-    .pCPUMHC        RTHCPTR_RES    1          ; Host Context pointer
-
-
     ;
     ; Host context state
     ;
-    alignb 32
     .Host.fpu            resb    FPUSTATE_SIZE
 
@@ -169,7 +163,6 @@
     ;
     ; Hypervisor Context.
-    ; (Identical to .Host.*)
-    ;
-    alignb 32                           ; the padding
+    ;
+    alignb 64                           ; the padding
     .Hyper.fpu            resb    FPUSTATE_SIZE
 
@@ -266,14 +259,10 @@
     .Hyper.trHid.Attr         resd    1
 
-    ; padding
-;;;;    .Hyper.padding            resd    6
-
-
 
     ;
     ; Guest context state
-    ; (Identical to the two above chunks)
-    ;
-    alignb 32
+    ; (Identical to the .Hyper chunk above.)
+    ;
+    alignb 64
     .Guest.fpu            resb    FPUSTATE_SIZE
 
@@ -370,17 +359,13 @@
     .Guest.trHid.Attr         resd    1
 
-    ; padding
-;;;;    .Guest.padding            resd    6
-
-
 
     ;
     ; Other stuff.
     ;
-    alignb 32
+    alignb 64
     ; hypervisor core context.
     .pHyperCoreR3         RTR3PTR_RES   1
     .pHyperCoreR0         RTR0PTR_RES   1
-    .pHyperCoreGC         RTGCPTR32_RES 1
+    .pHyperCoreRC         RTRCPTR_RES   1
     ;...
     .fUseFlags            resd    1
@@ -415,7 +400,7 @@
     .GuestCpuIdDef        resb    16
 
+    alignb 64
     ; CPUMCTX debug stuff...
     .GuestEntry           resb   1024
-
 endstruc
 
Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm	(revision 12656)
+++ /trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm	(revision 12657)
@@ -266,4 +266,5 @@
 ENDPROC     CPUMLoadFPUAsm
 
+
 ;;
 ; Restores the guest's FPU/XMM state
@@ -285,4 +286,5 @@
     ret
 ENDPROC CPUMSaveFPUAsm
+
 
 ;;
@@ -310,9 +312,9 @@
     movdqa  xmm6, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*6]
     movdqa  xmm7, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*7]
-    
+
 %ifdef RT_ARCH_AMD64
     test qword [xDX + CPUMCTX.msrEFER], MSR_K6_EFER_LMA
     jz CPUMLoadXMMAsm_done
-    
+
     movdqa  xmm8, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*8]
     movdqa  xmm9, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*9]
@@ -354,5 +356,5 @@
     movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*6], xmm6
     movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*7], xmm7
-    
+
 %ifdef RT_ARCH_AMD64
     test qword [xDX + CPUMCTX.msrEFER], MSR_K6_EFER_LMA
@@ -367,5 +369,5 @@
     movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*14], xmm14
     movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*15], xmm15
-    
+
 CPUMSaveXMMAsm_done:
 %endif
@@ -396,4 +398,5 @@
 ENDPROC   CPUMSetFCW
 
+
 ;;
 ; Get the FPU control word
@@ -408,5 +411,5 @@
 
 ;;
-; Set the MXCSR; 
+; Set the MXCSR;
 ;
 ; @param  u32MXCSR    x86:[esp+4] GCC:rdi MSC:rcx     New MXCSR
@@ -428,4 +431,5 @@
 ENDPROC   CPUMSetMXCSR
 
+
 ;;
 ; Get the MXCSR
Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp	(revision 12656)
+++ /trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp	(revision 12657)
@@ -1,5 +1,5 @@
 /* $Id$ */
 /** @file
- * CPUM - CPU Monitor(/Manager) - Gets and Sets.
+ * CPUM - CPU Monitor(/Manager) - Getters and Setters.
  */
 
@@ -38,5 +38,4 @@
 
 
-
 /** Disable stack frame pointer generation here. */
 #if defined(_MSC_VER) && !defined(DEBUG)
@@ -58,5 +57,5 @@
 CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore)
 {
-    LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVM->cpum.s.CTXALLSUFF(pHyperCore), pCtxCore));
+    LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVM->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
     if (!pCtxCore)
     {
@@ -64,5 +63,5 @@
         pVM->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
         pVM->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
-        pVM->cpum.s.pHyperCoreGC = (RCPTRTYPE(PCPUMCTXCORE))VM_GUEST_ADDR(pVM, pCtxCore);
+        pVM->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_GUEST_ADDR(pVM, pCtxCore);
     }
     else
@@ -70,5 +69,5 @@
         pVM->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
         pVM->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
-        pVM->cpum.s.pHyperCoreGC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
+        pVM->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
     }
 }
@@ -83,5 +82,5 @@
 CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore);
+    return pVM->cpum.s.CTX_SUFF(pHyperCore);
 }
 
@@ -105,4 +104,5 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit)
 {
@@ -112,4 +112,5 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit)
 {
@@ -119,4 +120,5 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3)
 {
@@ -124,49 +126,59 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->cs = SelCS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->ds = SelDS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelES)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->es = SelES;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
+}
+
 
 CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelFS)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->fs = SelFS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelGS)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->gs = SelGS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->ss = SelSS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->esp = u32ESP;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
+}
+
 
 CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->eflags.u32 = Efl;
-    return VINF_SUCCESS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
+    return VINF_SUCCESS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->eip = u32EIP;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
+}
+
 
 CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR)
@@ -175,8 +187,10 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR)
 {
     pVM->cpum.s.Hyper.ldtr = SelLDTR;
 }
+
 
 CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0)
@@ -186,4 +200,5 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1)
 {
@@ -192,4 +207,5 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2)
 {
@@ -198,4 +214,5 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3)
 {
@@ -204,4 +221,5 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6)
 {
@@ -210,4 +228,5 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7)
 {
@@ -219,110 +238,103 @@
 CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->cs;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->cs;
+}
+
 
 CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ds;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ds;
+}
+
 
 CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->es;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->es;
+}
+
 
 CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->fs;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->fs;
+}
+
 
 CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->gs;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->gs;
+}
+
 
 CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ss;
-}
-
-#if 0 /* these are not correct. */
-
-CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM)
-{
-    return pVM->cpum.s.Hyper.cr0;
-}
-
-CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM)
-{
-    return pVM->cpum.s.Hyper.cr2;
-}
-
-CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM)
-{
-    return pVM->cpum.s.Hyper.cr3;
-}
-
-CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM)
-{
-    return pVM->cpum.s.Hyper.cr4;
-}
-
-#endif /* not correct */
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ss;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eax;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->eax;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ebx;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ebx;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ecx;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ecx;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->edx;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->edx;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->esi;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->esi;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->edi;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->edi;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ebp;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ebp;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->esp;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->esp;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eflags.u32;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eip;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->eip;
+}
+
 
 CPUMDECL(uint64_t) CPUMGetHyperRIP(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->rip;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->rip;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit)
@@ -333,4 +345,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit)
 {
@@ -340,4 +353,5 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM)
 {
@@ -345,4 +359,5 @@
 }
 
+
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM)
 {
@@ -350,4 +365,5 @@
 }
 
+
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM)
 {
@@ -355,4 +371,5 @@
 }
 
+
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM)
 {
@@ -360,4 +377,5 @@
 }
 
+
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM)
 {
@@ -365,8 +383,10 @@
 }
 
+
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM)
 {
     return pVM->cpum.s.Hyper.dr[6];
 }
+
 
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM)
@@ -396,5 +416,5 @@
 CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore)
 {
-    /** @todo #1410 requires selectors to be checked. */
+    /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
 
     PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVM->cpum.s.Guest);
@@ -511,5 +531,5 @@
                 ASMSetCR0(HyperCR0);
             }
-#ifdef VBOX_STRICT
+# ifdef VBOX_STRICT
             else
             {
@@ -518,5 +538,5 @@
                 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVM->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
             }
-#endif
+# endif
         }
         else
@@ -536,5 +556,5 @@
         }
     }
-#endif
+#endif /* IN_GC */
 
     /*
@@ -551,4 +571,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint64_t cr2)
 {
@@ -556,4 +577,5 @@
     return VINF_SUCCESS;
 }
+
 
 CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint64_t cr3)
@@ -563,4 +585,5 @@
     return VINF_SUCCESS;
 }
+
 
 CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint64_t cr4)
@@ -576,4 +599,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags)
 {
@@ -582,4 +606,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip)
 {
@@ -588,4 +613,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax)
 {
@@ -594,4 +620,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx)
 {
@@ -600,4 +627,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx)
 {
@@ -606,4 +634,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx)
 {
@@ -612,4 +641,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp)
 {
@@ -618,4 +648,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp)
 {
@@ -624,4 +655,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi)
 {
@@ -630,4 +662,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi)
 {
@@ -636,4 +669,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss)
 {
@@ -642,4 +676,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs)
 {
@@ -648,4 +683,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds)
 {
@@ -654,4 +690,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es)
 {
@@ -660,4 +697,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs)
 {
@@ -666,4 +704,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs)
 {
@@ -672,4 +711,5 @@
 }
 
+
 CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val)
 {
@@ -677,57 +717,59 @@
 }
 
+
 CPUMDECL(uint64_t)  CPUMGetGuestMsr(PVM pVM, unsigned idMsr)
 {
-    uint64_t val = 0;
+    uint64_t u64 = 0;
 
     switch (idMsr)
     {
-    case MSR_IA32_CR_PAT:
-        val = pVM->cpum.s.Guest.msrPAT;
-        break;
-
-    case MSR_IA32_SYSENTER_CS:
-        val = pVM->cpum.s.Guest.SysEnter.cs;
-        break;
-
-    case MSR_IA32_SYSENTER_EIP:
-        val = pVM->cpum.s.Guest.SysEnter.eip;
-        break;
-
-    case MSR_IA32_SYSENTER_ESP:
-        val = pVM->cpum.s.Guest.SysEnter.esp;
-        break;
-
-    case MSR_K6_EFER:
-        val = pVM->cpum.s.Guest.msrEFER;
-        break;
-
-    case MSR_K8_SF_MASK:
-        val = pVM->cpum.s.Guest.msrSFMASK;
-        break;
-
-    case MSR_K6_STAR:
-        val = pVM->cpum.s.Guest.msrSTAR;
-        break;
-
-    case MSR_K8_LSTAR:
-        val = pVM->cpum.s.Guest.msrLSTAR;
-        break;
-
-    case MSR_K8_CSTAR:
-        val = pVM->cpum.s.Guest.msrCSTAR;
-        break;
-
-    case MSR_K8_KERNEL_GS_BASE:
-        val = pVM->cpum.s.Guest.msrKERNELGSBASE;
-        break;
-
-    /* fs & gs base skipped on purpose as the current context might not be up-to-date. */
-    default:
-        AssertFailed();
-        break;
+        case MSR_IA32_CR_PAT:
+            u64 = pVM->cpum.s.Guest.msrPAT;
+            break;
+
+        case MSR_IA32_SYSENTER_CS:
+            u64 = pVM->cpum.s.Guest.SysEnter.cs;
+            break;
+
+        case MSR_IA32_SYSENTER_EIP:
+            u64 = pVM->cpum.s.Guest.SysEnter.eip;
+            break;
+
+        case MSR_IA32_SYSENTER_ESP:
+            u64 = pVM->cpum.s.Guest.SysEnter.esp;
+            break;
+
+        case MSR_K6_EFER:
+            u64 = pVM->cpum.s.Guest.msrEFER;
+            break;
+
+        case MSR_K8_SF_MASK:
+            u64 = pVM->cpum.s.Guest.msrSFMASK;
+            break;
+
+        case MSR_K6_STAR:
+            u64 = pVM->cpum.s.Guest.msrSTAR;
+            break;
+
+        case MSR_K8_LSTAR:
+            u64 = pVM->cpum.s.Guest.msrLSTAR;
+            break;
+
+        case MSR_K8_CSTAR:
+            u64 = pVM->cpum.s.Guest.msrCSTAR;
+            break;
+
+        case MSR_K8_KERNEL_GS_BASE:
+            u64 = pVM->cpum.s.Guest.msrKERNELGSBASE;
+            break;
+
+        /* fs & gs base skipped on purpose as the current context might not be up-to-date. */
+        default:
+            AssertFailed();
+            break;
     }
-    return val;
-}
+    return u64;
+}
+
 
 CPUMDECL(RTGCPTR) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit)
@@ -738,4 +780,5 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM)
 {
@@ -743,4 +786,5 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM)
 {
@@ -748,4 +792,5 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM)
 {
@@ -753,4 +798,5 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM)
 {
@@ -758,4 +804,5 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM)
 {
@@ -763,4 +810,5 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM)
 {
@@ -768,4 +816,5 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM)
 {
@@ -773,4 +822,5 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM)
 {
@@ -778,4 +828,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestCR0(PVM pVM)
 {
@@ -783,4 +834,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestCR2(PVM pVM)
 {
@@ -788,4 +840,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestCR3(PVM pVM)
 {
@@ -793,4 +846,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestCR4(PVM pVM)
 {
@@ -798,4 +852,5 @@
 }
 
+
 CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR)
 {
@@ -803,4 +858,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM)
 {
@@ -808,4 +864,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestRIP(PVM pVM)
 {
@@ -813,4 +870,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM)
 {
@@ -818,4 +876,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM)
 {
@@ -823,4 +882,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM)
 {
@@ -828,4 +888,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM)
 {
@@ -833,4 +894,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM)
 {
@@ -838,4 +900,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM)
 {
@@ -843,4 +906,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM)
 {
@@ -848,4 +912,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM)
 {
@@ -853,4 +918,5 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM)
 {
@@ -858,4 +924,5 @@
 }
 
+
 CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM)
 {
@@ -863,5 +930,6 @@
 }
 
-//@todo: crx should be an array
+
+///@todo: crx should be an array
 CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, unsigned iReg, uint64_t *pValue)
 {
@@ -886,4 +954,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR0(PVM pVM)
 {
@@ -891,4 +960,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR1(PVM pVM)
 {
@@ -896,4 +966,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR2(PVM pVM)
 {
@@ -901,4 +972,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR3(PVM pVM)
 {
@@ -906,4 +978,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR6(PVM pVM)
 {
@@ -911,4 +984,5 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR7(PVM pVM)
 {
@@ -916,15 +990,21 @@
 }
 
+
 CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint64_t *pValue)
 {
     AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
+    /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
+    if (iReg == 4 || iReg == 5)
+        iReg += 2;
     *pValue = pVM->cpum.s.Guest.dr[iReg];
     return VINF_SUCCESS;
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM)
 {
     return pVM->cpum.s.Guest.msrEFER;
 }
+
 
 /**
@@ -957,4 +1037,5 @@
 }
 
+
 /**
  * Gets a pointer to the array of standard CPUID leafs.
@@ -971,4 +1052,5 @@
 }
 
+
 /**
  * Gets a pointer to the array of extended CPUID leafs.
@@ -982,6 +1064,7 @@
 CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM)
 {
-    return RCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
-}
+    return (RCPTRTYPE(PCCPUMCPUID))VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
+}
+
 
 /**
@@ -996,6 +1079,7 @@
 CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM)
 {
-    return RCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
-}
+    return (RCPTRTYPE(PCCPUMCPUID))VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
+}
+
 
 /**
@@ -1008,6 +1092,7 @@
 CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM)
 {
-    return RCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
-}
+    return (RCPTRTYPE(PCCPUMCPUID))VM_GUEST_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
+}
+
 
 /**
@@ -1023,4 +1108,5 @@
 }
 
+
 /**
  * Gets a number of extended CPUID leafs.
@@ -1035,4 +1121,5 @@
 }
 
+
 /**
  * Gets a number of centaur CPUID leafs.
@@ -1046,4 +1133,5 @@
     return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
 }
+
 
 /**
@@ -1196,4 +1284,5 @@
 }
 
+
 /**
  * Queries a CPUID feature bit.
@@ -1220,4 +1309,5 @@
     return false;
 }
+
 
 /**
@@ -1272,4 +1362,5 @@
 }
 
+
 /**
  * Gets the CPU vendor
@@ -1290,4 +1381,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, uint64_t uDr1)
 {
@@ -1296,4 +1388,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, uint64_t uDr2)
 {
@@ -1302,4 +1395,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, uint64_t uDr3)
 {
@@ -1308,4 +1402,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, uint64_t uDr6)
 {
@@ -1314,4 +1409,5 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, uint64_t uDr7)
 {
@@ -1320,7 +1416,11 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint64_t Value)
 {
     AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
+    /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
+    if (iReg == 4 || iReg == 5)
+        iReg += 2;
     pVM->cpum.s.Guest.dr[iReg] = Value;
     return CPUMRecalcHyperDRx(pVM);
@@ -1639,6 +1739,4 @@
 
 
-
-
 /**
  * Gets and resets the changed flags (CPUM_CHANGED_*).
@@ -1661,4 +1759,5 @@
 }
 
+
 /**
  * Sets the specified changed flags (CPUM_CHANGED_*).
@@ -1670,4 +1769,5 @@
     pVM->cpum.s.fChanged |= fChangedFlags;
 }
+
 
 /**
@@ -1706,6 +1806,6 @@
 }
 
-
 #ifndef IN_RING3
+
 /**
  * Lazily sync in the FPU/XMM state
@@ -1731,6 +1831,6 @@
     return CPUMRestoreHostFPUStateAsm(&pVM->cpum.s);
 }
+
 #endif /* !IN_RING3 */
-
 
 /**
@@ -1756,5 +1856,4 @@
 
 
-
 /**
  * Checks if the guest debug state is active
@@ -1768,4 +1867,5 @@
 }
 
+
 /**
  * Mark the guest's debug state as inactive
@@ -1774,5 +1874,5 @@
  * @param   pVM         VM handle.
  */
-CPUMDECL(void) CPUMDeactivateGuestDebugtate(PVM pVM)
+CPUMDECL(void) CPUMDeactivateGuestDebugState(PVM pVM)
 {
     pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
@@ -1820,5 +1920,6 @@
          * not affected by loading a conforming coding segment.
          *
-         * This only seems to apply to AMD-V; in the VT-x case we *do* need to look at SS. (ACP2 regression during install after a far call to ring 2)
+         * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
+         * at SS. (ACP2 regression during install after a far call to ring 2)
          */
         cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
@@ -1862,6 +1963,5 @@
     if (!(pVM->cpum.s.Guest.cr0 & X86_CR0_PE))
         enmMode = CPUMMODE_REAL;
-    else
-    if (!(pVM->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
+    else if (!(pVM->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
         enmMode = CPUMMODE_PROTECTED;
     else
@@ -1870,2 +1970,3 @@
     return enmMode;
 }
+
Index: /trunk/src/VBox/VMM/VMMAll/EMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 12656)
+++ /trunk/src/VBox/VMM/VMMAll/EMAll.cpp	(revision 12657)
@@ -298,7 +298,7 @@
     if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
         return rc;
-    /* 
-     * The page pool cache may end up here in some cases because it 
-     * flushed one of the shadow mappings used by the trapping 
+    /*
+     * The page pool cache may end up here in some cases because it
+     * flushed one of the shadow mappings used by the trapping
      * instruction and it either flushed the TLB or the CPU reused it.
      */
@@ -319,9 +319,9 @@
     if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
         return rc;
-    /* 
-     * The page pool cache may end up here in some cases because it 
-     * flushed one of the shadow mappings used by the trapping 
+    /*
+     * The page pool cache may end up here in some cases because it
+     * flushed one of the shadow mappings used by the trapping
      * instruction and it either flushed the TLB or the CPU reused it.
-     * We want to play safe here, verifying that we've got write 
+     * We want to play safe here, verifying that we've got write
      * access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
      */
@@ -331,5 +331,5 @@
     if (RT_FAILURE(rc))
         return rc;
-    if (    !(fFlags & X86_PTE_RW) 
+    if (    !(fFlags & X86_PTE_RW)
         &&  (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
         return VERR_ACCESS_DENIED;
@@ -351,10 +351,10 @@
 
 #if defined(VBOX_STRICT) || defined(LOG_ENABLED)
-/** 
+/**
  * Get the mnemonic for the disassembled instruction.
- *  
- * GC/R0 doesn't include the strings in the DIS tables because 
- * of limited space. 
- */ 
+ *
+ * GC/R0 doesn't include the strings in the DIS tables because
+ * of limited space.
+ */
 static const char *emGetMnemonic(PDISCPUSTATE pCpu)
 {
@@ -803,5 +803,5 @@
  * LOCK XOR/OR/AND Emulation.
  */
-static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, 
+static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
                                    uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
 {
@@ -1097,5 +1097,5 @@
  * LOCK BTR/C/S Emulation.
  */
-static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, 
+static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
                                   uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
 {
@@ -1141,6 +1141,6 @@
 #ifdef IN_GC
     Assert(TRPMHasTrap(pVM));
-    AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, 
-                    ("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault), 
+    AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault,
+                    ("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault),
                     VERR_EM_INTERPRETER);
 #endif
@@ -1157,5 +1157,5 @@
     if (RT_FAILURE(rc))
     {
-        Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n", 
+        Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n",
              emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
         return VERR_EM_INTERPRETER;
@@ -1395,6 +1395,6 @@
     }
     else
-    {    
-        if (!cTransfers) 
+    {
+        if (!cTransfers)
             return VINF_SUCCESS;
 
@@ -1517,5 +1517,5 @@
     else
         eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
-    
+
     LogFlow(("%s %VGv rax=%RX64 %RX64 ZF=%d\n", pszInstr, GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
 
@@ -2043,5 +2043,5 @@
         rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
     }
-    else 
+    else
     {
         uint32_t val32;
@@ -2059,5 +2059,5 @@
 #ifdef IN_GC
             /* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
-            if (    (val    & (X86_CR0_WP | X86_CR0_AM)) 
+            if (    (val    & (X86_CR0_WP | X86_CR0_AM))
                 !=  (oldval & (X86_CR0_WP | X86_CR0_AM)))
                 return VERR_EM_INTERPRETER;
@@ -2200,5 +2200,5 @@
         rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
     }
-    else 
+    else
     {
         uint32_t val32;
@@ -2207,9 +2207,9 @@
     }
 
-    if (VBOX_SUCCESS(rc))
-    {
-        /* @todo: we don't fail if illegal bits are set/cleared for e.g. dr7 */
+    if (RT_SUCCESS(rc))
+    {
+        /** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
         rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
-        if (VBOX_SUCCESS(rc))
+        if (RT_SUCCESS(rc))
             return rc;
         AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
Index: /trunk/src/VBox/VMM/VMMGC/CPUMGCA.asm
===================================================================
--- /trunk/src/VBox/VMM/VMMGC/CPUMGCA.asm	(revision 12656)
+++ /trunk/src/VBox/VMM/VMMGC/CPUMGCA.asm	(revision 12657)
@@ -1,6 +1,6 @@
 ; $Id$
 ;; @file
-;
 ; CPUM - Guest Context Assembly Routines.
+;
 
 ; Copyright (C) 2006-2007 Sun Microsystems, Inc.
@@ -187,6 +187,6 @@
     TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
     iret
-
 ENDPROC CPUMGCCallGuestTrapHandler
+
 
 ;;
@@ -195,7 +195,7 @@
 ;
 ; @param   pRegFrame   Original trap/interrupt context
-; 
+;
 ; This function does not return!
-; 
+;
 ;CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
 align 16
@@ -204,13 +204,13 @@
 
     ; construct iret stack frame
-    push    dword [ebp + CPUMCTXCORE.gs] 
-    push    dword [ebp + CPUMCTXCORE.fs] 
-    push    dword [ebp + CPUMCTXCORE.ds] 
-    push    dword [ebp + CPUMCTXCORE.es] 
-    push    dword [ebp + CPUMCTXCORE.ss] 
-    push    dword [ebp + CPUMCTXCORE.esp] 
-    push    dword [ebp + CPUMCTXCORE.eflags] 
-    push    dword [ebp + CPUMCTXCORE.cs] 
-    push    dword [ebp + CPUMCTXCORE.eip] 
+    push    dword [ebp + CPUMCTXCORE.gs]
+    push    dword [ebp + CPUMCTXCORE.fs]
+    push    dword [ebp + CPUMCTXCORE.ds]
+    push    dword [ebp + CPUMCTXCORE.es]
+    push    dword [ebp + CPUMCTXCORE.ss]
+    push    dword [ebp + CPUMCTXCORE.esp]
+    push    dword [ebp + CPUMCTXCORE.eflags]
+    push    dword [ebp + CPUMCTXCORE.cs]
+    push    dword [ebp + CPUMCTXCORE.eip]
 
     ;
@@ -235,4 +235,5 @@
     iret
 ENDPROC CPUMGCCallV86Code
+
 
 ;;
@@ -384,5 +385,2 @@
 ENDPROC     CPUMGCResumeGuestV86
 
-
-
-
Index: /trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp	(revision 12656)
+++ /trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp	(revision 12657)
@@ -36,5 +36,4 @@
 
 
-
 /**
  * Does Ring-0 CPUM initialization.
@@ -53,5 +52,5 @@
      * Check CR0 & CR4 flags.
      */
-    uint32_t    u32CR0 = ASMGetCR0();
+    uint32_t u32CR0 = ASMGetCR0();
     if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
     {
@@ -99,5 +98,5 @@
      * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
      */
-    uint32_t    u32DR7 = ASMGetDR7();
+    uint32_t u32DR7 = ASMGetDR7();
     if (u32DR7 & X86_DR7_ENABLED_MASK)
     {
@@ -155,12 +154,11 @@
      */
 
-    switch(pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
-    {
-    case X86_CR0_MP | X86_CR0_TS:
-    case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
-        return VINF_EM_RAW_GUEST_TRAP;
-
-    default:
-        break;
+    switch (pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
+    {
+        case X86_CR0_MP | X86_CR0_TS:
+        case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
+            return VINF_EM_RAW_GUEST_TRAP;
+        default:
+            break;
     }
 
@@ -172,7 +170,8 @@
     if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
     {
-        /* @todo Do we really need to read this every time?? The host could change this on the fly though. */
+        /** @todo Do we really need to read this every time?? The host could change this on the fly though.
+         *  bird: what about starting by skipping the ASMWrMsr below if we didn't
+         *        change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
         oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
-
         if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
         {
@@ -193,6 +192,9 @@
  	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
     ASMSetCR0(oldCR0);
-#else
-    /* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
+
+#else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
+
+    /*
+     * Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
      * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
      */
@@ -203,5 +205,6 @@
     CPUMLoadFPUAsm(pCtx);
 
-    /* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
+    /*
+     * The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
      *
      * MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
@@ -209,5 +212,5 @@
     if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
     {
-        /* @todo Do we really need to read this every time?? The host could change this on the fly though. */
+        /** @todo Do we really need to read this every time?? The host could change this on the fly though. */
         uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
 
@@ -219,5 +222,5 @@
         }
     }
-#endif
+#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
 
     pVM->cpum.s.fUseFlags |= CPUM_USED_FPU;
@@ -254,5 +257,5 @@
         ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost | MSR_K6_EFER_FFXSR);
 
-#else
+#else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
     CPUMSaveFPUAsm(pCtx);
     if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
@@ -261,5 +264,7 @@
         CPUMSaveXMMAsm(pCtx);
     }
-    /* Restore the original FPU control word and MXCSR.
+
+    /*
+     * Restore the original FPU control word and MXCSR.
      * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
      */
@@ -267,7 +272,7 @@
     if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
         CPUMSetMXCSR(pVM->cpum.s.Host.fpu.MXCSR);
-#endif
-
-    pVM->cpum.s.fUseFlags &= ~(CPUM_USED_FPU|CPUM_MANUAL_XMM_RESTORE);
+#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
+
+    pVM->cpum.s.fUseFlags &= ~(CPUM_USED_FPU | CPUM_MANUAL_XMM_RESTORE);
     return VINF_SUCCESS;
 }
@@ -294,5 +299,6 @@
         pCtx->dr[6] = ASMGetDR6();
 
-    /* Restore the host's debug state. DR0-3, DR6 and only then DR7! 
+    /*
+     * Restore the host's debug state. DR0-3, DR6 and only then DR7!
      * DR7 contains 0x400 right now.
      */
@@ -325,5 +331,5 @@
     pVM->cpum.s.Host.dr3 = ASMGetDR3();
     pVM->cpum.s.Host.dr6 = ASMGetDR6();
-    /* @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
+    /** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
     pVM->cpum.s.Host.dr7 = ASMGetDR7();
     /* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
@@ -341,2 +347,3 @@
     return VINF_SUCCESS;
 }
+
Index: /trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp	(revision 12656)
+++ /trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp	(revision 12657)
@@ -748,5 +748,5 @@
 
     /* Always load the guest's debug state on-demand. */
-    CPUMDeactivateGuestDebugtate(pVM);
+    CPUMDeactivateGuestDebugState(pVM);
 
     /* Always reload the host context and the guest's CR0 register. (!!!!) */
Index: /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp
===================================================================
--- /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp	(revision 12656)
+++ /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp	(revision 12657)
@@ -160,7 +160,8 @@
     }
     CHECK_MEMBER_ALIGNMENT(VM, trpm.s.aIdt, 16);
-    CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Host, 32);
-    CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Guest, 32);
-    CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Hyper, 32);
+    CHECK_MEMBER_ALIGNMENT(VM, cpum, 64);
+    CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Host, 64);
+    CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Guest, 64);
+    CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Hyper, 64);
     CHECK_MEMBER_ALIGNMENT(VM, vmm.s.CritSectVMLock, 8);
     CHECK_MEMBER_ALIGNMENT(VM, vmm.s.CallHostR0JmpBuf, 8);
@@ -180,5 +181,4 @@
     CHECK_MEMBER_ALIGNMENT(CPUMCTX, idtr, 4);
     CHECK_MEMBER_ALIGNMENT(CPUMCTX, SysEnter, 8);
-    CHECK_SIZE_ALIGNMENT(CPUMCTX, 32);
     CHECK_CPUMCTXCORE(eax);
     CHECK_CPUMCTXCORE(ebx);
@@ -220,4 +220,6 @@
     }
 #endif
+    CHECK_SIZE_ALIGNMENT(CPUMCTX, 64);
+    CHECK_SIZE_ALIGNMENT(CPUMHOSTCTX, 64);
 
     /* pdm */
