VirtualBox

Changeset 12688 in vbox for trunk/include


Ignore:
Timestamp:
Sep 24, 2008 2:22:18 PM (16 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
36993
Message:

#1865: EM - one pointer and statistics. Added a couple of more samples to the release statistics.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/em.h

    r12305 r12688  
    7878} EMSTATE;
    7979
    80 /*
    81  * Callback handlers for instruction emulation functions.
    82  */
    83 typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2_UINT32(void *pvParam1, uint64_t val2);
    84 typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM2(void *pvParam1, size_t val2);
    85 typedef DECLCALLBACK(uint32_t) PFN_EMULATE_PARAM3(void *pvParam1, uint64_t val2, size_t val3);
    86 typedef DECLCALLBACK(int)      FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
    87 typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
    88 typedef DECLCALLBACK(int)      FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
    89 typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
    90 
    91 /**
    92  * Get the current execution manager status.
    93  *
    94  * @returns Current status.
    95  */
    9680EMDECL(EMSTATE) EMGetState(PVM pVM);
     81
     82/** @name Callback handlers for instruction emulation functions.
     83 * These are placed here because IOM wants to use them as well.
     84 * @{
     85 */
     86typedef DECLCALLBACK(uint32_t)  FNEMULATEPARAM2UINT32(void *pvParam1, uint64_t val2);
     87typedef FNEMULATEPARAM2UINT32  *PFNEMULATEPARAM2UINT32;
     88typedef DECLCALLBACK(uint32_t)  FNEMULATEPARAM2(void *pvParam1, size_t val2);
     89typedef FNEMULATEPARAM2        *PFNEMULATEPARAM2;
     90typedef DECLCALLBACK(uint32_t)  FNEMULATEPARAM3(void *pvParam1, uint64_t val2, size_t val3);
     91typedef FNEMULATEPARAM3        *PFNEMULATEPARAM3;
     92typedef DECLCALLBACK(int)       FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
     93typedef FNEMULATELOCKPARAM2    *PFNEMULATELOCKPARAM2;
     94typedef DECLCALLBACK(int)       FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
     95typedef FNEMULATELOCKPARAM3    *PFNEMULATELOCKPARAM3;
     96/** @}  */
     97
    9798
    9899/**
    … …  
    114115#define EMIsRawRing0Enabled(pVM) ((pVM)->fRawR0Enabled)
    115116
    116 /**
    117  * Sets the PC for which interrupts should be inhibited.
    118  *
    119  * @param   pVM         The VM handle.
    120  * @param   PC          The PC.
    121  */
    122 EMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC);
    123 
    124 /**
    125  * Gets the PC for which interrupts should be inhibited.
    126  *
    127  * There are a few instructions which inhibits or delays interrupts
    128  * for the instruction following them. These instructions are:
    129  *      - STI
    130  *      - MOV SS, r/m16
    131  *      - POP SS
    132  *
    133  * @returns The PC for which interrupts should be inhibited.
    134  * @param   pVM         VM handle.
    135  *
    136  */
     117EMDECL(void)        EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC);
    137118EMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVM pVM);
    138 
    139 /**
    140  * Disassembles one instruction.
    141  *
    142  * @param   pVM             The VM handle.
    143  * @param   pCtxCore        The context core (used for both the mode and instruction).
    144  * @param   pCpu            Where to return the parsed instruction info.
    145  * @param   pcbInstr        Where to return the instruction size. (optional)
    146  */
    147 EMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr);
    148 
    149 /**
    150  * Disassembles one instruction.
    151  *
    152  * This is used by internally by the interpreter and by trap/access handlers.
    153  *
    154  * @param   pVM             The VM handle.
    155  * @param   GCPtrInstr      The flat address of the instruction.
    156  * @param   pCtxCore        The context core (used to determin the cpu mode).
    157  * @param   pCpu            Where to return the parsed instruction info.
    158  * @param   pcbInstr        Where to return the instruction size. (optional)
    159  */
    160 EMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
    161                                   PDISCPUSTATE pCpu, unsigned *pcbInstr);
    162 
    163 /**
    164  * Interprets the current instruction.
    165  *
    166  * @returns VBox status code.
    167  * @retval  VINF_*                  Scheduling instructions.
    168  * @retval  VERR_EM_INTERPRETER     Something we can't cope with.
    169  * @retval  VERR_*                  Fatal errors.
    170  *
    171  * @param   pVM         The VM handle.
    172  * @param   pRegFrame   The register frame.
    173  *                      Updates the EIP if an instruction was executed successfully.
    174  * @param   pvFault     The fault address (CR2).
    175  * @param   pcbSize     Size of the write (if applicable).
    176  *
    177  * @remark  Invalid opcode exceptions have a higher priority than GP (see Intel
    178  *          Architecture System Developers Manual, Vol 3, 5.5) so we don't need
    179  *          to worry about e.g. invalid modrm combinations (!)
    180  */
    181 EMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
    182 
    183 /**
    184  * Interprets the current instruction using the supplied DISCPUSTATE structure.
    185  *
    186  * EIP is *NOT* updated!
    187  *
    188  * @returns VBox status code.
    189  * @retval  VINF_*                  Scheduling instructions. When these are returned, it
    190  *                                  starts to get a bit tricky to know whether code was
    191  *                                  executed or not... We'll address this when it becomes a problem.
    192  * @retval  VERR_EM_INTERPRETER     Something we can't cope with.
    193  * @retval  VERR_*                  Fatal errors.
    194  *
    195  * @param   pVM         The VM handle.
    196  * @param   pCpu        The disassembler cpu state for the instruction to be interpreted.
    197  * @param   pRegFrame   The register frame. EIP is *NOT* changed!
    198  * @param   pvFault     The fault address (CR2).
    199  * @param   pcbSize     Size of the write (if applicable).
    200  *
    201  * @remark  Invalid opcode exceptions have a higher priority than GP (see Intel
    202  *          Architecture System Developers Manual, Vol 3, 5.5) so we don't need
    203  *          to worry about e.g. invalid modrm combinations (!)
    204  */
    205 EMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
    206 
    207 /**
    208  * Interpret CPUID given the parameters in the CPU context
    209  *
    210  * @returns VBox status code.
    211  * @param   pVM         The VM handle.
    212  * @param   pRegFrame   The register frame.
    213  *
    214  */
    215 EMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame);
    216 
    217 /**
    218  * Interpret RDTSC
    219  *
    220  * @returns VBox status code.
    221  * @param   pVM         The VM handle.
    222  * @param   pRegFrame   The register frame.
    223  *
    224  */
    225 EMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame);
    226 
    227 /**
    228  * Interpret INVLPG
    229  *
    230  * @returns VBox status code.
    231  * @param   pVM         The VM handle.
    232  * @param   pRegFrame   The register frame.
    233  * @param   pAddrGC     Operand address
    234  *
    235  */
    236 EMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
    237 
    238 /**
    239  * Interpret IRET (currently only to V86 code)
    240  *
    241  * @returns VBox status code.
    242  * @param   pVM         The VM handle.
    243  * @param   pRegFrame   The register frame.
    244  *
    245  */
    246 EMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame);
    247 
    248 /**
    249  * Interpret DRx write
    250  *
    251  * @returns VBox status code.
    252  * @param   pVM         The VM handle.
    253  * @param   pRegFrame   The register frame.
    254  * @param   DestRegDRx  DRx register index (USE_REG_DR*)
    255  * @param   SrcRegGen   General purpose register index (USE_REG_E**))
    256  *
    257  */
    258 EMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
    259 
    260 /**
    261  * Interpret DRx read
    262  *
    263  * @returns VBox status code.
    264  * @param   pVM         The VM handle.
    265  * @param   pRegFrame   The register frame.
    266  * @param   DestRegGen  General purpose register index (USE_REG_E**))
    267  * @param   SrcRegDRx   DRx register index (USE_REG_DR*)
    268  *
    269  */
    270 EMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
    271 
    272 /**
    273  * Interpret CRx write
    274  *
    275  * @returns VBox status code.
    276  * @param   pVM         The VM handle.
    277  * @param   pRegFrame   The register frame.
    278  * @param   DestRegCRx  DRx register index (USE_REG_CR*)
    279  * @param   SrcRegGen   General purpose register index (USE_REG_E**))
    280  *
    281  */
    282 EMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
    283 
    284 /**
    285  * Interpret CRx read
    286  *
    287  * @returns VBox status code.
    288  * @param   pVM         The VM handle.
    289  * @param   pRegFrame   The register frame.
    290  * @param   DestRegGen  General purpose register index (USE_REG_E**))
    291  * @param   SrcRegCRx   CRx register index (USE_REG_CR*)
    292  *
    293  */
    294 EMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
    295 
    296 /**
    297  * Interpret LMSW
    298  *
    299  * @returns VBox status code.
    300  * @param   pVM         The VM handle.
    301  * @param   u16Data     LMSW source data.
    302  */
    303 EMDECL(int) EMInterpretLMSW(PVM pVM, uint16_t u16Data);
    304 
    305 /**
    306  * Interpret CLTS
    307  *
    308  * @returns VBox status code.
    309  * @param   pVM         The VM handle.
    310  *
    311  */
    312 EMDECL(int) EMInterpretCLTS(PVM pVM);
    313 
    314 /**
    315  * Interpret a port I/O instruction.
    316  *
    317  * @returns VBox status code suitable for scheduling.
    318  * @param   pVM         The VM handle.
    319  * @param   pCtxCore    The context core. This will be updated on successful return.
    320  * @param   pCpu        The instruction to interpret.
    321  * @param   cbOp        The size of the instruction.
    322  * @remark  This may raise exceptions.
    323  */
    324 EMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp);
    325 
    326 /**
    327  * Flushes the REM translation blocks the next time we execute code there.
    328  *
    329  * @param   pVM         The VM handle.
    330  */
    331 EMDECL(void) EMFlushREMTBs(PVM pVM);
    332 
    333 EMDECL(uint32_t) EMEmulateCmp(uint32_t u32Param1, uint64_t u64Param2, size_t cb);
    334 EMDECL(uint32_t) EMEmulateAnd(void *pvParam1, uint64_t u64Param2, size_t cb);
    335 EMDECL(uint32_t) EMEmulateInc(void *pvParam1, size_t cb);
    336 EMDECL(uint32_t) EMEmulateDec(void *pvParam1, size_t cb);
    337 EMDECL(uint32_t) EMEmulateOr(void *pvParam1, uint64_t u64Param2, size_t cb);
    338 EMDECL(int)      EMEmulateLockOr(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
    339 EMDECL(uint32_t) EMEmulateXor(void *pvParam1, uint64_t u64Param2, size_t cb);
    340 EMDECL(uint32_t) EMEmulateAdd(void *pvParam1, uint64_t u64Param2, size_t cb);
    341 EMDECL(uint32_t) EMEmulateSub(void *pvParam1, uint64_t u64Param2, size_t cb);
    342 EMDECL(uint32_t) EMEmulateAdcWithCarrySet(void *pvParam1, uint64_t u64Param2, size_t cb);
    343 EMDECL(uint32_t) EMEmulateBtr(void *pvParam1, uint64_t u64Param2);
    344 EMDECL(int)      EMEmulateLockBtr(void *pvParam1, uint64_t u64Param2, RTGCUINTREG32 *pf);
    345 EMDECL(uint32_t) EMEmulateBts(void *pvParam1, uint64_t u64Param2);
    346 EMDECL(uint32_t) EMEmulateBtc(void *pvParam1, uint64_t u64Param2);
    347 EMDECL(uint32_t) EMEmulateCmpXchg(void *pvParam1, uint64_t *pu32Param2, uint64_t u32Param3, size_t cbSize);
    348 EMDECL(uint32_t) EMEmulateLockCmpXchg(void *pvParam1, uint64_t *pu64Param2, uint64_t u64Param3, size_t cbSize);
    349 EMDECL(uint32_t) EMEmulateCmpXchg8b32(RTHCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
    350 EMDECL(uint32_t) EMEmulateLockCmpXchg8b(RTHCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
    351 EMDECL(int)      EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame);
    352 EMDECL(int)      EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame);
     119EMDECL(int)         EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr);
     120EMDECL(int)         EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
     121                                          PDISCPUSTATE pCpu, unsigned *pcbInstr);
     122EMDECL(int)         EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
     123EMDECL(int)         EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
     124EMDECL(int)         EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame);
     125EMDECL(int)         EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame);
     126EMDECL(int)         EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
     127EMDECL(int)         EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame);
     128EMDECL(int)         EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
     129EMDECL(int)         EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
     130EMDECL(int)         EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
     131EMDECL(int)         EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
     132EMDECL(int)         EMInterpretLMSW(PVM pVM, uint16_t u16Data);
     133EMDECL(int)         EMInterpretCLTS(PVM pVM);
     134EMDECL(int)         EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp);
     135EMDECL(int)         EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame);
     136EMDECL(int)         EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame);
     137EMDECL(void)        EMFlushREMTBs(PVM pVM);
     138
     139/** @name Assembly routines
     140 * @{ */
     141EMDECL(uint32_t)    EMEmulateCmp(uint32_t u32Param1, uint64_t u64Param2, size_t cb);
     142EMDECL(uint32_t)    EMEmulateAnd(void *pvParam1, uint64_t u64Param2, size_t cb);
     143EMDECL(uint32_t)    EMEmulateInc(void *pvParam1, size_t cb);
     144EMDECL(uint32_t)    EMEmulateDec(void *pvParam1, size_t cb);
     145EMDECL(uint32_t)    EMEmulateOr(void *pvParam1, uint64_t u64Param2, size_t cb);
     146EMDECL(int)         EMEmulateLockOr(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
     147EMDECL(uint32_t)    EMEmulateXor(void *pvParam1, uint64_t u64Param2, size_t cb);
     148EMDECL(uint32_t)    EMEmulateAdd(void *pvParam1, uint64_t u64Param2, size_t cb);
     149EMDECL(uint32_t)    EMEmulateSub(void *pvParam1, uint64_t u64Param2, size_t cb);
     150EMDECL(uint32_t)    EMEmulateAdcWithCarrySet(void *pvParam1, uint64_t u64Param2, size_t cb);
     151EMDECL(uint32_t)    EMEmulateBtr(void *pvParam1, uint64_t u64Param2);
     152EMDECL(int)         EMEmulateLockBtr(void *pvParam1, uint64_t u64Param2, RTGCUINTREG32 *pf);
     153EMDECL(uint32_t)    EMEmulateBts(void *pvParam1, uint64_t u64Param2);
     154EMDECL(uint32_t)    EMEmulateBtc(void *pvParam1, uint64_t u64Param2);
     155EMDECL(uint32_t)    EMEmulateCmpXchg(void *pvParam1, uint64_t *pu32Param2, uint64_t u32Param3, size_t cbSize);
     156EMDECL(uint32_t)    EMEmulateLockCmpXchg(void *pvParam1, uint64_t *pu64Param2, uint64_t u64Param3, size_t cbSize);
     157EMDECL(uint32_t)    EMEmulateCmpXchg8b32(RTHCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
     158EMDECL(uint32_t)    EMEmulateLockCmpXchg8b(RTHCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
     159/** @} */
    353160
    354161#ifdef IN_RING3
    … …  
    357164 * @{
    358165 */
    359 
    360 /**
    361  * Initializes the EM.
    362  *
    363  * @returns VBox status code.
    364  * @param   pVM         The VM to operate on.
    365  */
    366 EMR3DECL(int) EMR3Init(PVM pVM);
    367 
    368 /**
    369  * Applies relocations to data and code managed by this
    370  * component. This function will be called at init and
    371  * whenever the VMM need to relocate it self inside the GC.
    372  *
    373  * @param   pVM     The VM.
    374  */
    375 EMR3DECL(void) EMR3Relocate(PVM pVM);
    376 
    377 /**
    378  * Reset notification.
    379  *
    380  * @param   pVM
    381  */
    382 EMR3DECL(void) EMR3Reset(PVM pVM);
    383 
    384 /**
    385  * Terminates the EM.
    386  *
    387  * Termination means cleaning up and freeing all resources,
    388  * the VM it self is at this point powered off or suspended.
    389  *
    390  * @returns VBox status code.
    391  * @param   pVM         The VM to operate on.
    392  */
    393 EMR3DECL(int) EMR3Term(PVM pVM);
    394 
     166EMR3DECL(int)       EMR3Init(PVM pVM);
     167EMR3DECL(void)      EMR3Relocate(PVM pVM);
     168EMR3DECL(void)      EMR3Reset(PVM pVM);
     169EMR3DECL(int)       EMR3Term(PVM pVM);
     170EMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVM pVM, int rc);
     171EMR3DECL(int)       EMR3ExecuteVM(PVM pVM);
     172EMR3DECL(int)       EMR3CheckRawForcedActions(PVM pVM);
     173EMR3DECL(int)       EMR3Interpret(PVM pVM);
    395174
    396175/**
    … …  
    415194} EMRAWMODE;
    416195
    417 /**
    418  * Enables or disables a set of raw-mode execution modes.
    419  *
    420  * @returns VINF_SUCCESS on success.
    421  * @returns VINF_RESCHEDULE if a rescheduling might be required.
    422  * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
    423  *
    424  * @param   pVM         The VM to operate on.
    425  * @param   enmMode     The execution mode change.
    426  * @thread  The emulation thread.
    427  */
    428 EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode);
    429 
    430 /**
    431  * Raise a fatal error.
    432  *
    433  * Safely terminate the VM with full state report and stuff. This function
    434  * will naturally never return.
    435  *
    436  * @param   pVM         VM handle.
    437  * @param   rc          VBox status code.
    438  */
    439 EMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVM pVM, int rc);
    440 
    441 /**
    442  * Execute VM
    443  *
    444  * This function is the main loop of the VM. The emulation thread
    445  * calls this function when the VM has been successfully constructed
    446  * and we're ready for executing the VM.
    447  *
    448  * Returning from this function means that the VM is turned off or
    449  * suspended (state already saved) and deconstruction in next in line.
    450  *
    451  * @returns VBox status code.
    452  * @param   pVM         The VM to operate on.
    453  */
    454 EMR3DECL(int) EMR3ExecuteVM(PVM pVM);
    455 
    456 /**
    457  * Check for pending raw actions
    458  *
    459  * @returns VBox status code.
    460  * @param   pVM         The VM to operate on.
    461  */
    462 EMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM);
    463 
    464 /**
    465  * Interpret instructions.
    466  * This works directly on the Guest CPUM context.
    467  * The interpretation will try execute at least one instruction. It will
    468  * stop when a we're better off in a raw or recompiler mode.
    469  *
    470  * @returns Todo - status describing what to do next?
    471  * @param   pVM         The VM to operate on.
    472  */
    473 EMR3DECL(int) EMR3Interpret(PVM pVM);
    474 
    475 /** @} */
    476 #endif
     196EMR3DECL(int)       EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode);
     197/** @} */
     198#endif /* IN_RING3 */
    477199
    478200
    … …  
    482204 * @{
    483205 */
    484 
    485 /**
    486  * Decide what to do with a trap.
    487  *
    488  * @returns Next VMM state.
    489  * @returns Might not return at all?
    490  * @param   pVM         The VM to operate on.
    491  * @param   uTrap       The trap number.
    492  * @param   pRegFrame   Register frame to operate on.
    493  */
    494 EMGCDECL(int) EMGCTrap(PVM pVM, unsigned uTrap, PCPUMCTXCORE pRegFrame);
    495 
    496 EMGCDECL(uint32_t) EMGCEmulateLockCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
    497 EMGCDECL(uint32_t) EMGCEmulateCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
    498 EMGCDECL(uint32_t) EMGCEmulateLockCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
    499 EMGCDECL(uint32_t) EMGCEmulateCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
    500 EMGCDECL(uint32_t) EMGCEmulateLockXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
    501 EMGCDECL(uint32_t) EMGCEmulateXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
    502 
    503 /** @} */
     206EMGCDECL(int)       EMGCTrap(PVM pVM, unsigned uTrap, PCPUMCTXCORE pRegFrame);
     207EMGCDECL(uint32_t)  EMGCEmulateLockCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
     208EMGCDECL(uint32_t)  EMGCEmulateCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
     209EMGCDECL(uint32_t)  EMGCEmulateLockCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
     210EMGCDECL(uint32_t)  EMGCEmulateCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
     211EMGCDECL(uint32_t)  EMGCEmulateLockXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
     212EMGCDECL(uint32_t)  EMGCEmulateXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
     213/** @} */
     214#endif /* IN_GC */
     215
     216/** @} */
     217
     218__END_DECLS
     219
    504220#endif
    505221
    506 /** @} */
    507 
    508 __END_DECLS
    509 
    510 #endif
    511 
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